Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 | Date : Wed Jul 8 03:34:10 2026 | Host : fedora running 64-bit unknown | Command : report_timing_summary -delay_type max -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/vivado_reports_nodsp/timing_summary_full.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 38 input ports with no input delay specified. (HIGH) UART_RX UART_TX dip_sw[0] dip_sw[10] dip_sw[11] dip_sw[12] dip_sw[13] dip_sw[14] dip_sw[15] dip_sw[16] dip_sw[17] dip_sw[18] dip_sw[19] dip_sw[1] dip_sw[20] dip_sw[21] dip_sw[22] dip_sw[23] dip_sw[24] dip_sw[25] dip_sw[26] dip_sw[27] dip_sw[28] dip_sw[29] dip_sw[2] dip_sw[30] dip_sw[31] dip_sw[3] dip_sw[4] dip_sw[5] dip_sw[6] dip_sw[7] dip_sw[8] dip_sw[9] touch_btn[0] touch_btn[1] touch_btn[2] touch_btn[3] There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 40 ports with no output delay specified. (HIGH) UART_RX UART_TX dpy0[0] dpy0[1] dpy0[2] dpy0[3] dpy0[4] dpy0[5] dpy0[6] dpy0[7] dpy1[0] dpy1[1] dpy1[2] dpy1[3] dpy1[4] dpy1[5] dpy1[6] dpy1[7] leds[0] leds[10] leds[11] leds[12] leds[13] leds[14] leds[15] leds[1] leds[2] leds[3] leds[4] leds[5] leds[6] leds[7] leds[8] leds[9] video_de video_hsync video_red[0] video_red[1] video_red[2] video_vsync There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.167 0.000 0 115177 7.000 0.000 0 42610 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk {0.000 10.000} 20.000 50.000 clkfbout_clk_pll {0.000 10.000} 20.000 50.000 cpu_clk {0.000 15.161} 30.323 32.979 mlkem_clk_clk_pll {0.000 20.000} 40.000 25.000 sys_clk {0.000 10.000} 20.000 50.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk 7.000 0.000 0 1 clkfbout_clk_pll 17.845 0.000 0 3 cpu_clk 2.716 0.000 0 17197 13.911 0.000 0 6486 mlkem_clk_clk_pll 10.807 0.000 0 48474 18.750 0.000 0 26131 sys_clk 0.167 0.000 0 22818 8.750 0.000 0 9989 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- sys_clk mlkem_clk_clk_pll 14.363 0.000 0 108 mlkem_clk_clk_pll sys_clk 16.175 0.000 0 59 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- **async_default** cpu_clk cpu_clk 25.793 0.000 0 67 **async_default** mlkem_clk_clk_pll mlkem_clk_clk_pll 23.497 0.000 0 25694 **async_default** sys_clk mlkem_clk_clk_pll 9.156 0.000 0 4 **async_default** mlkem_clk_clk_pll sys_clk 11.249 0.000 0 2 **async_default** sys_clk sys_clk 4.581 0.000 0 886 ------------------------------------------------------------------------------------------------ | User Ignored Path Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) sys_clk cpu_clk (none) cpu_clk sys_clk ------------------------------------------------------------------------------------------------ | Unconstrained Path Table | ------------------------ ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) clkfbout_clk_pll (none) sys_clk (none) sys_clk ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk To Clock: clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { clk } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_pll To Clock: clkfbout_clk_pll Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_pll Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y19 pll_clk.u_clk_pll/inst/clkf_buf/I Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: cpu_clk To Clock: cpu_clk Setup : 0 Failing Endpoints, Worst Slack 2.716ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.716ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][13]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] ------------------------------------------------------------------- required time 27.473 arrival time -24.757 ------------------------------------------------------------------- slack 2.716 Slack (MET) : 2.716ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][14]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] ------------------------------------------------------------------- required time 27.473 arrival time -24.757 ------------------------------------------------------------------- slack 2.716 Slack (MET) : 2.716ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][15]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] ------------------------------------------------------------------- required time 27.473 arrival time -24.757 ------------------------------------------------------------------- slack 2.716 Slack (MET) : 2.716ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][16]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] ------------------------------------------------------------------- required time 27.473 arrival time -24.757 ------------------------------------------------------------------- slack 2.716 Slack (MET) : 2.716ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][1]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] ------------------------------------------------------------------- required time 27.473 arrival time -24.757 ------------------------------------------------------------------- slack 2.716 Slack (MET) : 2.716ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][28]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] ------------------------------------------------------------------- required time 27.473 arrival time -24.757 ------------------------------------------------------------------- slack 2.716 Slack (MET) : 2.751ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/C clock pessimism -0.498 27.875 clock uncertainty -0.074 27.801 SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] ------------------------------------------------------------------- required time 27.878 arrival time -25.127 ------------------------------------------------------------------- slack 2.751 Slack (MET) : 2.754ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: 0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.966 28.460 u_cpu/exe_stage/cpu_clk SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/C clock pessimism -0.498 27.962 clock uncertainty -0.074 27.888 SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] ------------------------------------------------------------------- required time 27.919 arrival time -25.165 ------------------------------------------------------------------- slack 2.754 Slack (MET) : 2.789ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.975 28.469 u_cpu/exe_stage/cpu_clk SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/C clock pessimism -0.498 27.971 clock uncertainty -0.074 27.897 SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 27.928 arrival time -25.138 ------------------------------------------------------------------- slack 2.789 Slack (MET) : 2.822ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.885 28.379 u_cpu/exe_stage/cpu_clk SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/C clock pessimism -0.498 27.881 clock uncertainty -0.074 27.807 SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] ------------------------------------------------------------------- required time 27.836 arrival time -25.013 ------------------------------------------------------------------- slack 2.822 Slack (MET) : 2.959ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.468ns (logic 7.073ns (25.750%) route 20.395ns (74.250%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.780 22.220 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I0_O) 0.124 22.344 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 1.068 23.412 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 SLICE_X45Y35 LUT4 (Prop_lut4_I2_O) 0.150 23.562 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O net (fo=1, routed) 1.078 24.640 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 SLICE_X39Y34 LUT6 (Prop_lut6_I1_O) 0.326 24.966 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O net (fo=1, routed) 0.000 24.966 u_cpu/exe_stage/ds_to_es_bus[118] SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.975 28.469 u_cpu/exe_stage/cpu_clk SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/C clock pessimism -0.498 27.971 clock uncertainty -0.074 27.897 SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.029 27.926 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] ------------------------------------------------------------------- required time 27.926 arrival time -24.966 ------------------------------------------------------------------- slack 2.959 Slack (MET) : 3.081ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.303ns (logic 7.073ns (25.905%) route 20.230ns (74.095%)) Logic Levels: 32 (CARRY4=5 LUT3=2 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.945ns = ( 28.378 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.096 21.904 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X39Y31 LUT6 (Prop_lut6_I5_O) 0.124 22.028 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_19/O net (fo=4, routed) 0.942 22.969 u_cpu/id_stage/ds_to_es_bus_r[188]_i_19_n_0 SLICE_X43Y28 LUT3 (Prop_lut3_I2_O) 0.150 23.119 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_11/O net (fo=1, routed) 0.652 23.771 u_cpu/id_stage/ds_to_es_bus_r[181]_i_11_n_0 SLICE_X43Y28 LUT6 (Prop_lut6_I5_O) 0.326 24.097 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.581 24.678 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X46Y28 LUT6 (Prop_lut6_I3_O) 0.124 24.802 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 24.802 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X46Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.884 28.378 u_cpu/exe_stage/cpu_clk SLICE_X46Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/C clock pessimism -0.498 27.880 clock uncertainty -0.074 27.806 SLICE_X46Y28 FDRE (Setup_fdre_C_D) 0.077 27.883 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 27.883 arrival time -24.802 ------------------------------------------------------------------- slack 3.081 Slack (MET) : 3.101ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.282ns (logic 6.845ns (25.090%) route 20.437ns (74.910%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.619 22.058 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X41Y30 LUT6 (Prop_lut6_I0_O) 0.124 22.182 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O net (fo=15, routed) 1.068 23.250 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 SLICE_X43Y32 LUT4 (Prop_lut4_I2_O) 0.124 23.374 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_2/O net (fo=1, routed) 1.282 24.656 u_cpu/id_stage/ds_to_es_bus_r[176]_i_2_n_0 SLICE_X46Y24 LUT6 (Prop_lut6_I1_O) 0.124 24.780 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 24.780 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/C clock pessimism -0.498 27.875 clock uncertainty -0.074 27.801 SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.081 27.882 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 27.882 arrival time -24.780 ------------------------------------------------------------------- slack 3.101 Slack (MET) : 3.107ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.229ns (logic 6.845ns (25.138%) route 20.384ns (74.862%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: 0.057ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.947ns = ( 28.376 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O net (fo=32, routed) 1.277 23.041 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 SLICE_X51Y27 LUT4 (Prop_lut4_I2_O) 0.124 23.165 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_12/O net (fo=1, routed) 0.649 23.814 u_cpu/id_stage/ds_to_es_bus_r[186]_i_12_n_0 SLICE_X47Y27 LUT5 (Prop_lut5_I0_O) 0.124 23.938 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_5/O net (fo=1, routed) 0.666 24.604 u_cpu/id_stage/ds_to_es_bus_r[186]_i_5_n_0 SLICE_X45Y27 LUT6 (Prop_lut6_I4_O) 0.124 24.728 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O net (fo=1, routed) 0.000 24.728 u_cpu/exe_stage/ds_to_es_bus[136] SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.882 28.376 u_cpu/exe_stage/cpu_clk SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/C clock pessimism -0.498 27.878 clock uncertainty -0.074 27.804 SLICE_X45Y27 FDRE (Setup_fdre_C_D) 0.031 27.835 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] ------------------------------------------------------------------- required time 27.835 arrival time -24.728 ------------------------------------------------------------------- slack 3.107 Slack (MET) : 3.111ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.278ns (logic 6.845ns (25.094%) route 20.433ns (74.906%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.940ns = ( 28.383 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.127 22.946 u_cpu/id_stage/fs_to_ds_bus_r_reg[46]_0 SLICE_X48Y33 LUT4 (Prop_lut4_I0_O) 0.124 23.070 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O net (fo=1, routed) 0.656 23.726 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 SLICE_X46Y30 LUT6 (Prop_lut6_I1_O) 0.124 23.850 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 0.803 24.652 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X44Y33 LUT6 (Prop_lut6_I4_O) 0.124 24.776 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 24.776 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X44Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.889 28.383 u_cpu/exe_stage/cpu_clk SLICE_X44Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/C clock pessimism -0.498 27.885 clock uncertainty -0.074 27.811 SLICE_X44Y33 FDRE (Setup_fdre_C_D) 0.077 27.888 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 27.888 arrival time -24.776 ------------------------------------------------------------------- slack 3.111 Slack (MET) : 3.117ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.301ns (logic 7.095ns (25.988%) route 20.206ns (74.012%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.780 22.220 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I0_O) 0.124 22.344 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 0.883 23.227 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 SLICE_X44Y32 LUT2 (Prop_lut2_I1_O) 0.150 23.377 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O net (fo=1, routed) 1.075 24.452 u_cpu/id_stage/ds_to_es_bus_r_reg[171] SLICE_X41Y26 LUT6 (Prop_lut6_I2_O) 0.348 24.800 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O net (fo=1, routed) 0.000 24.800 u_cpu/exe_stage/ds_to_es_bus[121] SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.966 28.460 u_cpu/exe_stage/cpu_clk SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/C clock pessimism -0.498 27.962 clock uncertainty -0.074 27.888 SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.029 27.917 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] ------------------------------------------------------------------- required time 27.917 arrival time -24.800 ------------------------------------------------------------------- slack 3.117 Slack (MET) : 3.132ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.293ns (logic 7.073ns (25.915%) route 20.220ns (74.085%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: 0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.818 22.446 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X40Y24 LUT5 (Prop_lut5_I0_O) 0.326 22.772 r u_cpu/u_csr/ds_to_es_bus_r[187]_i_11/O net (fo=1, routed) 0.976 23.747 u_cpu/id_stage/ds_to_es_bus_r_reg[187]_0 SLICE_X40Y30 LUT4 (Prop_lut4_I2_O) 0.124 23.871 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O net (fo=1, routed) 0.796 24.668 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 SLICE_X41Y31 LUT6 (Prop_lut6_I4_O) 0.124 24.792 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 24.792 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X41Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.971 28.465 u_cpu/exe_stage/cpu_clk SLICE_X41Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/C clock pessimism -0.498 27.967 clock uncertainty -0.074 27.893 SLICE_X41Y31 FDRE (Setup_fdre_C_D) 0.031 27.924 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 27.924 arrival time -24.792 ------------------------------------------------------------------- slack 3.132 Slack (MET) : 3.146ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.188ns (logic 6.949ns (25.559%) route 20.239ns (74.441%)) Logic Levels: 31 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.847 20.893 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y30 LUT5 (Prop_lut5_I2_O) 0.124 21.017 f u_cpu/id_stage/ds_to_es_bus_r[183]_i_15/O net (fo=8, routed) 1.169 22.186 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_1 SLICE_X44Y30 LUT2 (Prop_lut2_I1_O) 0.148 22.334 f u_cpu/id_stage/ds_to_es_bus_r[183]_i_12/O net (fo=6, routed) 0.893 23.226 u_cpu/id_stage/ds_to_es_bus_r[183]_i_12_n_0 SLICE_X41Y29 LUT6 (Prop_lut6_I3_O) 0.328 23.554 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_3/O net (fo=1, routed) 1.008 24.562 u_cpu/id_stage/ds_to_es_bus_r[180]_i_3_n_0 SLICE_X43Y26 LUT6 (Prop_lut6_I2_O) 0.124 24.686 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O net (fo=1, routed) 0.000 24.686 u_cpu/exe_stage/ds_to_es_bus[130] SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C clock pessimism -0.498 27.875 clock uncertainty -0.074 27.801 SLICE_X43Y26 FDRE (Setup_fdre_C_D) 0.032 27.833 u_cpu/exe_stage/ds_to_es_bus_r_reg[180] ------------------------------------------------------------------- required time 27.833 arrival time -24.686 ------------------------------------------------------------------- slack 3.146 Slack (MET) : 3.154ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.182ns (logic 6.845ns (25.182%) route 20.337ns (74.818%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.057ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.947ns = ( 28.376 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.745 21.553 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X39Y30 LUT6 (Prop_lut6_I3_O) 0.124 21.677 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.325 23.002 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X46Y27 LUT4 (Prop_lut4_I0_O) 0.124 23.126 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_10/O net (fo=1, routed) 0.502 23.627 u_cpu/id_stage/ds_to_es_bus_r[185]_i_10_n_0 SLICE_X46Y27 LUT6 (Prop_lut6_I5_O) 0.124 23.751 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_4/O net (fo=1, routed) 0.805 24.556 u_cpu/id_stage/ds_to_es_bus_r[185]_i_4_n_0 SLICE_X45Y27 LUT6 (Prop_lut6_I3_O) 0.124 24.680 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O net (fo=1, routed) 0.000 24.680 u_cpu/exe_stage/ds_to_es_bus[135] SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.882 28.376 u_cpu/exe_stage/cpu_clk SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/C clock pessimism -0.498 27.878 clock uncertainty -0.074 27.804 SLICE_X45Y27 FDRE (Setup_fdre_C_D) 0.031 27.835 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] ------------------------------------------------------------------- required time 27.835 arrival time -24.680 ------------------------------------------------------------------- slack 3.154 Slack (MET) : 3.179ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.162ns (logic 6.845ns (25.201%) route 20.317ns (74.799%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.940ns = ( 28.383 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.745 21.553 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X39Y30 LUT6 (Prop_lut6_I3_O) 0.124 21.677 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.184 22.860 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X46Y31 LUT4 (Prop_lut4_I0_O) 0.124 22.984 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_13/O net (fo=1, routed) 0.785 23.769 u_cpu/id_stage/ds_to_es_bus_r[189]_i_13_n_0 SLICE_X47Y33 LUT6 (Prop_lut6_I5_O) 0.124 23.893 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_4/O net (fo=1, routed) 0.643 24.536 u_cpu/id_stage/ds_to_es_bus_r[189]_i_4_n_0 SLICE_X47Y33 LUT6 (Prop_lut6_I3_O) 0.124 24.660 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O net (fo=1, routed) 0.000 24.660 u_cpu/exe_stage/ds_to_es_bus[139] SLICE_X47Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.889 28.383 u_cpu/exe_stage/cpu_clk SLICE_X47Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/C clock pessimism -0.498 27.885 clock uncertainty -0.074 27.811 SLICE_X47Y33 FDRE (Setup_fdre_C_D) 0.029 27.840 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] ------------------------------------------------------------------- required time 27.840 arrival time -24.660 ------------------------------------------------------------------- slack 3.179 Slack (MET) : 3.179ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.160ns (logic 7.073ns (26.042%) route 20.087ns (73.958%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: 0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 1.194 22.822 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X50Y28 LUT6 (Prop_lut6_I0_O) 0.326 23.148 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.700 23.848 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X47Y30 LUT6 (Prop_lut6_I2_O) 0.124 23.972 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.562 24.534 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X45Y29 LUT5 (Prop_lut5_I1_O) 0.124 24.658 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 24.658 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.885 28.379 u_cpu/exe_stage/cpu_clk SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/C clock pessimism -0.498 27.881 clock uncertainty -0.074 27.807 SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.031 27.838 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 27.838 arrival time -24.658 ------------------------------------------------------------------- slack 3.179 Slack (MET) : 3.222ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.251ns (logic 6.845ns (25.118%) route 20.406ns (74.882%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O net (fo=32, routed) 0.885 22.649 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 SLICE_X39Y35 LUT4 (Prop_lut4_I2_O) 0.124 22.773 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_9/O net (fo=1, routed) 1.128 23.901 u_cpu/id_stage/ds_to_es_bus_r[162]_i_9_n_0 SLICE_X39Y33 LUT6 (Prop_lut6_I2_O) 0.124 24.025 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_4/O net (fo=1, routed) 0.600 24.625 u_cpu/id_stage/ds_to_es_bus_r[162]_i_4_n_0 SLICE_X40Y32 LUT6 (Prop_lut6_I2_O) 0.124 24.749 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_1/O net (fo=1, routed) 0.000 24.749 u_cpu/exe_stage/ds_to_es_bus[112] SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/C clock pessimism -0.498 27.969 clock uncertainty -0.074 27.895 SLICE_X40Y32 FDRE (Setup_fdre_C_D) 0.077 27.972 u_cpu/exe_stage/ds_to_es_bus_r_reg[162] ------------------------------------------------------------------- required time 27.972 arrival time -24.749 ------------------------------------------------------------------- slack 3.222 Slack (MET) : 3.225ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.158ns (logic 6.845ns (25.204%) route 20.313ns (74.796%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.946ns = ( 28.377 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.499 21.307 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X40Y29 LUT5 (Prop_lut5_I4_O) 0.124 21.431 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 1.248 22.679 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X48Y34 LUT4 (Prop_lut4_I2_O) 0.124 22.803 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_8/O net (fo=1, routed) 0.983 23.787 u_cpu/id_stage/ds_to_es_bus_r[163]_i_8_n_0 SLICE_X42Y34 LUT6 (Prop_lut6_I0_O) 0.124 23.911 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_4/O net (fo=1, routed) 0.622 24.533 u_cpu/id_stage/ds_to_es_bus_r[163]_i_4_n_0 SLICE_X42Y29 LUT6 (Prop_lut6_I3_O) 0.124 24.657 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_1/O net (fo=1, routed) 0.000 24.657 u_cpu/exe_stage/ds_to_es_bus[113] SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.883 28.377 u_cpu/exe_stage/cpu_clk SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/C clock pessimism -0.498 27.879 clock uncertainty -0.074 27.805 SLICE_X42Y29 FDRE (Setup_fdre_C_D) 0.077 27.882 u_cpu/exe_stage/ds_to_es_bus_r_reg[163] ------------------------------------------------------------------- required time 27.882 arrival time -24.657 ------------------------------------------------------------------- slack 3.225 Slack (MET) : 3.228ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.103ns (logic 7.041ns (25.978%) route 20.062ns (74.021%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.499 21.307 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X40Y29 LUT5 (Prop_lut5_I4_O) 0.124 21.431 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 0.831 22.262 u_cpu/u_csr/ds_to_es_bus_r[166]_i_4_0 SLICE_X45Y31 LUT2 (Prop_lut2_I1_O) 0.118 22.380 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_8/O net (fo=1, routed) 0.965 23.345 u_cpu/u_csr/ds_to_es_bus_r[165]_i_8_n_0 SLICE_X42Y28 LUT6 (Prop_lut6_I0_O) 0.326 23.671 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.806 24.478 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X43Y26 LUT6 (Prop_lut6_I3_O) 0.124 24.602 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 24.602 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/C clock pessimism -0.498 27.875 clock uncertainty -0.074 27.801 SLICE_X43Y26 FDRE (Setup_fdre_C_D) 0.029 27.830 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 27.830 arrival time -24.602 ------------------------------------------------------------------- slack 3.228 Slack (MET) : 3.306ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.027ns (logic 6.845ns (25.326%) route 20.182ns (74.674%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O net (fo=32, routed) 1.269 23.016 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 SLICE_X50Y27 LUT4 (Prop_lut4_I0_O) 0.124 23.140 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_11/O net (fo=1, routed) 0.487 23.627 u_cpu/id_stage/ds_to_es_bus_r[174]_i_11_n_0 SLICE_X45Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.751 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_4/O net (fo=1, routed) 0.651 24.402 u_cpu/id_stage/ds_to_es_bus_r[174]_i_4_n_0 SLICE_X43Y26 LUT6 (Prop_lut6_I3_O) 0.124 24.526 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 24.526 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/C clock pessimism -0.498 27.875 clock uncertainty -0.074 27.801 SLICE_X43Y26 FDRE (Setup_fdre_C_D) 0.031 27.832 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 27.832 arrival time -24.526 ------------------------------------------------------------------- slack 3.306 Slack (MET) : 3.315ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.066ns (logic 6.845ns (25.290%) route 20.221ns (74.710%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.948ns = ( 28.375 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.494 21.302 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X38Y28 LUT6 (Prop_lut6_I5_O) 0.124 21.426 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_12/O net (fo=11, routed) 1.101 22.527 u_cpu/id_stage/ds_to_es_bus_r[178]_i_12_n_0 SLICE_X46Y22 LUT5 (Prop_lut5_I2_O) 0.124 22.651 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_10/O net (fo=1, routed) 0.985 23.636 u_cpu/id_stage/ds_to_es_bus_r[178]_i_10_n_0 SLICE_X46Y26 LUT6 (Prop_lut6_I2_O) 0.124 23.760 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O net (fo=1, routed) 0.680 24.440 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 SLICE_X46Y26 LUT6 (Prop_lut6_I3_O) 0.124 24.564 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 24.564 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X46Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.881 28.375 u_cpu/exe_stage/cpu_clk SLICE_X46Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/C clock pessimism -0.498 27.877 clock uncertainty -0.074 27.803 SLICE_X46Y26 FDRE (Setup_fdre_C_D) 0.077 27.880 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 27.880 arrival time -24.564 ------------------------------------------------------------------- slack 3.315 Slack (MET) : 3.348ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.129ns (logic 6.845ns (25.231%) route 20.284ns (74.769%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: 0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O net (fo=32, routed) 1.318 23.065 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 SLICE_X44Y31 LUT4 (Prop_lut4_I0_O) 0.124 23.189 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_7/O net (fo=1, routed) 0.553 23.742 u_cpu/id_stage/ds_to_es_bus_r[166]_i_7_n_0 SLICE_X40Y31 LUT5 (Prop_lut5_I0_O) 0.124 23.866 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_3/O net (fo=1, routed) 0.638 24.504 u_cpu/id_stage/ds_to_es_bus_r[166]_i_3_n_0 SLICE_X40Y32 LUT6 (Prop_lut6_I2_O) 0.124 24.628 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_1/O net (fo=1, routed) 0.000 24.628 u_cpu/exe_stage/ds_to_es_bus[116] SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/C clock pessimism -0.498 27.969 clock uncertainty -0.074 27.895 SLICE_X40Y32 FDRE (Setup_fdre_C_D) 0.081 27.976 u_cpu/exe_stage/ds_to_es_bus_r_reg[166] ------------------------------------------------------------------- required time 27.976 arrival time -24.628 ------------------------------------------------------------------- slack 3.348 Slack (MET) : 3.380ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.001ns (logic 6.845ns (25.351%) route 20.156ns (74.649%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.619 22.058 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X41Y30 LUT6 (Prop_lut6_I0_O) 0.124 22.182 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O net (fo=15, routed) 1.094 23.277 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 SLICE_X47Y33 LUT6 (Prop_lut6_I5_O) 0.124 23.401 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_2/O net (fo=1, routed) 0.974 24.375 u_cpu/id_stage/ds_to_es_bus_r[179]_i_2_n_0 SLICE_X46Y24 LUT5 (Prop_lut5_I1_O) 0.124 24.499 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_1/O net (fo=1, routed) 0.000 24.499 u_cpu/exe_stage/ds_to_es_bus[129] SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/C clock pessimism -0.498 27.875 clock uncertainty -0.074 27.801 SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.079 27.880 u_cpu/exe_stage/ds_to_es_bus_r_reg[179] ------------------------------------------------------------------- required time 27.880 arrival time -24.499 ------------------------------------------------------------------- slack 3.380 Slack (MET) : 3.393ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][10]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: 0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][10]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][10]/C clock pessimism -0.498 27.911 clock uncertainty -0.074 27.837 SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][10] ------------------------------------------------------------------- required time 27.632 arrival time -24.239 ------------------------------------------------------------------- slack 3.393 Slack (MET) : 3.393ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][18]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: 0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][18]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][18]/C clock pessimism -0.498 27.911 clock uncertainty -0.074 27.837 SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][18] ------------------------------------------------------------------- required time 27.632 arrival time -24.239 ------------------------------------------------------------------- slack 3.393 Slack (MET) : 3.393ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][23]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: 0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][23]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][23]/C clock pessimism -0.498 27.911 clock uncertainty -0.074 27.837 SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][23] ------------------------------------------------------------------- required time 27.632 arrival time -24.239 ------------------------------------------------------------------- slack 3.393 Slack (MET) : 3.393ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][27]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: 0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][27]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][27]/C clock pessimism -0.498 27.911 clock uncertainty -0.074 27.837 SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][27] ------------------------------------------------------------------- required time 27.632 arrival time -24.239 ------------------------------------------------------------------- slack 3.393 Slack (MET) : 3.408ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.974ns (logic 7.073ns (26.222%) route 19.901ns (73.778%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: 0.057ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.947ns = ( 28.376 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 1.025 22.652 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X45Y28 LUT5 (Prop_lut5_I0_O) 0.326 22.978 r u_cpu/u_csr/ds_to_es_bus_r[182]_i_8/O net (fo=1, routed) 0.653 23.631 u_cpu/id_stage/ds_to_es_bus_r_reg[182] SLICE_X44Y28 LUT6 (Prop_lut6_I1_O) 0.124 23.755 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_2/O net (fo=1, routed) 0.593 24.348 u_cpu/id_stage/ds_to_es_bus_r[182]_i_2_n_0 SLICE_X44Y27 LUT6 (Prop_lut6_I1_O) 0.124 24.472 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_1/O net (fo=1, routed) 0.000 24.472 u_cpu/exe_stage/ds_to_es_bus[132] SLICE_X44Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.882 28.376 u_cpu/exe_stage/cpu_clk SLICE_X44Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/C clock pessimism -0.498 27.878 clock uncertainty -0.074 27.804 SLICE_X44Y27 FDRE (Setup_fdre_C_D) 0.077 27.881 u_cpu/exe_stage/ds_to_es_bus_r_reg[182] ------------------------------------------------------------------- required time 27.881 arrival time -24.472 ------------------------------------------------------------------- slack 3.408 Slack (MET) : 3.421ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][29]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: 0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][29]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][29]/C clock pessimism -0.498 27.911 clock uncertainty -0.074 27.837 SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][29] ------------------------------------------------------------------- required time 27.632 arrival time -24.210 ------------------------------------------------------------------- slack 3.421 Slack (MET) : 3.421ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][2]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: 0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][2]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][2]/C clock pessimism -0.498 27.911 clock uncertainty -0.074 27.837 SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][2] ------------------------------------------------------------------- required time 27.632 arrival time -24.210 ------------------------------------------------------------------- slack 3.421 Slack (MET) : 3.421ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][4]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: 0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][4]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][4]/C clock pessimism -0.498 27.911 clock uncertainty -0.074 27.837 SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][4] ------------------------------------------------------------------- required time 27.632 arrival time -24.210 ------------------------------------------------------------------- slack 3.421 Slack (MET) : 3.421ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][7]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: 0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][7]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][7]/C clock pessimism -0.498 27.911 clock uncertainty -0.074 27.837 SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][7] ------------------------------------------------------------------- required time 27.632 arrival time -24.210 ------------------------------------------------------------------- slack 3.421 Slack (MET) : 3.432ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.954ns (logic 7.073ns (26.241%) route 19.881ns (73.759%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.943ns = ( 28.380 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 1.175 22.803 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X47Y31 LUT4 (Prop_lut4_I3_O) 0.326 23.129 r u_cpu/u_csr/ds_to_es_bus_r[188]_i_12/O net (fo=1, routed) 0.667 23.796 u_cpu/id_stage/ds_to_es_bus_r_reg[188] SLICE_X47Y31 LUT6 (Prop_lut6_I1_O) 0.124 23.920 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_5/O net (fo=1, routed) 0.409 24.329 u_cpu/id_stage/ds_to_es_bus_r[188]_i_5_n_0 SLICE_X48Y31 LUT6 (Prop_lut6_I4_O) 0.124 24.453 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_1/O net (fo=1, routed) 0.000 24.453 u_cpu/exe_stage/ds_to_es_bus[138] SLICE_X48Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.886 28.380 u_cpu/exe_stage/cpu_clk SLICE_X48Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/C clock pessimism -0.498 27.882 clock uncertainty -0.074 27.808 SLICE_X48Y31 FDRE (Setup_fdre_C_D) 0.077 27.885 u_cpu/exe_stage/ds_to_es_bus_r_reg[188] ------------------------------------------------------------------- required time 27.885 arrival time -24.453 ------------------------------------------------------------------- slack 3.432 Slack (MET) : 3.450ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.937ns (logic 7.073ns (26.257%) route 19.864ns (73.743%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.946ns = ( 28.377 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.952 22.579 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X42Y24 LUT5 (Prop_lut5_I1_O) 0.326 22.905 r u_cpu/u_csr/ds_to_es_bus_r[192]_i_9/O net (fo=1, routed) 0.483 23.388 u_cpu/id_stage/ds_to_es_bus_r_reg[192] SLICE_X42Y27 LUT4 (Prop_lut4_I3_O) 0.124 23.512 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_3/O net (fo=1, routed) 0.800 24.312 u_cpu/id_stage/ds_to_es_bus_r[192]_i_3_n_0 SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 24.436 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_1/O net (fo=1, routed) 0.000 24.436 u_cpu/exe_stage/ds_to_es_bus[142] SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.883 28.377 u_cpu/exe_stage/cpu_clk SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/C clock pessimism -0.498 27.879 clock uncertainty -0.074 27.805 SLICE_X42Y29 FDRE (Setup_fdre_C_D) 0.081 27.886 u_cpu/exe_stage/ds_to_es_bus_r_reg[192] ------------------------------------------------------------------- required time 27.886 arrival time -24.436 ------------------------------------------------------------------- slack 3.450 Slack (MET) : 3.466ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[21][13]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][13]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][13]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][13] ------------------------------------------------------------------- required time 27.235 arrival time -23.769 ------------------------------------------------------------------- slack 3.466 Slack (MET) : 3.466ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[21][15]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][15]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][15]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][15] ------------------------------------------------------------------- required time 27.235 arrival time -23.769 ------------------------------------------------------------------- slack 3.466 Slack (MET) : 3.466ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[21][17]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][17]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][17]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][17] ------------------------------------------------------------------- required time 27.235 arrival time -23.769 ------------------------------------------------------------------- slack 3.466 Slack (MET) : 3.466ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[21][21]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][21]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][21]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][21] ------------------------------------------------------------------- required time 27.235 arrival time -23.769 ------------------------------------------------------------------- slack 3.466 Slack (MET) : 3.466ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[21][3]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][3]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][3]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][3] ------------------------------------------------------------------- required time 27.235 arrival time -23.769 ------------------------------------------------------------------- slack 3.466 Slack (MET) : 3.466ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[21][4]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][4]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][4]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][4] ------------------------------------------------------------------- required time 27.235 arrival time -23.769 ------------------------------------------------------------------- slack 3.466 Slack (MET) : 3.466ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[21][6]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][6]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][6]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][6] ------------------------------------------------------------------- required time 27.235 arrival time -23.769 ------------------------------------------------------------------- slack 3.466 Slack (MET) : 3.466ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[21][7]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][7]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][7]/C clock pessimism -0.498 27.716 clock uncertainty -0.074 27.642 SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][7] ------------------------------------------------------------------- required time 27.235 arrival time -23.769 ------------------------------------------------------------------- slack 3.466 Slack (MET) : 3.472ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.860ns (logic 6.845ns (25.484%) route 20.015ns (74.516%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.494 21.302 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X38Y28 LUT6 (Prop_lut6_I5_O) 0.124 21.426 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_12/O net (fo=11, routed) 1.266 22.692 u_cpu/id_stage/ds_to_es_bus_r[178]_i_12_n_0 SLICE_X45Y19 LUT5 (Prop_lut5_I4_O) 0.124 22.816 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_7/O net (fo=1, routed) 0.650 23.467 u_cpu/id_stage/ds_to_es_bus_r[169]_i_7_n_0 SLICE_X45Y24 LUT5 (Prop_lut5_I2_O) 0.124 23.591 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_3/O net (fo=1, routed) 0.643 24.234 u_cpu/id_stage/ds_to_es_bus_r[169]_i_3_n_0 SLICE_X45Y24 LUT6 (Prop_lut6_I2_O) 0.124 24.358 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_1/O net (fo=1, routed) 0.000 24.358 u_cpu/exe_stage/ds_to_es_bus[119] SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/C clock pessimism -0.498 27.875 clock uncertainty -0.074 27.801 SLICE_X45Y24 FDRE (Setup_fdre_C_D) 0.029 27.830 u_cpu/exe_stage/ds_to_es_bus_r_reg[169] ------------------------------------------------------------------- required time 27.830 arrival time -24.358 ------------------------------------------------------------------- slack 3.472 Slack (MET) : 3.473ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.860ns (logic 6.845ns (25.484%) route 20.015ns (74.516%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.494 21.302 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X38Y28 LUT6 (Prop_lut6_I5_O) 0.124 21.426 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_12/O net (fo=11, routed) 1.155 22.581 u_cpu/id_stage/ds_to_es_bus_r[178]_i_12_n_0 SLICE_X42Y20 LUT5 (Prop_lut5_I4_O) 0.124 22.705 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O net (fo=1, routed) 0.760 23.465 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 SLICE_X42Y24 LUT5 (Prop_lut5_I0_O) 0.124 23.589 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O net (fo=1, routed) 0.646 24.235 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 SLICE_X45Y24 LUT6 (Prop_lut6_I3_O) 0.124 24.359 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 24.359 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/C clock pessimism -0.498 27.875 clock uncertainty -0.074 27.801 SLICE_X45Y24 FDRE (Setup_fdre_C_D) 0.031 27.832 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 27.832 arrival time -24.359 ------------------------------------------------------------------- slack 3.473 Slack (MET) : 3.482ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[13][26]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.650ns (logic 5.748ns (21.569%) route 20.902ns (78.431%)) Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: 0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.915ns = ( 28.408 - 30.323 ) Source Clock Delay (SCD): -2.502ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O net (fo=30, routed) 0.872 24.148 u_cpu/btb/btb_pc[13][29]_i_1_n_0 SLICE_X114Y41 FDRE r u_cpu/btb/btb_pc_reg[13][26]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.914 28.408 u_cpu/btb/cpu_clk SLICE_X114Y41 FDRE r u_cpu/btb/btb_pc_reg[13][26]/C clock pessimism -0.498 27.910 clock uncertainty -0.074 27.836 SLICE_X114Y41 FDRE (Setup_fdre_C_CE) -0.205 27.631 u_cpu/btb/btb_pc_reg[13][26] ------------------------------------------------------------------- required time 27.631 arrival time -24.148 ------------------------------------------------------------------- slack 3.482 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: cpu_clk Waveform(ns): { 0.000 15.161 } Period(ns): 30.323 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.323 29.074 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[0]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[1]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y5 u_cpu/btb/btb_untaken_entry_r_reg[0]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y6 u_cpu/btb/btb_untaken_entry_r_reg[10]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y8 u_cpu/btb/btb_untaken_entry_r_reg[11]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y4 u_cpu/btb/btb_untaken_entry_r_reg[12]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X50Y5 u_cpu/btb/btb_untaken_entry_r_reg[13]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X49Y9 u_cpu/btb/btb_untaken_entry_r_reg[14]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- From Clock: mlkem_clk_clk_pll To Clock: mlkem_clk_clk_pll Setup : 0 Failing Endpoints, Worst Slack 10.807ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 10.807ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/C clock pessimism -0.507 37.214 clock uncertainty -0.077 37.138 SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] ------------------------------------------------------------------- required time 37.167 arrival time -26.360 ------------------------------------------------------------------- slack 10.807 Slack (MET) : 10.904ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/C clock pessimism -0.507 37.214 clock uncertainty -0.077 37.138 SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] ------------------------------------------------------------------- required time 37.219 arrival time -26.315 ------------------------------------------------------------------- slack 10.904 Slack (MET) : 10.918ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/C clock pessimism -0.507 37.214 clock uncertainty -0.077 37.138 SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] ------------------------------------------------------------------- required time 37.215 arrival time -26.297 ------------------------------------------------------------------- slack 10.918 Slack (MET) : 11.034ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/C clock pessimism -0.507 37.214 clock uncertainty -0.077 37.138 SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] ------------------------------------------------------------------- required time 37.169 arrival time -26.135 ------------------------------------------------------------------- slack 11.034 Slack (MET) : 11.059ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/C clock pessimism -0.507 37.214 clock uncertainty -0.077 37.138 SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] ------------------------------------------------------------------- required time 37.215 arrival time -26.156 ------------------------------------------------------------------- slack 11.059 Slack (MET) : 11.066ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/C clock pessimism -0.507 37.214 clock uncertainty -0.077 37.138 SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] ------------------------------------------------------------------- required time 37.219 arrival time -26.153 ------------------------------------------------------------------- slack 11.066 Slack (MET) : 11.162ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.098ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/C clock pessimism -0.507 37.212 clock uncertainty -0.077 37.136 SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] ------------------------------------------------------------------- required time 37.165 arrival time -26.003 ------------------------------------------------------------------- slack 11.162 Slack (MET) : 11.217ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.097ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/C clock pessimism -0.507 37.213 clock uncertainty -0.077 37.137 SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] ------------------------------------------------------------------- required time 37.166 arrival time -25.949 ------------------------------------------------------------------- slack 11.217 Slack (MET) : 11.246ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.097ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/C clock pessimism -0.507 37.213 clock uncertainty -0.077 37.137 SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] ------------------------------------------------------------------- required time 37.214 arrival time -25.968 ------------------------------------------------------------------- slack 11.246 Slack (MET) : 11.322ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.099ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/C clock pessimism -0.507 37.211 clock uncertainty -0.077 37.135 SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] ------------------------------------------------------------------- required time 37.166 arrival time -25.844 ------------------------------------------------------------------- slack 11.322 Slack (MET) : 11.414ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.098ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/C clock pessimism -0.507 37.212 clock uncertainty -0.077 37.136 SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] ------------------------------------------------------------------- required time 37.213 arrival time -25.799 ------------------------------------------------------------------- slack 11.414 Slack (MET) : 11.421ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.098ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/C clock pessimism -0.507 37.212 clock uncertainty -0.077 37.136 SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] ------------------------------------------------------------------- required time 37.217 arrival time -25.796 ------------------------------------------------------------------- slack 11.421 Slack (MET) : 11.503ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.097ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/C clock pessimism -0.507 37.213 clock uncertainty -0.077 37.137 SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] ------------------------------------------------------------------- required time 37.168 arrival time -25.665 ------------------------------------------------------------------- slack 11.503 Slack (MET) : 11.505ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.544 37.716 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/C clock pessimism -0.507 37.209 clock uncertainty -0.077 37.133 SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] ------------------------------------------------------------------- required time 37.162 arrival time -25.657 ------------------------------------------------------------------- slack 11.505 Slack (MET) : 11.519ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.099ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/C clock pessimism -0.507 37.211 clock uncertainty -0.077 37.135 SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] ------------------------------------------------------------------- required time 37.216 arrival time -25.697 ------------------------------------------------------------------- slack 11.519 Slack (MET) : 11.557ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.299ns (logic 0.704ns (2.488%) route 27.595ns (97.512%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.099ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.357 25.485 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.609 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[952]_i_1/O net (fo=1, routed) 0.000 25.609 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_474 SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952]/C clock pessimism -0.507 37.211 clock uncertainty -0.077 37.135 SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952] ------------------------------------------------------------------- required time 37.166 arrival time -25.609 ------------------------------------------------------------------- slack 11.557 Slack (MET) : 11.686ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.168ns (logic 0.704ns (2.499%) route 27.464ns (97.501%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.100ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns = ( 37.717 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.227 25.355 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X43Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.479 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[955]_i_1/O net (fo=1, routed) 0.000 25.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_477 SLICE_X43Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.545 37.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X43Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955]/C clock pessimism -0.507 37.210 clock uncertainty -0.077 37.134 SLICE_X43Y132 FDCE (Setup_fdce_C_D) 0.031 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955] ------------------------------------------------------------------- required time 37.165 arrival time -25.479 ------------------------------------------------------------------- slack 11.686 Slack (MET) : 11.688ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.252ns (logic 0.704ns (2.492%) route 27.548ns (97.508%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.196ns = ( 37.804 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.311 25.438 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X41Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1020]_i_1/O net (fo=1, routed) 0.000 25.562 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1186 SLICE_X41Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.632 37.804 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X41Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020]/C clock pessimism -0.507 37.297 clock uncertainty -0.077 37.221 SLICE_X41Y133 FDCE (Setup_fdce_C_D) 0.029 37.250 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020] ------------------------------------------------------------------- required time 37.250 arrival time -25.562 ------------------------------------------------------------------- slack 11.688 Slack (MET) : 11.690ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.161ns (logic 0.704ns (2.500%) route 27.457ns (97.500%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.220 25.347 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X47Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1016]_i_1/O net (fo=1, routed) 0.000 25.471 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1182 SLICE_X47Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.544 37.716 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X47Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016]/C clock pessimism -0.507 37.209 clock uncertainty -0.077 37.133 SLICE_X47Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016] ------------------------------------------------------------------- required time 37.162 arrival time -25.471 ------------------------------------------------------------------- slack 11.690 Slack (MET) : 11.731ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.172ns (logic 0.704ns (2.499%) route 27.468ns (97.501%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.098ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.230 25.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X42Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.482 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1005]_i_1/O net (fo=1, routed) 0.000 25.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1171 SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005]/C clock pessimism -0.507 37.212 clock uncertainty -0.077 37.136 SLICE_X42Y134 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005] ------------------------------------------------------------------- required time 37.213 arrival time -25.482 ------------------------------------------------------------------- slack 11.731 Slack (MET) : 11.735ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.114ns (logic 0.704ns (2.504%) route 27.410ns (97.496%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.103ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.173 25.301 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X50Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.425 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[653]_i_1/O net (fo=1, routed) 0.000 25.425 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_906 SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653]/C clock pessimism -0.507 37.207 clock uncertainty -0.077 37.131 SLICE_X50Y129 FDCE (Setup_fdce_C_D) 0.029 37.160 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653] ------------------------------------------------------------------- required time 37.160 arrival time -25.425 ------------------------------------------------------------------- slack 11.735 Slack (MET) : 11.764ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.140ns (logic 0.704ns (2.502%) route 27.436ns (97.498%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.198 25.326 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X44Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.450 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[880]_i_1/O net (fo=1, routed) 0.000 25.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1117 SLICE_X44Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.544 37.716 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X44Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880]/C clock pessimism -0.507 37.209 clock uncertainty -0.077 37.133 SLICE_X44Y131 FDCE (Setup_fdce_C_D) 0.081 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880] ------------------------------------------------------------------- required time 37.214 arrival time -25.450 ------------------------------------------------------------------- slack 11.764 Slack (MET) : 11.777ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.166ns (logic 0.704ns (2.499%) route 27.462ns (97.501%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.012ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.225 25.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X41Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[968]_i_1/O net (fo=1, routed) 0.000 25.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1142 SLICE_X41Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.633 37.805 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X41Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968]/C clock pessimism -0.507 37.298 clock uncertainty -0.077 37.222 SLICE_X41Y134 FDCE (Setup_fdce_C_D) 0.031 37.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968] ------------------------------------------------------------------- required time 37.253 arrival time -25.476 ------------------------------------------------------------------- slack 11.777 Slack (MET) : 11.846ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.007ns (logic 0.704ns (2.514%) route 27.303ns (97.486%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.099ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.066 25.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X43Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.318 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[825]_i_1/O net (fo=1, routed) 0.000 25.318 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_468 SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825]/C clock pessimism -0.507 37.211 clock uncertainty -0.077 37.135 SLICE_X43Y133 FDCE (Setup_fdce_C_D) 0.029 37.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825] ------------------------------------------------------------------- required time 37.164 arrival time -25.318 ------------------------------------------------------------------- slack 11.846 Slack (MET) : 11.849ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 28.006ns (logic 0.704ns (2.514%) route 27.302ns (97.486%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.099ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.065 25.193 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X43Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.317 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[921]_i_1/O net (fo=1, routed) 0.000 25.317 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1006 SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921]/C clock pessimism -0.507 37.211 clock uncertainty -0.077 37.135 SLICE_X43Y133 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921] ------------------------------------------------------------------- required time 37.166 arrival time -25.317 ------------------------------------------------------------------- slack 11.849 Slack (MET) : 11.911ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.944ns (logic 0.704ns (2.519%) route 27.240ns (97.481%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.098ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.002 25.130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X43Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.254 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[794]_i_1/O net (fo=1, routed) 0.000 25.254 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1000 SLICE_X43Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X43Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794]/C clock pessimism -0.507 37.212 clock uncertainty -0.077 37.136 SLICE_X43Y134 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794] ------------------------------------------------------------------- required time 37.165 arrival time -25.254 ------------------------------------------------------------------- slack 11.911 Slack (MET) : 11.944ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.955ns (logic 0.704ns (2.518%) route 27.251ns (97.482%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.102ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.285ns = ( 37.715 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.013 25.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X46Y130 LUT6 (Prop_lut6_I1_O) 0.124 25.265 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[941]_i_1/O net (fo=1, routed) 0.000 25.265 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_335 SLICE_X46Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.543 37.715 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X46Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941]/C clock pessimism -0.507 37.208 clock uncertainty -0.077 37.132 SLICE_X46Y130 FDCE (Setup_fdce_C_D) 0.077 37.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941] ------------------------------------------------------------------- required time 37.209 arrival time -25.265 ------------------------------------------------------------------- slack 11.944 Slack (MET) : 11.945ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) Source Clock Delay (SCD): -2.586ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114]/C clock pessimism -0.507 37.309 clock uncertainty -0.077 37.233 SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114] ------------------------------------------------------------------- required time 36.862 arrival time -24.917 ------------------------------------------------------------------- slack 11.945 Slack (MET) : 11.945ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) Source Clock Delay (SCD): -2.586ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115]/C clock pessimism -0.507 37.309 clock uncertainty -0.077 37.233 SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115] ------------------------------------------------------------------- required time 36.862 arrival time -24.917 ------------------------------------------------------------------- slack 11.945 Slack (MET) : 11.945ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) Source Clock Delay (SCD): -2.586ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331]/C clock pessimism -0.507 37.309 clock uncertainty -0.077 37.233 SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331] ------------------------------------------------------------------- required time 36.862 arrival time -24.917 ------------------------------------------------------------------- slack 11.945 Slack (MET) : 11.945ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) Source Clock Delay (SCD): -2.586ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401]/C clock pessimism -0.507 37.309 clock uncertainty -0.077 37.233 SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401] ------------------------------------------------------------------- required time 36.862 arrival time -24.917 ------------------------------------------------------------------- slack 11.945 Slack (MET) : 11.945ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) Source Clock Delay (SCD): -2.586ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435]/C clock pessimism -0.507 37.309 clock uncertainty -0.077 37.233 SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435] ------------------------------------------------------------------- required time 36.862 arrival time -24.917 ------------------------------------------------------------------- slack 11.945 Slack (MET) : 11.945ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) Source Clock Delay (SCD): -2.586ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829]/C clock pessimism -0.507 37.309 clock uncertainty -0.077 37.233 SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829] ------------------------------------------------------------------- required time 36.862 arrival time -24.917 ------------------------------------------------------------------- slack 11.945 Slack (MET) : 11.945ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) Source Clock Delay (SCD): -2.586ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860]/C clock pessimism -0.507 37.309 clock uncertainty -0.077 37.233 SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860] ------------------------------------------------------------------- required time 36.862 arrival time -24.917 ------------------------------------------------------------------- slack 11.945 Slack (MET) : 11.945ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) Source Clock Delay (SCD): -2.586ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924]/C clock pessimism -0.507 37.309 clock uncertainty -0.077 37.233 SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924] ------------------------------------------------------------------- required time 36.862 arrival time -24.917 ------------------------------------------------------------------- slack 11.945 Slack (MET) : 11.947ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.960ns (logic 0.704ns (2.518%) route 27.256ns (97.482%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.098ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 21.018 25.146 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X42Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1006]_i_1/O net (fo=1, routed) 0.000 25.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1172 SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006]/C clock pessimism -0.507 37.212 clock uncertainty -0.077 37.136 SLICE_X42Y134 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006] ------------------------------------------------------------------- required time 37.217 arrival time -25.270 ------------------------------------------------------------------- slack 11.947 Slack (MET) : 11.958ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.891ns (logic 0.704ns (2.524%) route 27.187ns (97.476%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.103ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 20.950 25.078 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X51Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[698]_i_1/O net (fo=1, routed) 0.000 25.202 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_462 SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698]/C clock pessimism -0.507 37.207 clock uncertainty -0.077 37.131 SLICE_X51Y129 FDCE (Setup_fdce_C_D) 0.029 37.160 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698] ------------------------------------------------------------------- required time 37.160 arrival time -25.202 ------------------------------------------------------------------- slack 11.958 Slack (MET) : 11.960ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.891ns (logic 0.704ns (2.524%) route 27.187ns (97.476%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.103ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 20.950 25.078 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X50Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[996]_i_1/O net (fo=1, routed) 0.000 25.202 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_785 SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996]/C clock pessimism -0.507 37.207 clock uncertainty -0.077 37.131 SLICE_X50Y129 FDCE (Setup_fdce_C_D) 0.031 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996] ------------------------------------------------------------------- required time 37.162 arrival time -25.202 ------------------------------------------------------------------- slack 11.960 Slack (MET) : 11.962ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.889ns (logic 0.704ns (2.524%) route 27.185ns (97.476%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.103ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 20.948 25.076 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X51Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[997]_i_1/O net (fo=1, routed) 0.000 25.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_786 SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997]/C clock pessimism -0.507 37.207 clock uncertainty -0.077 37.131 SLICE_X51Y129 FDCE (Setup_fdce_C_D) 0.031 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997] ------------------------------------------------------------------- required time 37.162 arrival time -25.200 ------------------------------------------------------------------- slack 11.962 Slack (MET) : 11.975ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.867ns (logic 0.704ns (2.526%) route 27.163ns (97.474%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns = ( 37.707 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 20.926 25.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X55Y125 LUT6 (Prop_lut6_I1_O) 0.124 25.178 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[713]_i_1/O net (fo=1, routed) 0.000 25.178 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1029 SLICE_X55Y125 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.535 37.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X55Y125 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713]/C clock pessimism -0.507 37.200 clock uncertainty -0.077 37.124 SLICE_X55Y125 FDCE (Setup_fdce_C_D) 0.029 37.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713] ------------------------------------------------------------------- required time 37.153 arrival time -25.178 ------------------------------------------------------------------- slack 11.975 Slack (MET) : 12.001ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.895ns (logic 0.704ns (2.524%) route 27.191ns (97.476%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.104ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.287ns = ( 37.713 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 20.954 25.082 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X52Y128 LUT6 (Prop_lut6_I1_O) 0.124 25.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[714]_i_1/O net (fo=1, routed) 0.000 25.206 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1030 SLICE_X52Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.541 37.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X52Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714]/C clock pessimism -0.507 37.206 clock uncertainty -0.077 37.130 SLICE_X52Y128 FDCE (Setup_fdce_C_D) 0.077 37.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714] ------------------------------------------------------------------- required time 37.207 arrival time -25.206 ------------------------------------------------------------------- slack 12.001 Slack (MET) : 12.017ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.835ns (logic 0.704ns (2.529%) route 27.131ns (97.471%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.103ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 20.894 25.021 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X53Y130 LUT6 (Prop_lut6_I1_O) 0.124 25.145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[701]_i_1/O net (fo=1, routed) 0.000 25.145 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_465 SLICE_X53Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X53Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701]/C clock pessimism -0.507 37.207 clock uncertainty -0.077 37.131 SLICE_X53Y130 FDCE (Setup_fdce_C_D) 0.031 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701] ------------------------------------------------------------------- required time 37.162 arrival time -25.145 ------------------------------------------------------------------- slack 12.017 Slack (MET) : 12.030ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.826ns (logic 0.704ns (2.530%) route 27.122ns (97.470%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.097ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 20.884 25.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X43Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1002]_i_1/O net (fo=1, routed) 0.000 25.136 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1168 SLICE_X43Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X43Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002]/C clock pessimism -0.507 37.213 clock uncertainty -0.077 37.137 SLICE_X43Y135 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002] ------------------------------------------------------------------- required time 37.166 arrival time -25.136 ------------------------------------------------------------------- slack 12.030 Slack (MET) : 12.046ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.810ns (logic 0.704ns (2.531%) route 27.106ns (97.469%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 20.869 24.997 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X45Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.121 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[781]_i_1/O net (fo=1, routed) 0.000 25.121 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_913 SLICE_X45Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781]/C clock pessimism -0.507 37.214 clock uncertainty -0.077 37.138 SLICE_X45Y136 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781] ------------------------------------------------------------------- required time 37.167 arrival time -25.121 ------------------------------------------------------------------- slack 12.046 Slack (MET) : 12.066ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.826ns (logic 0.704ns (2.530%) route 27.122ns (97.470%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.291ns = ( 37.709 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 20.885 25.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X56Y126 LUT6 (Prop_lut6_I1_O) 0.124 25.137 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[712]_i_1/O net (fo=1, routed) 0.000 25.137 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1028 SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.537 37.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712]/C clock pessimism -0.507 37.202 clock uncertainty -0.077 37.126 SLICE_X56Y126 FDCE (Setup_fdce_C_D) 0.077 37.203 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712] ------------------------------------------------------------------- required time 37.203 arrival time -25.137 ------------------------------------------------------------------- slack 12.066 Slack (MET) : 12.080ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.816ns (logic 0.704ns (2.531%) route 27.112ns (97.469%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.291ns = ( 37.709 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 20.875 25.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X56Y126 LUT6 (Prop_lut6_I1_O) 0.124 25.127 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[716]_i_1/O net (fo=1, routed) 0.000 25.127 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1032 SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.537 37.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716]/C clock pessimism -0.507 37.202 clock uncertainty -0.077 37.126 SLICE_X56Y126 FDCE (Setup_fdce_C_D) 0.081 37.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716] ------------------------------------------------------------------- required time 37.207 arrival time -25.127 ------------------------------------------------------------------- slack 12.080 Slack (MET) : 12.098ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.803ns (logic 0.704ns (2.532%) route 27.099ns (97.468%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.099ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) Source Clock Delay (SCD): -2.690ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O net (fo=936, routed) 20.862 24.990 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 SLICE_X42Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.114 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[920]_i_1/O net (fo=1, routed) 0.000 25.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1005 SLICE_X42Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X42Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920]/C clock pessimism -0.507 37.211 clock uncertainty -0.077 37.135 SLICE_X42Y133 FDCE (Setup_fdce_C_D) 0.077 37.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920] ------------------------------------------------------------------- required time 37.212 arrival time -25.114 ------------------------------------------------------------------- slack 12.098 Slack (MET) : 12.111ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.340ns (logic 1.594ns (5.830%) route 25.746ns (94.170%)) Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.180ns = ( 37.820 - 40.000 ) Source Clock Delay (SCD): -2.586ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.963 24.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.648 37.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490]/C clock pessimism -0.507 37.313 clock uncertainty -0.077 37.237 SLICE_X22Y111 FDCE (Setup_fdce_C_CE) -0.371 36.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490] ------------------------------------------------------------------- required time 36.866 arrival time -24.755 ------------------------------------------------------------------- slack 12.111 Slack (MET) : 12.111ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.340ns (logic 1.594ns (5.830%) route 25.746ns (94.170%)) Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.180ns = ( 37.820 - 40.000 ) Source Clock Delay (SCD): -2.586ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.963 24.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.648 37.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491]/C clock pessimism -0.507 37.313 clock uncertainty -0.077 37.237 SLICE_X22Y111 FDCE (Setup_fdce_C_CE) -0.371 36.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491] ------------------------------------------------------------------- required time 36.866 arrival time -24.755 ------------------------------------------------------------------- slack 12.111 Slack (MET) : 12.111ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 27.340ns (logic 1.594ns (5.830%) route 25.746ns (94.170%)) Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.180ns = ( 37.820 - 40.000 ) Source Clock Delay (SCD): -2.586ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C ------------------------------------------------------------------- ------------------- SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.963 24.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.648 37.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778]/C clock pessimism -0.507 37.313 clock uncertainty -0.077 37.237 SLICE_X22Y111 FDCE (Setup_fdce_C_CE) -0.371 36.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778] ------------------------------------------------------------------- required time 36.866 arrival time -24.755 ------------------------------------------------------------------- slack 12.111 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: mlkem_clk_clk_pll Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 40.000 38.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X103Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[897]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X101Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[898]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y118 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[899]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[89]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[8]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[900]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[901]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[902]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[903]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X56Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[904]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[905]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[906]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[907]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[908]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[909]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[90]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[910]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[911]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[912]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[913]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X92Y115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[914]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X148Y176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][3]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][4]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][5]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X125Y187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][6]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X132Y173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][7]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][8]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X150Y179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][9]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X130Y211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][0]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][10]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][11]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X121Y226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][1]/C Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 40.000 120.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: sys_clk To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 0.167ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.167ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 13.188 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -13.188 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.284ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O net (fo=1, unset) 0.000 13.070 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -13.070 ------------------------------------------------------------------- slack 0.284 Slack (MET) : 0.377ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T AC16 OBUFT (TriStatE_obuft_T_O) 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O net (fo=1, unset) 0.000 12.977 ext_ram_data[21] AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.977 ------------------------------------------------------------------- slack 0.377 Slack (MET) : 0.414ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T AB16 OBUFT (TriStatE_obuft_T_O) 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.940 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.940 ------------------------------------------------------------------- slack 0.414 Slack (MET) : 0.424ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O net (fo=1, unset) 0.000 12.931 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.931 ------------------------------------------------------------------- slack 0.424 Slack (MET) : 0.431ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O net (fo=1, unset) 0.000 12.923 ext_ram_data[20] AD18 r ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.923 ------------------------------------------------------------------- slack 0.431 Slack (MET) : 0.455ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.899 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.899 ------------------------------------------------------------------- slack 0.455 Slack (MET) : 0.477ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[28] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O net (fo=1, unset) 0.000 12.877 base_ram_data[28] N22 r base_ram_data[28] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.877 ------------------------------------------------------------------- slack 0.477 Slack (MET) : 0.555ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T M20 OBUFT (TriStatE_obuft_T_O) 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O net (fo=1, unset) 0.000 12.799 base_ram_data[21] M20 r base_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.799 ------------------------------------------------------------------- slack 0.555 Slack (MET) : 0.555ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T M24 OBUFT (TriStatE_obuft_T_O) 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.799 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.799 ------------------------------------------------------------------- slack 0.555 Slack (MET) : 0.558ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.118ns (logic 6.871ns (45.448%) route 8.247ns (54.552%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.444 9.239 ext_ram_data_IOBUF[24]_inst/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 12.797 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.797 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.797 ------------------------------------------------------------------- slack 0.558 Slack (MET) : 0.584ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[17] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.092ns (logic 6.859ns (45.448%) route 8.233ns (54.552%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.694 9.224 base_ram_data_IOBUF[17]_inst/T M21 OBUFT (TriStatE_obuft_T_O) 3.546 12.770 r base_ram_data_IOBUF[17]_inst/OBUFT/O net (fo=1, unset) 0.000 12.770 base_ram_data[17] M21 r base_ram_data[17] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.770 ------------------------------------------------------------------- slack 0.584 Slack (MET) : 0.597ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[23] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.079ns (logic 6.848ns (45.415%) route 8.231ns (54.585%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.693 9.222 base_ram_data_IOBUF[23]_inst/T N21 OBUFT (TriStatE_obuft_T_O) 3.535 12.757 r base_ram_data_IOBUF[23]_inst/OBUFT/O net (fo=1, unset) 0.000 12.757 base_ram_data[23] N21 r base_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.757 ------------------------------------------------------------------- slack 0.597 Slack (MET) : 0.647ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[19] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.124ns (logic 5.128ns (33.905%) route 9.996ns (66.095%)) Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=196, routed) 1.513 2.665 u_matmul_axi_slave/b0_c_reg_r2_0_15_48_53/ADDRB0 SLICE_X36Y74 RAMD32 (Prop_ramd32_RADR0_O) 0.124 2.789 r u_matmul_axi_slave/b0_c_reg_r2_0_15_48_53/RAMB_D1/O net (fo=1, routed) 0.605 3.393 u_snix_axil_cdma_mux_8ch/ep_rd_c0[51] SLICE_X34Y74 LUT6 (Prop_lut6_I1_O) 0.124 3.517 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_14__0/O net (fo=2, routed) 0.775 4.293 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[19]_inst_i_1_0 SLICE_X30Y77 LUT5 (Prop_lut5_I3_O) 0.124 4.417 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_7__0/O net (fo=2, routed) 1.453 5.869 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[19] SLICE_X6Y79 LUT3 (Prop_lut3_I0_O) 0.124 5.993 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[19]_inst_i_1/O net (fo=2, routed) 3.172 9.165 ext_ram_data_IOBUF[19]_inst/I AC18 OBUFT (Prop_obuft_I_O) 3.542 12.707 r ext_ram_data_IOBUF[19]_inst/OBUFT/O net (fo=1, unset) 0.000 12.707 ext_ram_data[19] AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.707 ------------------------------------------------------------------- slack 0.647 Slack (MET) : 0.675ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[2] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.000ns (logic 6.848ns (45.654%) route 8.152ns (54.346%)) Logic Levels: 14 (CARRY4=7 LUT4=1 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.270 7.078 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X11Y127 LUT6 (Prop_lut6_I5_O) 0.124 7.202 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[2]_inst_i_1/O net (fo=1, routed) 1.941 9.143 base_ram_be_n_OBUF[2] L23 OBUF (Prop_obuf_I_O) 3.535 12.679 r base_ram_be_n_OBUF[2]_inst/O net (fo=0) 0.000 12.679 base_ram_be_n[2] L23 r base_ram_be_n[2] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.679 ------------------------------------------------------------------- slack 0.675 Slack (MET) : 0.680ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.996ns (logic 6.840ns (45.614%) route 8.156ns (54.386%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.617 9.147 base_ram_data_IOBUF[16]_inst/T P21 OBUFT (TriStatE_obuft_T_O) 3.527 12.674 r base_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.674 base_ram_data[16] P21 r base_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.674 ------------------------------------------------------------------- slack 0.680 Slack (MET) : 0.681ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.090ns (logic 5.359ns (35.512%) route 9.732ns (64.488%)) Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O net (fo=2, routed) 3.167 9.136 base_ram_data_IOBUF[22]_inst/I N24 OBUFT (Prop_obuft_I_O) 3.537 12.673 r base_ram_data_IOBUF[22]_inst/OBUFT/O net (fo=1, unset) 0.000 12.673 base_ram_data[22] N24 r base_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.673 ------------------------------------------------------------------- slack 0.681 Slack (MET) : 0.682ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.993ns (logic 6.873ns (45.840%) route 8.120ns (54.160%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.582 9.112 base_ram_data_IOBUF[0]_inst/T L24 OBUFT (TriStatE_obuft_T_O) 3.560 12.672 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.672 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.672 ------------------------------------------------------------------- slack 0.682 Slack (MET) : 0.692ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[23] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.984ns (logic 6.855ns (45.753%) route 8.128ns (54.247%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.325 9.120 ext_ram_data_IOBUF[23]_inst/T AA15 OBUFT (TriStatE_obuft_T_O) 3.542 12.662 r ext_ram_data_IOBUF[23]_inst/OBUFT/O net (fo=1, unset) 0.000 12.662 ext_ram_data[23] AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.662 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.697ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[29] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.075ns (logic 5.121ns (33.974%) route 9.953ns (66.026%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.174 2.506 u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/ADDRA1 SLICE_X36Y75 RAMD32 (Prop_ramd32_RADR1_O) 0.124 2.630 r u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/RAMA_D1/O net (fo=1, routed) 0.969 3.598 u_snix_axil_cdma_mux_8ch/ep_rd_c0[61] SLICE_X35Y72 LUT6 (Prop_lut6_I1_O) 0.124 3.722 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_26__0/O net (fo=1, routed) 0.767 4.489 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][29]_i_2 SLICE_X34Y70 LUT4 (Prop_lut4_I2_O) 0.124 4.613 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_11__0/O net (fo=7, routed) 1.469 6.082 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_3 SLICE_X6Y65 LUT3 (Prop_lut3_I0_O) 0.124 6.206 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[29]_inst_i_1/O net (fo=2, routed) 2.916 9.122 base_ram_data_IOBUF[29]_inst/I N23 OBUFT (Prop_obuft_I_O) 3.535 12.657 r base_ram_data_IOBUF[29]_inst/OBUFT/O net (fo=1, unset) 0.000 12.657 base_ram_data[29] N23 r base_ram_data[29] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.657 ------------------------------------------------------------------- slack 0.697 Slack (MET) : 0.700ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.976ns (logic 6.883ns (45.959%) route 8.093ns (54.041%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.555 9.084 base_ram_data_IOBUF[3]_inst/T M25 OBUFT (TriStatE_obuft_T_O) 3.570 12.654 r base_ram_data_IOBUF[3]_inst/OBUFT/O net (fo=1, unset) 0.000 12.654 base_ram_data[3] M25 r base_ram_data[3] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.654 ------------------------------------------------------------------- slack 0.700 Slack (MET) : 0.717ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.959ns (logic 6.859ns (45.853%) route 8.100ns (54.147%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.562 9.091 base_ram_data_IOBUF[31]_inst/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.638 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.638 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.638 ------------------------------------------------------------------- slack 0.717 Slack (MET) : 0.724ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.048ns (logic 5.340ns (35.487%) route 9.708ns (64.513%)) Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O net (fo=2, routed) 2.954 9.128 base_ram_data_IOBUF[20]_inst/I N19 OBUFT (Prop_obuft_I_O) 3.502 12.630 r base_ram_data_IOBUF[20]_inst/OBUFT/O net (fo=1, unset) 0.000 12.630 base_ram_data[20] N19 r base_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.630 ------------------------------------------------------------------- slack 0.724 Slack (MET) : 0.737ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.035ns (logic 5.349ns (35.580%) route 9.685ns (64.420%)) Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O net (fo=2, routed) 3.564 9.084 base_ram_data_IOBUF[18]_inst/I P23 OBUFT (Prop_obuft_I_O) 3.533 12.617 r base_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.617 base_ram_data[18] P23 r base_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.617 ------------------------------------------------------------------- slack 0.737 Slack (MET) : 0.793ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[28] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.978ns (logic 5.374ns (35.881%) route 9.604ns (64.119%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O net (fo=2, routed) 2.870 9.008 ext_ram_data_IOBUF[28]_inst/I AD21 OBUFT (Prop_obuft_I_O) 3.552 12.561 r ext_ram_data_IOBUF[28]_inst/OBUFT/O net (fo=1, unset) 0.000 12.561 ext_ram_data[28] AD21 r ext_ram_data[28] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.561 ------------------------------------------------------------------- slack 0.793 Slack (MET) : 0.827ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[26] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.945ns (logic 5.374ns (35.959%) route 9.571ns (64.041%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 0.957 2.289 u_matmul_axi_slave/b1_c_reg_r2_0_15_54_59/ADDRC1 SLICE_X36Y70 RAMD32 (Prop_ramd32_RADR1_O) 0.153 2.442 r u_matmul_axi_slave/b1_c_reg_r2_0_15_54_59/RAMC/O net (fo=1, routed) 0.739 3.181 u_snix_axil_cdma_mux_8ch/ep_rd_c1[58] SLICE_X39Y71 LUT6 (Prop_lut6_I0_O) 0.331 3.512 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_23__0/O net (fo=1, routed) 0.706 4.218 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][26]_i_2_0 SLICE_X35Y73 LUT4 (Prop_lut4_I2_O) 0.124 4.342 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_10__0/O net (fo=6, routed) 1.406 5.748 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[26] SLICE_X2Y73 LUT3 (Prop_lut3_I0_O) 0.124 5.872 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[26]_inst_i_1/O net (fo=2, routed) 3.104 8.975 ext_ram_data_IOBUF[26]_inst/I AD20 OBUFT (Prop_obuft_I_O) 3.552 12.527 r ext_ram_data_IOBUF[26]_inst/OBUFT/O net (fo=1, unset) 0.000 12.527 ext_ram_data[26] AD20 r ext_ram_data[26] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.527 ------------------------------------------------------------------- slack 0.827 Slack (MET) : 0.830ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[19] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.845ns (logic 6.831ns (46.012%) route 8.015ns (53.988%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.476 9.006 base_ram_data_IOBUF[19]_inst/T P19 OBUFT (TriStatE_obuft_T_O) 3.518 12.524 r base_ram_data_IOBUF[19]_inst/OBUFT/O net (fo=1, unset) 0.000 12.524 base_ram_data[19] P19 r base_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.524 ------------------------------------------------------------------- slack 0.830 Slack (MET) : 0.836ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[2]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.109ns (logic 5.382ns (28.164%) route 13.727ns (71.836%)) Logic Levels: 18 (CARRY4=3 LUT2=3 LUT3=1 LUT4=4 LUT5=2 LUT6=5) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) Source Clock Delay (SCD): -2.536ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O net (fo=15, routed) 1.005 16.243 u_matmul_axi_slave/crc32_word_next1_return1[1] SLICE_X71Y60 LUT3 (Prop_lut3_I1_O) 0.331 16.574 r u_matmul_axi_slave/crc_reg[2]_i_1/O net (fo=1, routed) 0.000 16.574 u_matmul_axi_slave/crc32_word_next1_return[2] SLICE_X71Y60 FDSE r u_matmul_axi_slave/crc_reg_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk SLICE_X71Y60 FDSE r u_matmul_axi_slave/crc_reg_reg[2]/C clock pessimism -0.426 17.449 clock uncertainty -0.071 17.379 SLICE_X71Y60 FDSE (Setup_fdse_C_D) 0.031 17.410 u_matmul_axi_slave/crc_reg_reg[2] ------------------------------------------------------------------- required time 17.410 arrival time -16.574 ------------------------------------------------------------------- slack 0.836 Slack (MET) : 0.845ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.830ns (logic 6.844ns (46.150%) route 7.986ns (53.850%)) Logic Levels: 14 (CARRY4=7 LUT4=1 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 1.799 6.608 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y112 LUT6 (Prop_lut6_I5_O) 0.124 6.732 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 2.246 8.977 base_ram_be_n_OBUF[0] L20 OBUF (Prop_obuf_I_O) 3.531 12.509 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.509 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.509 ------------------------------------------------------------------- slack 0.845 Slack (MET) : 0.860ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[17] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.912ns (logic 5.126ns (34.375%) route 9.786ns (65.625%)) Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.285 2.617 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 SLICE_X40Y73 RAMD32 (Prop_ramd32_RADR1_O) 0.124 2.741 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA_D1/O net (fo=1, routed) 0.600 3.341 u_snix_axil_cdma_mux_8ch/ep_rd_c1[49] SLICE_X35Y74 LUT6 (Prop_lut6_I0_O) 0.124 3.465 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_12_17_i_6__0/O net (fo=2, routed) 0.596 4.061 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[17]_inst_i_1_0 SLICE_X34Y73 LUT5 (Prop_lut5_I3_O) 0.124 4.185 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_12_17_i_3__0/O net (fo=2, routed) 1.313 5.498 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[17] SLICE_X8Y69 LUT3 (Prop_lut3_I0_O) 0.124 5.622 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[17]_inst_i_1/O net (fo=2, routed) 3.333 8.954 ext_ram_data_IOBUF[17]_inst/I AC19 OBUFT (Prop_obuft_I_O) 3.540 12.494 r ext_ram_data_IOBUF[17]_inst/OBUFT/O net (fo=1, unset) 0.000 12.494 ext_ram_data[17] AC19 r ext_ram_data[17] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.494 ------------------------------------------------------------------- slack 0.860 Slack (MET) : 0.862ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[29] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.910ns (logic 5.133ns (34.429%) route 9.777ns (65.571%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.174 2.506 u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/ADDRA1 SLICE_X36Y75 RAMD32 (Prop_ramd32_RADR1_O) 0.124 2.630 r u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/RAMA_D1/O net (fo=1, routed) 0.969 3.598 u_snix_axil_cdma_mux_8ch/ep_rd_c0[61] SLICE_X35Y72 LUT6 (Prop_lut6_I1_O) 0.124 3.722 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_26__0/O net (fo=1, routed) 0.767 4.489 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][29]_i_2 SLICE_X34Y70 LUT4 (Prop_lut4_I2_O) 0.124 4.613 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_11__0/O net (fo=7, routed) 1.469 6.082 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_3 SLICE_X6Y65 LUT3 (Prop_lut3_I0_O) 0.124 6.206 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[29]_inst_i_1/O net (fo=2, routed) 2.740 8.945 ext_ram_data_IOBUF[29]_inst/I AC21 OBUFT (Prop_obuft_I_O) 3.547 12.492 r ext_ram_data_IOBUF[29]_inst/OBUFT/O net (fo=1, unset) 0.000 12.492 ext_ram_data[29] AC21 r ext_ram_data[29] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.492 ------------------------------------------------------------------- slack 0.862 Slack (MET) : 0.870ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[19]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.071ns (logic 5.382ns (28.221%) route 13.689ns (71.779%)) Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=2 LUT6=6) Clock Path Skew: -0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) Source Clock Delay (SCD): -2.536ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O net (fo=15, routed) 0.967 16.204 u_matmul_axi_slave/crc32_word_next1_return1[1] SLICE_X71Y64 LUT6 (Prop_lut6_I3_O) 0.331 16.535 r u_matmul_axi_slave/crc_reg[19]_i_1/O net (fo=1, routed) 0.000 16.535 u_matmul_axi_slave/crc32_word_next1_return[19] SLICE_X71Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.701 17.873 u_matmul_axi_slave/sys_clk SLICE_X71Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[19]/C clock pessimism -0.426 17.446 clock uncertainty -0.071 17.376 SLICE_X71Y64 FDSE (Setup_fdse_C_D) 0.029 17.405 u_matmul_axi_slave/crc_reg_reg[19] ------------------------------------------------------------------- required time 17.405 arrival time -16.535 ------------------------------------------------------------------- slack 0.870 Slack (MET) : 0.875ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[27] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.896ns (logic 5.131ns (34.446%) route 9.765ns (65.554%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.268 2.600 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/ADDRB1 SLICE_X36Y69 RAMD32 (Prop_ramd32_RADR1_O) 0.124 2.724 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB_D1/O net (fo=1, routed) 0.724 3.448 u_snix_axil_cdma_mux_8ch/ep_rd_c0[27] SLICE_X34Y71 LUT6 (Prop_lut6_I1_O) 0.124 3.572 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_21__0/O net (fo=1, routed) 0.977 4.549 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][27]_i_2_1 SLICE_X23Y72 LUT4 (Prop_lut4_I3_O) 0.124 4.673 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_9__0/O net (fo=6, routed) 1.188 5.861 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[27] SLICE_X0Y75 LUT3 (Prop_lut3_I0_O) 0.124 5.985 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[27]_inst_i_1/O net (fo=2, routed) 2.949 8.934 ext_ram_data_IOBUF[27]_inst/I AB21 OBUFT (Prop_obuft_I_O) 3.545 12.479 r ext_ram_data_IOBUF[27]_inst/OBUFT/O net (fo=1, unset) 0.000 12.479 ext_ram_data[27] AB21 r ext_ram_data[27] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.479 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.883ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.888ns (logic 5.398ns (36.257%) route 9.490ns (63.743%)) Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) 0.146 2.991 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.751 3.742 u_snix_axil_cdma_mux_8ch/ep_rd_c0[0] SLICE_X34Y76 LUT6 (Prop_lut6_I1_O) 0.328 4.070 r u_snix_axil_cdma_mux_8ch/ram_reg_i_80/O net (fo=1, routed) 0.416 4.485 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0 SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.609 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_48/O net (fo=9, routed) 1.361 5.971 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_0 SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.095 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 2.790 8.885 ext_ram_data_IOBUF[0]_inst/I AF24 OBUFT (Prop_obuft_I_O) 3.586 12.471 r ext_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.471 ext_ram_data[0] AF24 r ext_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.471 ------------------------------------------------------------------- slack 0.883 Slack (MET) : 0.890ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_addr[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.786ns (logic 6.749ns (45.642%) route 8.037ns (54.358%)) Logic Levels: 13 (CARRY4=7 LUT4=1 LUT5=1 LUT6=3 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.925 4.220 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X0Y70 LUT6 (Prop_lut6_I5_O) 0.313 4.533 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[16]_inst_i_2/O net (fo=2, routed) 0.648 5.181 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[16]_inst_i_2_n_0 SLICE_X0Y71 LUT6 (Prop_lut6_I1_O) 0.124 5.305 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[16]_inst_i_1/O net (fo=2, routed) 3.599 8.905 ext_ram_addr_OBUF[16] AE17 OBUF (Prop_obuf_I_O) 3.560 12.464 r ext_ram_addr_OBUF[16]_inst/O net (fo=0) 0.000 12.464 ext_ram_addr[16] AE17 r ext_ram_addr[16] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.464 ------------------------------------------------------------------- slack 0.890 Slack (MET) : 0.905ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[18]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.087ns (logic 5.382ns (28.198%) route 13.705ns (71.802%)) Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=2 LUT6=6) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) Source Clock Delay (SCD): -2.536ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O net (fo=15, routed) 0.983 16.220 u_matmul_axi_slave/crc32_word_next1_return1[1] SLICE_X68Y64 LUT6 (Prop_lut6_I2_O) 0.331 16.551 r u_matmul_axi_slave/crc_reg[18]_i_1/O net (fo=1, routed) 0.000 16.551 u_matmul_axi_slave/crc32_word_next1_return[18] SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[18]/C clock pessimism -0.426 17.449 clock uncertainty -0.071 17.379 SLICE_X68Y64 FDSE (Setup_fdse_C_D) 0.077 17.456 u_matmul_axi_slave/crc_reg_reg[18] ------------------------------------------------------------------- required time 17.456 arrival time -16.551 ------------------------------------------------------------------- slack 0.905 Slack (MET) : 0.911ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[25]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.085ns (logic 5.382ns (28.201%) route 13.703ns (71.799%)) Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=2 LUT6=6) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) Source Clock Delay (SCD): -2.536ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O net (fo=15, routed) 0.981 16.218 u_matmul_axi_slave/crc32_word_next1_return1[1] SLICE_X68Y64 LUT6 (Prop_lut6_I2_O) 0.331 16.549 r u_matmul_axi_slave/crc_reg[25]_i_1/O net (fo=1, routed) 0.000 16.549 u_matmul_axi_slave/crc32_word_next1_return0[23] SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[25]/C clock pessimism -0.426 17.449 clock uncertainty -0.071 17.379 SLICE_X68Y64 FDSE (Setup_fdse_C_D) 0.081 17.460 u_matmul_axi_slave/crc_reg_reg[25] ------------------------------------------------------------------- required time 17.460 arrival time -16.549 ------------------------------------------------------------------- slack 0.911 Slack (MET) : 0.948ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.823ns (logic 5.154ns (34.770%) route 9.669ns (65.230%)) Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O net (fo=2, routed) 2.927 8.838 ext_ram_data_IOBUF[1]_inst/I AE23 OBUFT (Prop_obuft_I_O) 3.568 12.406 r ext_ram_data_IOBUF[1]_inst/OBUFT/O net (fo=1, unset) 0.000 12.406 ext_ram_data[1] AE23 r ext_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.406 ------------------------------------------------------------------- slack 0.948 Slack (MET) : 0.949ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[26] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.726ns (logic 6.846ns (46.488%) route 7.880ns (53.512%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.342 8.872 base_ram_data_IOBUF[26]_inst/T R21 OBUFT (TriStatE_obuft_T_O) 3.533 12.405 r base_ram_data_IOBUF[26]_inst/OBUFT/O net (fo=1, unset) 0.000 12.405 base_ram_data[26] R21 r base_ram_data[26] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.405 ------------------------------------------------------------------- slack 0.949 Slack (MET) : 0.959ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[13]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.035ns (logic 5.382ns (28.275%) route 13.653ns (71.725%)) Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=5 LUT5=2 LUT6=5) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) Source Clock Delay (SCD): -2.536ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O net (fo=15, routed) 0.931 16.168 u_matmul_axi_slave/crc32_word_next1_return1[1] SLICE_X68Y64 LUT4 (Prop_lut4_I1_O) 0.331 16.499 r u_matmul_axi_slave/crc_reg[13]_i_1/O net (fo=1, routed) 0.000 16.499 u_matmul_axi_slave/crc32_word_next1_return[13] SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[13]/C clock pessimism -0.426 17.449 clock uncertainty -0.071 17.379 SLICE_X68Y64 FDSE (Setup_fdse_C_D) 0.079 17.458 u_matmul_axi_slave/crc_reg_reg[13] ------------------------------------------------------------------- required time 17.458 arrival time -16.499 ------------------------------------------------------------------- slack 0.959 Slack (MET) : 0.962ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[29]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.029ns (logic 5.382ns (28.283%) route 13.647ns (71.717%)) Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=3 LUT6=5) Clock Path Skew: -0.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.126ns = ( 17.874 - 20.000 ) Source Clock Delay (SCD): -2.536ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O net (fo=15, routed) 0.925 16.162 u_matmul_axi_slave/crc32_word_next1_return1[1] SLICE_X70Y62 LUT5 (Prop_lut5_I4_O) 0.331 16.493 r u_matmul_axi_slave/crc_reg[29]_i_1/O net (fo=1, routed) 0.000 16.493 u_matmul_axi_slave/crc32_word_next1_return0[27] SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.702 17.874 u_matmul_axi_slave/sys_clk SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[29]/C clock pessimism -0.426 17.447 clock uncertainty -0.071 17.377 SLICE_X70Y62 FDSE (Setup_fdse_C_D) 0.079 17.456 u_matmul_axi_slave/crc_reg_reg[29] ------------------------------------------------------------------- required time 17.456 arrival time -16.493 ------------------------------------------------------------------- slack 0.962 Slack (MET) : 0.969ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[30]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.061ns (logic 5.414ns (28.404%) route 13.647ns (71.596%)) Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=5 LUT5=2 LUT6=5) Clock Path Skew: -0.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.126ns = ( 17.874 - 20.000 ) Source Clock Delay (SCD): -2.536ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O net (fo=15, routed) 0.925 16.162 u_matmul_axi_slave/crc32_word_next1_return1[1] SLICE_X70Y62 LUT4 (Prop_lut4_I3_O) 0.363 16.525 r u_matmul_axi_slave/crc_reg[30]_i_1/O net (fo=1, routed) 0.000 16.525 u_matmul_axi_slave/crc32_word_next1_return0[28] SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.702 17.874 u_matmul_axi_slave/sys_clk SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[30]/C clock pessimism -0.426 17.447 clock uncertainty -0.071 17.377 SLICE_X70Y62 FDSE (Setup_fdse_C_D) 0.118 17.495 u_matmul_axi_slave/crc_reg_reg[30] ------------------------------------------------------------------- required time 17.495 arrival time -16.525 ------------------------------------------------------------------- slack 0.969 Slack (MET) : 0.971ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[27]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 18.975ns (logic 5.382ns (28.364%) route 13.593ns (71.636%)) Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=3 LUT6=5) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) Source Clock Delay (SCD): -2.536ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O net (fo=15, routed) 0.871 16.108 u_matmul_axi_slave/crc32_word_next1_return1[1] SLICE_X69Y63 LUT5 (Prop_lut5_I3_O) 0.331 16.439 r u_matmul_axi_slave/crc_reg[27]_i_1/O net (fo=1, routed) 0.000 16.439 u_matmul_axi_slave/crc32_word_next1_return0[25] SLICE_X69Y63 FDSE r u_matmul_axi_slave/crc_reg_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk SLICE_X69Y63 FDSE r u_matmul_axi_slave/crc_reg_reg[27]/C clock pessimism -0.426 17.449 clock uncertainty -0.071 17.379 SLICE_X69Y63 FDSE (Setup_fdse_C_D) 0.031 17.410 u_matmul_axi_slave/crc_reg_reg[27] ------------------------------------------------------------------- required time 17.410 arrival time -16.439 ------------------------------------------------------------------- slack 0.971 Slack (MET) : 1.008ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[5] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.764ns (logic 5.026ns (34.045%) route 9.738ns (65.955%)) Logic Levels: 8 (LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.515 2.847 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) 0.124 2.971 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/O net (fo=1, routed) 0.999 3.970 u_snix_axil_cdma_mux_8ch/ep_rd_c0[5] SLICE_X38Y78 LUT6 (Prop_lut6_I1_O) 0.124 4.094 r u_snix_axil_cdma_mux_8ch/ram_reg_i_37/O net (fo=3, routed) 0.879 4.973 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_29 SLICE_X43Y73 LUT6 (Prop_lut6_I3_O) 0.124 5.097 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[5]_inst_i_1/O net (fo=2, routed) 3.685 8.782 ext_ram_data_IOBUF[5]_inst/I AE21 OBUFT (Prop_obuft_I_O) 3.564 12.347 r ext_ram_data_IOBUF[5]_inst/OBUFT/O net (fo=1, unset) 0.000 12.347 ext_ram_data[5] AE21 r ext_ram_data[5] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.347 ------------------------------------------------------------------- slack 1.008 Slack (MET) : 1.012ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[27] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.664ns (logic 6.836ns (46.615%) route 7.828ns (53.385%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.290 8.820 base_ram_data_IOBUF[27]_inst/T P20 OBUFT (TriStatE_obuft_T_O) 3.523 12.342 r base_ram_data_IOBUF[27]_inst/OBUFT/O net (fo=1, unset) 0.000 12.342 base_ram_data[27] P20 r base_ram_data[27] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.342 ------------------------------------------------------------------- slack 1.012 Slack (MET) : 1.016ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.660ns (logic 6.906ns (47.111%) route 7.753ns (52.889%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 2.950 8.745 ext_ram_data_IOBUF[3]_inst/T AE22 OBUFT (TriStatE_obuft_T_O) 3.593 12.338 r ext_ram_data_IOBUF[3]_inst/OBUFT/O net (fo=1, unset) 0.000 12.338 ext_ram_data[3] AE22 r ext_ram_data[3] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.338 ------------------------------------------------------------------- slack 1.016 Slack (MET) : 1.017ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.659ns (logic 6.844ns (46.685%) route 7.815ns (53.314%)) Logic Levels: 14 (CARRY4=7 LUT4=1 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 1.983 6.791 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X0Y121 LUT6 (Prop_lut6_I5_O) 0.124 6.915 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O net (fo=1, routed) 1.892 8.807 base_ram_be_n_OBUF[1] L22 OBUF (Prop_obuf_I_O) 3.531 12.337 r base_ram_be_n_OBUF[1]_inst/O net (fo=0) 0.000 12.337 base_ram_be_n[1] L22 r base_ram_be_n[1] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.337 ------------------------------------------------------------------- slack 1.017 Slack (MET) : 1.017ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[4] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.659ns (logic 6.905ns (47.105%) route 7.754ns (52.895%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 2.951 8.745 ext_ram_data_IOBUF[4]_inst/T AF22 OBUFT (TriStatE_obuft_T_O) 3.592 12.337 r ext_ram_data_IOBUF[4]_inst/OBUFT/O net (fo=1, unset) 0.000 12.337 ext_ram_data[4] AF22 r ext_ram_data[4] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.337 ------------------------------------------------------------------- slack 1.017 Slack (MET) : 1.018ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[5] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.754ns (logic 5.001ns (33.893%) route 9.753ns (66.107%)) Logic Levels: 8 (LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.418ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=132, routed) 1.515 2.847 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) 0.124 2.971 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/O net (fo=1, routed) 0.999 3.970 u_snix_axil_cdma_mux_8ch/ep_rd_c0[5] SLICE_X38Y78 LUT6 (Prop_lut6_I1_O) 0.124 4.094 r u_snix_axil_cdma_mux_8ch/ram_reg_i_37/O net (fo=3, routed) 0.879 4.973 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_29 SLICE_X43Y73 LUT6 (Prop_lut6_I3_O) 0.124 5.097 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[5]_inst_i_1/O net (fo=2, routed) 3.700 8.798 base_ram_data_IOBUF[5]_inst/I P24 OBUFT (Prop_obuft_I_O) 3.539 12.336 r base_ram_data_IOBUF[5]_inst/OBUFT/O net (fo=1, unset) 0.000 12.336 base_ram_data[5] P24 r base_ram_data[5] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.336 ------------------------------------------------------------------- slack 1.018 Slack (MET) : 1.019ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.656ns (logic 6.857ns (46.787%) route 7.799ns (53.213%)) Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 2.996 8.790 ext_ram_data_IOBUF[30]_inst/T AA19 OBUFT (TriStatE_obuft_T_O) 3.544 12.335 r ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.335 ext_ram_data[30] AA19 r ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.335 ------------------------------------------------------------------- slack 1.019 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y68 cdma_axil_b_bridge_reg/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X24Y67 cdma_axil_r_bridge_reg/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y67 cdma_axil_wr_active_reg/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y67 cdma_axil_wr_bridge_hold_reg/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[0]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[1]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[5]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[6]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[7]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[8]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[9]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[0]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[10]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[11]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[12]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X20Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[13]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[14]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[0]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[1]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[2]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[3]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[4]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[5]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[6]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[7]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[8]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[9]/C Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- From Clock: sys_clk To Clock: mlkem_clk_clk_pll Setup : 0 Failing Endpoints, Worst Slack 14.363ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 14.363ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.986ns (logic 1.344ns (26.958%) route 3.642ns (73.042%)) Logic Levels: 0 Clock Path Skew: -0.195ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 3.642 22.469 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[12] SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.260 36.832 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12] ------------------------------------------------------------------- required time 36.832 arrival time -22.469 ------------------------------------------------------------------- slack 14.363 Slack (MET) : 14.642ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.902ns (logic 1.317ns (26.864%) route 3.585ns (73.136%)) Logic Levels: 0 Clock Path Skew: -0.195ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.800 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 3.585 22.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[15] SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.064 37.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15] ------------------------------------------------------------------- required time 37.028 arrival time -22.386 ------------------------------------------------------------------- slack 14.642 Slack (MET) : 14.889ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.419ns (logic 1.344ns (30.411%) route 3.075ns (69.589%)) Logic Levels: 0 Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.829 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 3.075 21.905 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[18] SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.299 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18] ------------------------------------------------------------------- required time 36.794 arrival time -21.905 ------------------------------------------------------------------- slack 14.889 Slack (MET) : 15.059ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.297ns (logic 1.336ns (31.089%) route 2.961ns (68.911%)) Logic Levels: 0 Clock Path Skew: -0.195ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.821 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 2.961 21.783 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[28] SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/C clock pessimism -0.601 37.291 clock uncertainty -0.197 37.094 SLICE_X116Y76 FDRE (Setup_fdre_C_D) -0.252 36.842 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28] ------------------------------------------------------------------- required time 36.842 arrival time -21.783 ------------------------------------------------------------------- slack 15.059 Slack (MET) : 15.085ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.257ns (logic 1.344ns (31.570%) route 2.913ns (68.429%)) Logic Levels: 0 Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.829 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 2.913 21.743 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.266 36.827 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24] ------------------------------------------------------------------- required time 36.827 arrival time -21.743 ------------------------------------------------------------------- slack 15.085 Slack (MET) : 15.131ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.202ns (logic 1.344ns (31.982%) route 2.858ns (68.018%)) Logic Levels: 0 Clock Path Skew: -0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.511ns = ( 17.489 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.831 17.489 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/WCLK SLICE_X56Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y71 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.833 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/O net (fo=1, routed) 2.858 21.692 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[36] SLICE_X110Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X110Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/C clock pessimism -0.601 37.291 clock uncertainty -0.197 37.094 SLICE_X110Y71 FDRE (Setup_fdre_C_D) -0.271 36.823 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36] ------------------------------------------------------------------- required time 36.823 arrival time -21.692 ------------------------------------------------------------------- slack 15.131 Slack (MET) : 15.149ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.015ns (logic 1.344ns (33.474%) route 2.671ns (66.526%)) Logic Levels: 0 Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.926 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/O net (fo=1, routed) 2.671 21.597 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[6] SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/C clock pessimism -0.601 37.256 clock uncertainty -0.197 37.059 SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.313 36.746 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6] ------------------------------------------------------------------- required time 36.746 arrival time -21.597 ------------------------------------------------------------------- slack 15.149 Slack (MET) : 15.187ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.166ns (logic 1.336ns (32.067%) route 2.830ns (67.933%)) Logic Levels: 0 Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.821 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 2.830 21.652 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[22] SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.254 36.839 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22] ------------------------------------------------------------------- required time 36.839 arrival time -21.652 ------------------------------------------------------------------- slack 15.187 Slack (MET) : 15.190ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.336ns (logic 1.314ns (30.303%) route 3.022ns (69.697%)) Logic Levels: 0 Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 3.022 21.822 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[23] SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.081 37.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23] ------------------------------------------------------------------- required time 37.012 arrival time -21.822 ------------------------------------------------------------------- slack 15.190 Slack (MET) : 15.238ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.936ns (logic 1.344ns (34.149%) route 2.592ns (65.851%)) Logic Levels: 0 Clock Path Skew: -0.321ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.139ns = ( 37.861 - 40.000 ) Source Clock Delay (SCD): -2.420ns = ( 17.580 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.922 17.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.924 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 2.592 21.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[0] SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.689 37.861 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/C clock pessimism -0.601 37.260 clock uncertainty -0.197 37.063 SLICE_X77Y70 FDRE (Setup_fdre_C_D) -0.309 36.754 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0] ------------------------------------------------------------------- required time 36.754 arrival time -21.516 ------------------------------------------------------------------- slack 15.238 Slack (MET) : 15.346ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.027ns (logic 1.336ns (33.179%) route 2.691ns (66.821%)) Logic Levels: 0 Clock Path Skew: -0.193ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 2.691 21.510 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[16] SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/C clock pessimism -0.601 37.291 clock uncertainty -0.197 37.094 SLICE_X116Y76 FDRE (Setup_fdre_C_D) -0.238 36.856 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16] ------------------------------------------------------------------- required time 36.856 arrival time -21.510 ------------------------------------------------------------------- slack 15.346 Slack (MET) : 15.359ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.218ns (logic 1.317ns (31.224%) route 2.901ns (68.776%)) Logic Levels: 0 Clock Path Skew: -0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.807 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 2.901 21.708 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[3] SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/C clock pessimism -0.601 37.292 clock uncertainty -0.197 37.095 SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.028 37.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3] ------------------------------------------------------------------- required time 37.067 arrival time -21.708 ------------------------------------------------------------------- slack 15.359 Slack (MET) : 15.360ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.008ns (logic 1.336ns (33.331%) route 2.672ns (66.669%)) Logic Levels: 0 Clock Path Skew: -0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.826 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 2.672 21.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[4] SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/C clock pessimism -0.601 37.292 clock uncertainty -0.197 37.095 SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.237 36.858 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4] ------------------------------------------------------------------- required time 36.858 arrival time -21.499 ------------------------------------------------------------------- slack 15.360 Slack (MET) : 15.365ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.184ns (logic 1.309ns (31.283%) route 2.875ns (68.717%)) Logic Levels: 0 Clock Path Skew: -0.195ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.792 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 2.875 21.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[13] SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.059 37.033 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13] ------------------------------------------------------------------- required time 37.033 arrival time -21.668 ------------------------------------------------------------------- slack 15.365 Slack (MET) : 15.371ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.144ns (logic 1.309ns (31.591%) route 2.835ns (68.409%)) Logic Levels: 0 Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.794 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 2.835 21.629 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[19] SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.093 37.000 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19] ------------------------------------------------------------------- required time 37.000 arrival time -21.629 ------------------------------------------------------------------- slack 15.371 Slack (MET) : 15.375ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.000ns (logic 1.309ns (32.724%) route 2.691ns (67.276%)) Logic Levels: 0 Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 2.691 21.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7] SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/C clock pessimism -0.601 37.256 clock uncertainty -0.197 37.059 SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.102 36.957 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7] ------------------------------------------------------------------- required time 36.957 arrival time -21.583 ------------------------------------------------------------------- slack 15.375 Slack (MET) : 15.382ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.988ns (logic 1.344ns (33.703%) route 2.644ns (66.297%)) Logic Levels: 0 Clock Path Skew: -0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.834 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 2.644 21.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[0] SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/C clock pessimism -0.601 37.292 clock uncertainty -0.197 37.095 SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.235 36.860 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0] ------------------------------------------------------------------- required time 36.860 arrival time -21.478 ------------------------------------------------------------------- slack 15.382 Slack (MET) : 15.406ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.814ns (logic 1.344ns (35.240%) route 2.470ns (64.760%)) Logic Levels: 0 Clock Path Skew: -0.324ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.919 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 2.470 21.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0] SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/C clock pessimism -0.601 37.252 clock uncertainty -0.197 37.055 SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.260 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0] ------------------------------------------------------------------- required time 36.795 arrival time -21.389 ------------------------------------------------------------------- slack 15.406 Slack (MET) : 15.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.896ns (logic 1.343ns (34.471%) route 2.553ns (65.529%)) Logic Levels: 0 Clock Path Skew: -0.195ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.826 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 2.553 21.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[14] SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/C clock pessimism -0.601 37.289 clock uncertainty -0.197 37.092 SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.287 36.805 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14] ------------------------------------------------------------------- required time 36.805 arrival time -21.379 ------------------------------------------------------------------- slack 15.426 Slack (MET) : 15.429ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.762ns (logic 1.343ns (35.695%) route 2.419ns (64.305%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.919 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/O net (fo=1, routed) 2.419 21.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[8] SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/C clock pessimism -0.601 37.252 clock uncertainty -0.197 37.055 SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.287 36.768 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8] ------------------------------------------------------------------- required time 36.768 arrival time -21.339 ------------------------------------------------------------------- slack 15.429 Slack (MET) : 15.440ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.128ns (logic 1.314ns (31.835%) route 2.814ns (68.165%)) Logic Levels: 0 Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 2.814 21.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[29] SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.040 37.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29] ------------------------------------------------------------------- required time 37.053 arrival time -21.613 ------------------------------------------------------------------- slack 15.440 Slack (MET) : 15.459ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.955ns (logic 1.317ns (33.302%) route 2.638ns (66.698%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.893 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/O net (fo=1, routed) 2.638 21.531 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[9] SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/C clock pessimism -0.601 37.252 clock uncertainty -0.197 37.055 SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.065 36.990 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9] ------------------------------------------------------------------- required time 36.990 arrival time -21.531 ------------------------------------------------------------------- slack 15.459 Slack (MET) : 15.477ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.733ns (logic 1.336ns (35.784%) route 2.397ns (64.216%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.912 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/O net (fo=1, routed) 2.397 21.310 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[10] SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/C clock pessimism -0.601 37.252 clock uncertainty -0.197 37.055 SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.268 36.787 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10] ------------------------------------------------------------------- required time 36.787 arrival time -21.310 ------------------------------------------------------------------- slack 15.477 Slack (MET) : 15.480ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.063ns (logic 1.314ns (32.340%) route 2.749ns (67.660%)) Logic Levels: 0 Clock Path Skew: -0.194ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.797 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 2.749 21.547 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[17] SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.067 37.026 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17] ------------------------------------------------------------------- required time 37.026 arrival time -21.547 ------------------------------------------------------------------- slack 15.480 Slack (MET) : 15.482ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.864ns (logic 1.344ns (34.786%) route 2.520ns (65.214%)) Logic Levels: 0 Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 2.520 21.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[30] SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/C clock pessimism -0.601 37.292 clock uncertainty -0.197 37.095 SLICE_X117Y77 FDRE (Setup_fdre_C_D) -0.271 36.824 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30] ------------------------------------------------------------------- required time 36.824 arrival time -21.342 ------------------------------------------------------------------- slack 15.482 Slack (MET) : 15.506ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.864ns (logic 1.317ns (34.080%) route 2.547ns (65.920%)) Logic Levels: 0 Clock Path Skew: -0.328ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) Source Clock Delay (SCD): -2.417ns = ( 17.583 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.925 17.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X36Y66 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y66 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.900 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/O net (fo=1, routed) 2.547 21.448 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[15] SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/C clock pessimism -0.601 37.256 clock uncertainty -0.197 37.059 SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.105 36.954 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15] ------------------------------------------------------------------- required time 36.954 arrival time -21.448 ------------------------------------------------------------------- slack 15.506 Slack (MET) : 15.550ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.822ns (logic 1.309ns (34.245%) route 2.513ns (65.755%)) Logic Levels: 0 Clock Path Skew: -0.328ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) Source Clock Delay (SCD): -2.417ns = ( 17.583 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.925 17.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X36Y66 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y66 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.892 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/O net (fo=1, routed) 2.513 21.406 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[13] SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/C clock pessimism -0.601 37.256 clock uncertainty -0.197 37.059 SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.103 36.956 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13] ------------------------------------------------------------------- required time 36.956 arrival time -21.406 ------------------------------------------------------------------- slack 15.550 Slack (MET) : 15.552ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.834ns (logic 1.309ns (34.141%) route 2.525ns (65.859%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.884 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/O net (fo=1, routed) 2.525 21.410 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[1] SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/C clock pessimism -0.601 37.251 clock uncertainty -0.197 37.054 SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.093 36.961 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1] ------------------------------------------------------------------- required time 36.961 arrival time -21.410 ------------------------------------------------------------------- slack 15.552 Slack (MET) : 15.552ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 4.012ns (logic 1.317ns (32.824%) route 2.695ns (67.176%)) Logic Levels: 0 Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.802 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 2.695 21.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[27] SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.043 37.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27] ------------------------------------------------------------------- required time 37.050 arrival time -21.498 ------------------------------------------------------------------- slack 15.552 Slack (MET) : 15.555ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.961ns (logic 1.317ns (33.248%) route 2.644ns (66.752%)) Logic Levels: 0 Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.802 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 2.644 21.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[21] SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.092 37.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21] ------------------------------------------------------------------- required time 37.001 arrival time -21.447 ------------------------------------------------------------------- slack 15.555 Slack (MET) : 15.555ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.607ns (logic 1.343ns (37.237%) route 2.264ns (62.763%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.918 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O net (fo=1, routed) 2.264 21.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2] SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/C clock pessimism -0.601 37.251 clock uncertainty -0.197 37.054 SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.317 36.737 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2] ------------------------------------------------------------------- required time 36.737 arrival time -21.182 ------------------------------------------------------------------- slack 15.555 Slack (MET) : 15.654ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.719ns (logic 1.309ns (35.195%) route 2.410ns (64.805%)) Logic Levels: 0 Clock Path Skew: -0.328ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.150ns = ( 37.850 - 40.000 ) Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.885 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 2.410 21.296 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[7] SLICE_X78Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.678 37.850 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X78Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/C clock pessimism -0.601 37.249 clock uncertainty -0.197 37.052 SLICE_X78Y72 FDRE (Setup_fdre_C_D) -0.103 36.949 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7] ------------------------------------------------------------------- required time 36.949 arrival time -21.296 ------------------------------------------------------------------- slack 15.654 Slack (MET) : 15.659ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.762ns (logic 1.317ns (35.012%) route 2.445ns (64.988%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.892 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/O net (fo=1, routed) 2.445 21.337 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[3] SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/C clock pessimism -0.601 37.251 clock uncertainty -0.197 37.054 SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.058 36.996 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3] ------------------------------------------------------------------- required time 36.996 arrival time -21.337 ------------------------------------------------------------------- slack 15.659 Slack (MET) : 15.683ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.690ns (logic 1.309ns (35.473%) route 2.381ns (64.527%)) Logic Levels: 0 Clock Path Skew: -0.328ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.146ns = ( 37.854 - 40.000 ) Source Clock Delay (SCD): -2.420ns = ( 17.580 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.922 17.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/O net (fo=1, routed) 2.381 21.271 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[1] SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.682 37.854 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/C clock pessimism -0.601 37.253 clock uncertainty -0.197 37.056 SLICE_X78Y68 FDRE (Setup_fdre_C_D) -0.103 36.953 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1] ------------------------------------------------------------------- required time 36.953 arrival time -21.271 ------------------------------------------------------------------- slack 15.683 Slack (MET) : 15.729ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.413ns (logic 1.343ns (39.347%) route 2.070ns (60.653%)) Logic Levels: 0 Clock Path Skew: -0.330ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.146ns = ( 37.854 - 40.000 ) Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.925 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/O net (fo=1, routed) 2.070 20.996 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[8] SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.682 37.854 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/C clock pessimism -0.601 37.253 clock uncertainty -0.197 37.056 SLICE_X78Y68 FDRE (Setup_fdre_C_D) -0.332 36.724 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8] ------------------------------------------------------------------- required time 36.724 arrival time -20.996 ------------------------------------------------------------------- slack 15.729 Slack (MET) : 15.768ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.779ns (logic 1.309ns (34.643%) route 2.470ns (65.357%)) Logic Levels: 0 Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.794 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 2.470 21.264 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.061 37.032 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25] ------------------------------------------------------------------- required time 37.032 arrival time -21.264 ------------------------------------------------------------------- slack 15.768 Slack (MET) : 15.770ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.381ns (logic 1.343ns (39.723%) route 2.038ns (60.277%)) Logic Levels: 0 Clock Path Skew: -0.324ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.139ns = ( 37.861 - 40.000 ) Source Clock Delay (SCD): -2.417ns = ( 17.583 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.925 17.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X36Y66 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y66 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.926 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/O net (fo=1, routed) 2.038 20.964 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[14] SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.689 37.861 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C clock pessimism -0.601 37.260 clock uncertainty -0.197 37.063 SLICE_X77Y70 FDRE (Setup_fdre_C_D) -0.329 36.734 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14] ------------------------------------------------------------------- required time 36.734 arrival time -20.964 ------------------------------------------------------------------- slack 15.770 Slack (MET) : 15.794ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.497ns (logic 1.343ns (38.409%) route 2.154ns (61.591%)) Logic Levels: 0 Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.828 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 2.154 20.982 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[20] SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.317 36.776 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20] ------------------------------------------------------------------- required time 36.776 arrival time -20.982 ------------------------------------------------------------------- slack 15.794 Slack (MET) : 15.816ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.720ns (logic 1.309ns (35.188%) route 2.411ns (64.812%)) Logic Levels: 0 Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.787 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 2.411 21.198 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[31] SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/C clock pessimism -0.601 37.292 clock uncertainty -0.197 37.095 SLICE_X117Y77 FDRE (Setup_fdre_C_D) -0.081 37.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31] ------------------------------------------------------------------- required time 37.014 arrival time -21.198 ------------------------------------------------------------------- slack 15.816 Slack (MET) : 15.821ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.408ns (logic 1.336ns (39.197%) route 2.072ns (60.803%)) Logic Levels: 0 Clock Path Skew: -0.320ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.136ns = ( 37.864 - 40.000 ) Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.918 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/O net (fo=1, routed) 2.072 20.991 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[10] SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.692 37.864 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/C clock pessimism -0.601 37.263 clock uncertainty -0.197 37.066 SLICE_X76Y67 FDRE (Setup_fdre_C_D) -0.254 36.812 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10] ------------------------------------------------------------------- required time 36.812 arrival time -20.991 ------------------------------------------------------------------- slack 15.821 Slack (MET) : 15.826ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.590ns (logic 1.314ns (36.599%) route 2.276ns (63.401%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/O net (fo=1, routed) 2.276 21.166 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[5] SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/C clock pessimism -0.601 37.251 clock uncertainty -0.197 37.054 SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.062 36.992 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5] ------------------------------------------------------------------- required time 36.992 arrival time -21.166 ------------------------------------------------------------------- slack 15.826 Slack (MET) : 15.830ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.395ns (logic 1.336ns (39.356%) route 2.059ns (60.644%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.911 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 2.059 20.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[4] SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/C clock pessimism -0.601 37.251 clock uncertainty -0.197 37.054 SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.254 36.800 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4] ------------------------------------------------------------------- required time 36.800 arrival time -20.970 ------------------------------------------------------------------- slack 15.830 Slack (MET) : 15.834ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.501ns (logic 1.343ns (38.357%) route 2.158ns (61.643%)) Logic Levels: 0 Clock Path Skew: -0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.833 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 2.158 20.992 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[2] SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/C clock pessimism -0.601 37.292 clock uncertainty -0.197 37.095 SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.269 36.826 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2] ------------------------------------------------------------------- required time 36.826 arrival time -20.992 ------------------------------------------------------------------- slack 15.834 Slack (MET) : 15.836ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.395ns (logic 1.344ns (39.592%) route 2.051ns (60.408%)) Logic Levels: 0 Clock Path Skew: -0.326ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.920 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/O net (fo=1, routed) 2.051 20.971 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[6] SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/C clock pessimism -0.601 37.251 clock uncertainty -0.197 37.054 SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.247 36.807 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6] ------------------------------------------------------------------- required time 36.807 arrival time -20.971 ------------------------------------------------------------------- slack 15.836 Slack (MET) : 15.842ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.469ns (logic 1.344ns (38.739%) route 2.125ns (61.261%)) Logic Levels: 0 Clock Path Skew: -0.185ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.525ns = ( 17.475 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.817 17.475 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) 1.344 18.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 2.125 20.945 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6] SLICE_X114Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X114Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/C clock pessimism -0.601 37.291 clock uncertainty -0.197 37.094 SLICE_X114Y72 FDRE (Setup_fdre_C_D) -0.307 36.787 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6] ------------------------------------------------------------------- required time 36.787 arrival time -20.945 ------------------------------------------------------------------- slack 15.842 Slack (MET) : 15.908ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.473ns (logic 1.336ns (38.463%) route 2.137ns (61.537%)) Logic Levels: 0 Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) 1.336 18.814 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/O net (fo=1, routed) 2.137 20.952 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[34] SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/C clock pessimism -0.601 37.292 clock uncertainty -0.197 37.095 SLICE_X116Y77 FDRE (Setup_fdre_C_D) -0.235 36.860 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34] ------------------------------------------------------------------- required time 36.860 arrival time -20.952 ------------------------------------------------------------------- slack 15.908 Slack (MET) : 15.958ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.613ns (logic 1.317ns (36.447%) route 2.296ns (63.553%)) Logic Levels: 0 Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) 1.317 18.795 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/O net (fo=1, routed) 2.296 21.092 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[33] SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/C clock pessimism -0.601 37.292 clock uncertainty -0.197 37.095 SLICE_X116Y77 FDRE (Setup_fdre_C_D) -0.045 37.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33] ------------------------------------------------------------------- required time 37.050 arrival time -21.092 ------------------------------------------------------------------- slack 15.958 Slack (MET) : 15.958ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.633ns (logic 1.314ns (36.165%) route 2.319ns (63.835%)) Logic Levels: 0 Clock Path Skew: -0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) 1.314 18.804 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 2.319 21.124 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[5] SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/C clock pessimism -0.601 37.292 clock uncertainty -0.197 37.095 SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.013 37.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5] ------------------------------------------------------------------- required time 37.082 arrival time -21.124 ------------------------------------------------------------------- slack 15.958 Slack (MET) : 15.961ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.365ns (logic 1.343ns (39.913%) route 2.022ns (60.087%)) Logic Levels: 0 Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) 1.343 18.828 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 2.022 20.850 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[26] SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/C clock pessimism -0.601 37.290 clock uncertainty -0.197 37.093 SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.282 36.811 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26] ------------------------------------------------------------------- required time 36.811 arrival time -20.850 ------------------------------------------------------------------- slack 15.961 Slack (MET) : 15.990ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 3.572ns (logic 1.309ns (36.651%) route 2.263ns (63.349%)) Logic Levels: 0 Clock Path Skew: -0.199ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) 1.309 18.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 2.263 21.062 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1] SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/C clock pessimism -0.601 37.292 clock uncertainty -0.197 37.095 SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.043 37.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1] ------------------------------------------------------------------- required time 37.052 arrival time -21.062 ------------------------------------------------------------------- slack 15.990 --------------------------------------------------------------------------------------------------- From Clock: mlkem_clk_clk_pll To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 16.175ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 16.175ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 3.211ns (logic 1.343ns (41.819%) route 1.868ns (58.181%)) Logic Levels: 0 Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) Source Clock Delay (SCD): -2.521ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.178 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 1.868 0.691 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[14] SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/C clock pessimism -0.601 17.368 clock uncertainty -0.197 17.171 SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.305 16.866 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14] ------------------------------------------------------------------- required time 16.866 arrival time -0.691 ------------------------------------------------------------------- slack 16.175 Slack (MET) : 16.288ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 3.133ns (logic 1.344ns (42.898%) route 1.789ns (57.102%)) Logic Levels: 0 Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) Source Clock Delay (SCD): -2.521ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.177 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 1.789 0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/C clock pessimism -0.601 17.368 clock uncertainty -0.197 17.171 SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.271 16.900 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12] ------------------------------------------------------------------- required time 16.900 arrival time -0.612 ------------------------------------------------------------------- slack 16.288 Slack (MET) : 16.322ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 3.253ns (logic 1.309ns (40.244%) route 1.944ns (59.756%)) Logic Levels: 0 Clock Path Skew: -0.120ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) Source Clock Delay (SCD): -2.515ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 1.944 0.738 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/C clock pessimism -0.601 17.366 clock uncertainty -0.197 17.169 SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.109 17.060 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7] ------------------------------------------------------------------- required time 17.060 arrival time -0.738 ------------------------------------------------------------------- slack 16.322 Slack (MET) : 16.382ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.989ns (logic 1.343ns (44.934%) route 1.646ns (55.066%)) Logic Levels: 0 Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) Source Clock Delay (SCD): -2.516ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.173 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 1.646 0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2] SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/C clock pessimism -0.601 17.368 clock uncertainty -0.197 17.171 SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.316 16.855 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2] ------------------------------------------------------------------- required time 16.855 arrival time -0.473 ------------------------------------------------------------------- slack 16.382 Slack (MET) : 16.446ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 3.152ns (logic 1.309ns (41.524%) route 1.843ns (58.476%)) Logic Levels: 0 Clock Path Skew: -0.112ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) Source Clock Delay (SCD): -2.521ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.212 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 1.843 0.632 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/C clock pessimism -0.601 17.368 clock uncertainty -0.197 17.171 SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.093 17.078 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13] ------------------------------------------------------------------- required time 17.078 arrival time -0.632 ------------------------------------------------------------------- slack 16.446 Slack (MET) : 16.520ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.917ns (logic 1.336ns (45.800%) route 1.581ns (54.200%)) Logic Levels: 0 Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) Source Clock Delay (SCD): -2.516ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.180 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 1.581 0.401 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4] SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/C clock pessimism -0.601 17.368 clock uncertainty -0.197 17.171 SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.250 16.921 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4] ------------------------------------------------------------------- required time 16.921 arrival time -0.401 ------------------------------------------------------------------- slack 16.520 Slack (MET) : 16.587ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.822ns (logic 1.336ns (47.335%) route 1.486ns (52.665%)) Logic Levels: 0 Clock Path Skew: -0.120ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) Source Clock Delay (SCD): -2.515ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.179 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 1.486 0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10] SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/C clock pessimism -0.601 17.366 clock uncertainty -0.197 17.169 SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.274 16.895 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10] ------------------------------------------------------------------- required time 16.895 arrival time -0.308 ------------------------------------------------------------------- slack 16.587 Slack (MET) : 16.599ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.995ns (logic 1.309ns (43.709%) route 1.686ns (56.291%)) Logic Levels: 0 Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) Source Clock Delay (SCD): -2.516ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 1.686 0.479 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/C clock pessimism -0.601 17.368 clock uncertainty -0.197 17.171 SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.093 17.078 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1] ------------------------------------------------------------------- required time 17.078 arrival time -0.479 ------------------------------------------------------------------- slack 16.599 Slack (MET) : 16.680ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.736ns (logic 1.344ns (49.121%) route 1.392ns (50.879%)) Logic Levels: 0 Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) Source Clock Delay (SCD): -2.516ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.172 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 1.392 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0] SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/C clock pessimism -0.601 17.368 clock uncertainty -0.197 17.171 SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.271 16.900 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0] ------------------------------------------------------------------- required time 16.900 arrival time -0.221 ------------------------------------------------------------------- slack 16.680 Slack (MET) : 16.714ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.930ns (logic 1.314ns (44.850%) route 1.616ns (55.150%)) Logic Levels: 0 Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) Source Clock Delay (SCD): -2.516ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 1.616 0.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C clock pessimism -0.601 17.368 clock uncertainty -0.197 17.171 SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.043 17.128 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5] ------------------------------------------------------------------- required time 17.128 arrival time -0.414 ------------------------------------------------------------------- slack 16.714 Slack (MET) : 16.930ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.383ns (logic 1.343ns (56.369%) route 1.040ns (43.631%)) Logic Levels: 0 Clock Path Skew: -0.205ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.177 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 1.040 -0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C clock pessimism -0.601 17.276 clock uncertainty -0.197 17.079 SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.286 16.793 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26] ------------------------------------------------------------------- required time 16.793 arrival time 0.137 ------------------------------------------------------------------- slack 16.930 Slack (MET) : 16.970ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.472ns (logic 1.344ns (54.377%) route 1.128ns (45.623%)) Logic Levels: 0 Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) Source Clock Delay (SCD): -2.515ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.171 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 1.128 -0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C clock pessimism -0.601 17.368 clock uncertainty -0.197 17.171 SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.244 16.927 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6] ------------------------------------------------------------------- required time 16.927 arrival time 0.043 ------------------------------------------------------------------- slack 16.970 Slack (MET) : 16.987ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.297ns (logic 1.343ns (58.459%) route 0.954ns (41.541%)) Logic Levels: 0 Clock Path Skew: -0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.180 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.954 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C clock pessimism -0.601 17.276 clock uncertainty -0.197 17.079 SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.317 16.762 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20] ------------------------------------------------------------------- required time 16.762 arrival time 0.225 ------------------------------------------------------------------- slack 16.987 Slack (MET) : 16.991ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.542ns (logic 1.317ns (51.811%) route 1.225ns (48.189%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.022ns = ( 17.978 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O net (fo=1, routed) 1.225 0.128 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.806 17.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C clock pessimism -0.601 17.377 clock uncertainty -0.197 17.180 SLICE_X19Y76 FDRE (Setup_fdre_C_D) -0.061 17.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33] ------------------------------------------------------------------- required time 17.119 arrival time -0.128 ------------------------------------------------------------------- slack 16.991 Slack (MET) : 17.017ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.587ns (logic 1.317ns (50.909%) route 1.270ns (49.091%)) Logic Levels: 0 Clock Path Skew: -0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) Source Clock Delay (SCD): -2.516ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.199 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 1.270 0.071 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C clock pessimism -0.601 17.366 clock uncertainty -0.197 17.169 SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.081 17.088 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3] ------------------------------------------------------------------- required time 17.088 arrival time -0.071 ------------------------------------------------------------------- slack 17.017 Slack (MET) : 17.045ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.595ns (logic 1.317ns (50.744%) route 1.278ns (49.256%)) Logic Levels: 0 Clock Path Skew: -0.120ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) Source Clock Delay (SCD): -2.515ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.198 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 1.278 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C clock pessimism -0.601 17.366 clock uncertainty -0.197 17.169 SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.043 17.126 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9] ------------------------------------------------------------------- required time 17.126 arrival time -0.081 ------------------------------------------------------------------- slack 17.045 Slack (MET) : 17.067ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.418ns (logic 0.456ns (18.857%) route 1.962ns (81.143%)) Logic Levels: 0 Clock Path Skew: -0.213ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) Source Clock Delay (SCD): -2.419ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.923 -2.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.456 -1.963 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 1.962 -0.000 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.798 17.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.601 17.369 clock uncertainty -0.197 17.172 SLICE_X24Y73 FDCE (Setup_fdce_C_D) -0.105 17.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 17.067 arrival time 0.000 ------------------------------------------------------------------- slack 17.067 Slack (MET) : 17.092ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.462ns (logic 1.314ns (53.376%) route 1.148ns (46.624%)) Logic Levels: 0 Clock Path Skew: -0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 1.148 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C clock pessimism -0.601 17.274 clock uncertainty -0.197 17.077 SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.043 17.034 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29] ------------------------------------------------------------------- required time 17.034 arrival time 0.058 ------------------------------------------------------------------- slack 17.092 Slack (MET) : 17.095ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.436ns (logic 1.317ns (54.066%) route 1.119ns (45.934%)) Logic Levels: 0 Clock Path Skew: -0.212ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) Source Clock Delay (SCD): -2.409ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.092 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 1.119 0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C clock pessimism -0.601 17.380 clock uncertainty -0.197 17.183 SLICE_X17Y78 FDRE (Setup_fdre_C_D) -0.061 17.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39] ------------------------------------------------------------------- required time 17.122 arrival time -0.027 ------------------------------------------------------------------- slack 17.095 Slack (MET) : 17.100ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.301ns (logic 1.343ns (58.359%) route 0.958ns (41.641%)) Logic Levels: 0 Clock Path Skew: -0.120ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) Source Clock Delay (SCD): -2.515ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.172 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 0.958 -0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C clock pessimism -0.601 17.366 clock uncertainty -0.197 17.169 SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.282 16.887 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8] ------------------------------------------------------------------- required time 16.887 arrival time 0.213 ------------------------------------------------------------------- slack 17.100 Slack (MET) : 17.150ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.212ns (logic 1.336ns (60.403%) route 0.876ns (39.597%)) Logic Levels: 0 Clock Path Skew: -0.204ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.187 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.876 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C clock pessimism -0.601 17.274 clock uncertainty -0.197 17.077 SLICE_X62Y81 FDRE (Setup_fdre_C_D) -0.238 16.839 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22] ------------------------------------------------------------------- required time 16.839 arrival time 0.311 ------------------------------------------------------------------- slack 17.150 Slack (MET) : 17.198ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.407ns (logic 1.314ns (54.587%) route 1.093ns (45.413%)) Logic Levels: 0 Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) Source Clock Delay (SCD): -2.515ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.201 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 1.093 -0.107 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C clock pessimism -0.601 17.368 clock uncertainty -0.197 17.171 SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.081 17.090 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11] ------------------------------------------------------------------- required time 17.090 arrival time 0.107 ------------------------------------------------------------------- slack 17.198 Slack (MET) : 17.220ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.336ns (logic 1.317ns (56.385%) route 1.019ns (43.615%)) Logic Levels: 0 Clock Path Skew: -0.205ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 1.019 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27] SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C clock pessimism -0.601 17.276 clock uncertainty -0.197 17.079 SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.043 17.036 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27] ------------------------------------------------------------------- required time 17.036 arrival time 0.184 ------------------------------------------------------------------- slack 17.220 Slack (MET) : 17.264ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.241ns (logic 1.314ns (58.629%) route 0.927ns (41.371%)) Logic Levels: 0 Clock Path Skew: -0.206ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) Source Clock Delay (SCD): -2.521ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 0.927 -0.279 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C clock pessimism -0.601 17.274 clock uncertainty -0.197 17.077 SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.093 16.984 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17] ------------------------------------------------------------------- required time 16.984 arrival time 0.279 ------------------------------------------------------------------- slack 17.264 Slack (MET) : 17.264ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.063ns (logic 1.336ns (64.747%) route 0.727ns (35.253%)) Logic Levels: 0 Clock Path Skew: -0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.184 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 0.727 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C clock pessimism -0.601 17.274 clock uncertainty -0.197 17.077 SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.269 16.808 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28] ------------------------------------------------------------------- required time 16.808 arrival time 0.456 ------------------------------------------------------------------- slack 17.264 Slack (MET) : 17.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.053ns (logic 1.336ns (65.060%) route 0.717ns (34.940%)) Logic Levels: 0 Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK SLICE_X22Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y72 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.078 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 0.717 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.798 17.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C clock pessimism -0.601 17.369 clock uncertainty -0.197 17.172 SLICE_X28Y72 FDRE (Setup_fdre_C_D) -0.265 16.907 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4] ------------------------------------------------------------------- required time 16.907 arrival time 0.360 ------------------------------------------------------------------- slack 17.267 Slack (MET) : 17.269ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.055ns (logic 1.336ns (65.010%) route 0.719ns (34.990%)) Logic Levels: 0 Clock Path Skew: -0.206ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) Source Clock Delay (SCD): -2.521ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.719 -0.466 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C clock pessimism -0.601 17.274 clock uncertainty -0.197 17.077 SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.274 16.803 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16] ------------------------------------------------------------------- required time 16.803 arrival time 0.466 ------------------------------------------------------------------- slack 17.269 Slack (MET) : 17.276ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.013ns (logic 1.343ns (66.730%) route 0.670ns (33.270%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.022ns = ( 17.978 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.071 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 0.670 -0.401 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.806 17.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C clock pessimism -0.601 17.377 clock uncertainty -0.197 17.180 SLICE_X19Y76 FDRE (Setup_fdre_C_D) -0.305 16.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32] ------------------------------------------------------------------- required time 16.875 arrival time 0.401 ------------------------------------------------------------------- slack 17.276 Slack (MET) : 17.295ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.030ns (logic 0.419ns (20.636%) route 1.611ns (79.364%)) Logic Levels: 0 Clock Path Skew: -0.213ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) Source Clock Delay (SCD): -2.400ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.419 -1.981 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=5, routed) 1.611 -0.369 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.601 17.388 clock uncertainty -0.197 17.191 SLICE_X15Y87 FDCE (Setup_fdce_C_D) -0.265 16.926 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 16.926 arrival time 0.369 ------------------------------------------------------------------- slack 17.295 Slack (MET) : 17.298ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.211ns (logic 1.309ns (59.215%) route 0.902ns (40.785%)) Logic Levels: 0 Clock Path Skew: -0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.902 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C clock pessimism -0.601 17.276 clock uncertainty -0.197 17.079 SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.093 16.986 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19] ------------------------------------------------------------------- required time 16.986 arrival time 0.312 ------------------------------------------------------------------- slack 17.298 Slack (MET) : 17.298ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.200ns (logic 0.456ns (20.732%) route 1.744ns (79.268%)) Logic Levels: 0 Clock Path Skew: -0.213ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.027ns = ( 17.973 - 20.000 ) Source Clock Delay (SCD): -2.416ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.926 -2.416 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y79 FDCE (Prop_fdce_C_Q) 0.456 -1.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 1.744 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.801 17.973 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.601 17.372 clock uncertainty -0.197 17.175 SLICE_X27Y78 FDCE (Setup_fdce_C_D) -0.093 17.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 17.082 arrival time 0.216 ------------------------------------------------------------------- slack 17.298 Slack (MET) : 17.351ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.004ns (logic 0.419ns (20.911%) route 1.585ns (79.089%)) Logic Levels: 0 Clock Path Skew: -0.213ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) Source Clock Delay (SCD): -2.419ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.923 -2.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.419 -2.000 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 1.585 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.798 17.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.601 17.369 clock uncertainty -0.197 17.172 SLICE_X26Y73 FDCE (Setup_fdce_C_D) -0.236 16.936 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 16.936 arrival time 0.415 ------------------------------------------------------------------- slack 17.351 Slack (MET) : 17.368ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.159ns (logic 1.309ns (60.638%) route 0.850ns (39.362%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.850 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C clock pessimism -0.601 17.368 clock uncertainty -0.197 17.171 SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.058 17.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31] ------------------------------------------------------------------- required time 17.113 arrival time 0.255 ------------------------------------------------------------------- slack 17.368 Slack (MET) : 17.377ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.108ns (logic 0.456ns (21.629%) route 1.652ns (78.371%)) Logic Levels: 0 Clock Path Skew: -0.213ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) Source Clock Delay (SCD): -2.400ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.456 -1.944 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=3, routed) 1.652 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2] SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.601 17.388 clock uncertainty -0.197 17.191 SLICE_X15Y87 FDCE (Setup_fdce_C_D) -0.105 17.086 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 17.086 arrival time 0.291 ------------------------------------------------------------------- slack 17.377 Slack (MET) : 17.380ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.944ns (logic 0.419ns (21.557%) route 1.525ns (78.443%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 17.891 - 20.000 ) Source Clock Delay (SCD): -2.501ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.841 -2.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.419 -2.082 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 1.525 -0.557 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.719 17.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.601 17.290 clock uncertainty -0.197 17.093 SLICE_X114Y76 FDCE (Setup_fdce_C_D) -0.270 16.823 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 16.823 arrival time 0.557 ------------------------------------------------------------------- slack 17.380 Slack (MET) : 17.388ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.108ns (logic 0.456ns (21.629%) route 1.652ns (78.371%)) Logic Levels: 0 Clock Path Skew: -0.212ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.027ns = ( 17.973 - 20.000 ) Source Clock Delay (SCD): -2.417ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.925 -2.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y78 FDCE (Prop_fdce_C_Q) 0.456 -1.961 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 1.652 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.801 17.973 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.601 17.372 clock uncertainty -0.197 17.175 SLICE_X27Y78 FDCE (Setup_fdce_C_D) -0.095 17.080 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 17.080 arrival time 0.308 ------------------------------------------------------------------- slack 17.388 Slack (MET) : 17.399ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.106ns (logic 0.518ns (24.592%) route 1.588ns (75.408%)) Logic Levels: 0 Clock Path Skew: -0.203ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.096ns = ( 17.904 - 20.000 ) Source Clock Delay (SCD): -2.495ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X112Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y71 FDCE (Prop_fdce_C_Q) 0.518 -1.977 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q net (fo=2, routed) 1.588 -0.388 u_fft_mlkem_axi_slave/mlkem_intr_m SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.732 17.904 u_fft_mlkem_axi_slave/sys_clk SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C clock pessimism -0.601 17.303 clock uncertainty -0.197 17.106 SLICE_X117Y61 FDCE (Setup_fdce_C_D) -0.095 17.011 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0] ------------------------------------------------------------------- required time 17.011 arrival time 0.388 ------------------------------------------------------------------- slack 17.399 Slack (MET) : 17.403ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.095ns (logic 0.456ns (21.761%) route 1.639ns (78.239%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) Source Clock Delay (SCD): -2.425ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.917 -2.425 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X33Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y74 FDCE (Prop_fdce_C_Q) 0.456 -1.969 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 1.639 -0.329 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.601 17.366 clock uncertainty -0.197 17.169 SLICE_X30Y74 FDCE (Setup_fdce_C_D) -0.095 17.074 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 17.074 arrival time 0.329 ------------------------------------------------------------------- slack 17.403 Slack (MET) : 17.408ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.088ns (logic 0.456ns (21.835%) route 1.632ns (78.165%)) Logic Levels: 0 Clock Path Skew: -0.212ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 17.990 - 20.000 ) Source Clock Delay (SCD): -2.400ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.456 -1.944 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 1.632 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.818 17.990 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.601 17.389 clock uncertainty -0.197 17.192 SLICE_X15Y88 FDCE (Setup_fdce_C_D) -0.095 17.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 17.097 arrival time 0.311 ------------------------------------------------------------------- slack 17.408 Slack (MET) : 17.411ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.087ns (logic 0.456ns (21.845%) route 1.631ns (78.155%)) Logic Levels: 0 Clock Path Skew: -0.212ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns = ( 17.990 - 20.000 ) Source Clock Delay (SCD): -2.400ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.456 -1.944 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 1.631 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.818 17.990 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.601 17.389 clock uncertainty -0.197 17.192 SLICE_X15Y88 FDCE (Setup_fdce_C_D) -0.093 17.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 17.099 arrival time 0.312 ------------------------------------------------------------------- slack 17.411 Slack (MET) : 17.415ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.084ns (logic 0.456ns (21.879%) route 1.628ns (78.121%)) Logic Levels: 0 Clock Path Skew: -0.212ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) Source Clock Delay (SCD): -2.423ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.919 -2.423 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y74 FDCE (Prop_fdce_C_Q) 0.456 -1.967 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 1.628 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.601 17.366 clock uncertainty -0.197 17.169 SLICE_X29Y74 FDCE (Setup_fdce_C_D) -0.093 17.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 17.076 arrival time 0.338 ------------------------------------------------------------------- slack 17.415 Slack (MET) : 17.422ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.877ns (logic 1.344ns (71.587%) route 0.533ns (28.413%)) Logic Levels: 0 Clock Path Skew: -0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.176 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.533 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C clock pessimism -0.601 17.274 clock uncertainty -0.197 17.077 SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.297 16.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24] ------------------------------------------------------------------- required time 16.780 arrival time 0.642 ------------------------------------------------------------------- slack 17.422 Slack (MET) : 17.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.860ns (logic 1.343ns (72.194%) route 0.517ns (27.806%)) Logic Levels: 0 Clock Path Skew: -0.212ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) Source Clock Delay (SCD): -2.409ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.066 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O net (fo=1, routed) 0.517 -0.548 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C clock pessimism -0.601 17.380 clock uncertainty -0.197 17.183 SLICE_X17Y78 FDRE (Setup_fdre_C_D) -0.305 16.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] ------------------------------------------------------------------- required time 16.878 arrival time 0.548 ------------------------------------------------------------------- slack 17.426 Slack (MET) : 17.461ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.860ns (logic 1.344ns (72.269%) route 0.516ns (27.731%)) Logic Levels: 0 Clock Path Skew: -0.212ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) Source Clock Delay (SCD): -2.409ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.065 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O net (fo=1, routed) 0.516 -0.549 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C clock pessimism -0.601 17.380 clock uncertainty -0.197 17.183 SLICE_X17Y78 FDRE (Setup_fdre_C_D) -0.271 16.912 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36] ------------------------------------------------------------------- required time 16.912 arrival time 0.549 ------------------------------------------------------------------- slack 17.461 Slack (MET) : 17.463ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.069ns (logic 1.317ns (63.642%) route 0.752ns (36.358%)) Logic Levels: 0 Clock Path Skew: -0.204ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) Source Clock Delay (SCD): -2.521ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.204 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 0.752 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C clock pessimism -0.601 17.276 clock uncertainty -0.197 17.079 SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.067 17.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] ------------------------------------------------------------------- required time 17.012 arrival time 0.451 ------------------------------------------------------------------- slack 17.463 Slack (MET) : 17.464ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.079ns (logic 1.317ns (63.334%) route 0.762ns (36.666%)) Logic Levels: 0 Clock Path Skew: -0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 0.762 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C clock pessimism -0.601 17.276 clock uncertainty -0.197 17.079 SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.058 17.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] ------------------------------------------------------------------- required time 17.021 arrival time 0.443 ------------------------------------------------------------------- slack 17.464 Slack (MET) : 17.494ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.834ns (logic 1.336ns (72.831%) route 0.498ns (27.169%)) Logic Levels: 0 Clock Path Skew: -0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.022ns = ( 17.978 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.078 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O net (fo=1, routed) 0.498 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.806 17.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C clock pessimism -0.601 17.377 clock uncertainty -0.197 17.180 SLICE_X19Y76 FDRE (Setup_fdre_C_D) -0.265 16.915 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] ------------------------------------------------------------------- required time 16.915 arrival time 0.579 ------------------------------------------------------------------- slack 17.494 Slack (MET) : 17.513ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 2.042ns (logic 1.314ns (64.342%) route 0.728ns (35.658%)) Logic Levels: 0 Clock Path Skew: -0.204ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 0.728 -0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C clock pessimism -0.601 17.274 clock uncertainty -0.197 17.077 SLICE_X62Y81 FDRE (Setup_fdre_C_D) -0.045 17.032 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] ------------------------------------------------------------------- required time 17.032 arrival time 0.480 ------------------------------------------------------------------- slack 17.513 Slack (MET) : 17.526ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.999ns (logic 1.309ns (65.487%) route 0.690ns (34.513%)) Logic Levels: 0 Clock Path Skew: -0.212ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) Source Clock Delay (SCD): -2.409ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.100 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O net (fo=1, routed) 0.690 -0.410 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C clock pessimism -0.601 17.380 clock uncertainty -0.197 17.183 SLICE_X15Y78 FDRE (Setup_fdre_C_D) -0.067 17.116 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] ------------------------------------------------------------------- required time 17.116 arrival time 0.410 ------------------------------------------------------------------- slack 17.526 Slack (MET) : 17.534ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 1.826ns (logic 1.344ns (73.607%) route 0.482ns (26.393%)) Logic Levels: 0 Clock Path Skew: -0.209ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.130ns = ( 17.870 - 20.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.179 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 0.482 -0.697 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.698 17.870 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C clock pessimism -0.601 17.269 clock uncertainty -0.197 17.072 SLICE_X62Y76 FDRE (Setup_fdre_C_D) -0.235 16.837 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18] ------------------------------------------------------------------- required time 16.837 arrival time 0.697 ------------------------------------------------------------------- slack 17.534 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: cpu_clk To Clock: cpu_clk Setup : 0 Failing Endpoints, Worst Slack 25.793ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 25.793ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.498 27.806 clock uncertainty -0.074 27.732 SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 27.327 arrival time -1.534 ------------------------------------------------------------------- slack 25.793 Slack (MET) : 25.793ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.498 27.806 clock uncertainty -0.074 27.732 SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 27.327 arrival time -1.534 ------------------------------------------------------------------- slack 25.793 Slack (MET) : 25.793ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.498 27.806 clock uncertainty -0.074 27.732 SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 27.327 arrival time -1.534 ------------------------------------------------------------------- slack 25.793 Slack (MET) : 25.793ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.498 27.806 clock uncertainty -0.074 27.732 SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 27.327 arrival time -1.534 ------------------------------------------------------------------- slack 25.793 Slack (MET) : 25.793ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.498 27.806 clock uncertainty -0.074 27.732 SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 27.327 arrival time -1.534 ------------------------------------------------------------------- slack 25.793 Slack (MET) : 25.793ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.498 27.806 clock uncertainty -0.074 27.732 SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 27.327 arrival time -1.534 ------------------------------------------------------------------- slack 25.793 Slack (MET) : 25.837ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.498 27.806 clock uncertainty -0.074 27.732 SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.361 27.371 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 27.371 arrival time -1.534 ------------------------------------------------------------------- slack 25.837 Slack (MET) : 25.837ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.498 27.806 clock uncertainty -0.074 27.732 SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.361 27.371 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 27.371 arrival time -1.534 ------------------------------------------------------------------- slack 25.837 Slack (MET) : 25.879ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.498 27.806 clock uncertainty -0.074 27.732 SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.319 27.413 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 27.413 arrival time -1.534 ------------------------------------------------------------------- slack 25.879 Slack (MET) : 25.879ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.498 27.806 clock uncertainty -0.074 27.732 SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.319 27.413 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 27.413 arrival time -1.534 ------------------------------------------------------------------- slack 25.879 Slack (MET) : 25.879ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.498 27.806 clock uncertainty -0.074 27.732 SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.319 27.413 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 27.413 arrival time -1.534 ------------------------------------------------------------------- slack 25.879 Slack (MET) : 25.990ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.387ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.498 27.807 clock uncertainty -0.074 27.733 SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.361 27.372 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 27.372 arrival time -1.382 ------------------------------------------------------------------- slack 25.990 Slack (MET) : 25.990ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.387ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.498 27.807 clock uncertainty -0.074 27.733 SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.361 27.372 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 27.372 arrival time -1.382 ------------------------------------------------------------------- slack 25.990 Slack (MET) : 25.990ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.387ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.498 27.807 clock uncertainty -0.074 27.733 SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.361 27.372 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 27.372 arrival time -1.382 ------------------------------------------------------------------- slack 25.990 Slack (MET) : 25.995ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.384ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.498 27.810 clock uncertainty -0.074 27.736 SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 27.331 arrival time -1.336 ------------------------------------------------------------------- slack 25.995 Slack (MET) : 25.995ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.384ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.498 27.810 clock uncertainty -0.074 27.736 SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 27.331 arrival time -1.336 ------------------------------------------------------------------- slack 25.995 Slack (MET) : 25.995ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.384ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.498 27.810 clock uncertainty -0.074 27.736 SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 27.331 arrival time -1.336 ------------------------------------------------------------------- slack 25.995 Slack (MET) : 25.995ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.384ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.498 27.810 clock uncertainty -0.074 27.736 SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 27.331 arrival time -1.336 ------------------------------------------------------------------- slack 25.995 Slack (MET) : 25.995ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.384ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.498 27.810 clock uncertainty -0.074 27.736 SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 27.331 arrival time -1.336 ------------------------------------------------------------------- slack 25.995 Slack (MET) : 26.032ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.387ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.498 27.807 clock uncertainty -0.074 27.733 SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.319 27.414 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 27.414 arrival time -1.382 ------------------------------------------------------------------- slack 26.032 Slack (MET) : 26.032ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.387ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.498 27.807 clock uncertainty -0.074 27.733 SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.319 27.414 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 27.414 arrival time -1.382 ------------------------------------------------------------------- slack 26.032 Slack (MET) : 26.032ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.387ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.498 27.807 clock uncertainty -0.074 27.733 SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.319 27.414 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 27.414 arrival time -1.382 ------------------------------------------------------------------- slack 26.032 Slack (MET) : 26.072ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.804ns (logic 0.718ns (18.873%) route 3.086ns (81.127%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.455 1.401 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X4Y76 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/cpu_clk SLICE_X4Y76 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C clock pessimism -0.426 27.952 clock uncertainty -0.074 27.878 SLICE_X4Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 27.473 arrival time -1.401 ------------------------------------------------------------------- slack 26.072 Slack (MET) : 26.072ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.804ns (logic 0.718ns (18.873%) route 3.086ns (81.127%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.455 1.401 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X4Y76 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/cpu_clk SLICE_X4Y76 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C clock pessimism -0.426 27.952 clock uncertainty -0.074 27.878 SLICE_X4Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 27.473 arrival time -1.401 ------------------------------------------------------------------- slack 26.072 Slack (MET) : 26.072ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.804ns (logic 0.718ns (18.873%) route 3.086ns (81.127%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.455 1.401 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X4Y76 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/cpu_clk SLICE_X4Y76 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C clock pessimism -0.426 27.952 clock uncertainty -0.074 27.878 SLICE_X4Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 27.473 arrival time -1.401 ------------------------------------------------------------------- slack 26.072 Slack (MET) : 26.076ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.426 27.952 clock uncertainty -0.074 27.878 SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 27.473 arrival time -1.396 ------------------------------------------------------------------- slack 26.076 Slack (MET) : 26.076ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.426 27.952 clock uncertainty -0.074 27.878 SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 27.473 arrival time -1.396 ------------------------------------------------------------------- slack 26.076 Slack (MET) : 26.076ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.426 27.952 clock uncertainty -0.074 27.878 SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 27.473 arrival time -1.396 ------------------------------------------------------------------- slack 26.076 Slack (MET) : 26.076ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.426 27.952 clock uncertainty -0.074 27.878 SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 27.473 arrival time -1.396 ------------------------------------------------------------------- slack 26.076 Slack (MET) : 26.076ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.426 27.952 clock uncertainty -0.074 27.878 SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 27.473 arrival time -1.396 ------------------------------------------------------------------- slack 26.076 Slack (MET) : 26.076ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.426 27.952 clock uncertainty -0.074 27.878 SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 27.473 arrival time -1.396 ------------------------------------------------------------------- slack 26.076 Slack (MET) : 26.198ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.426 27.950 clock uncertainty -0.074 27.876 SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 27.471 arrival time -1.273 ------------------------------------------------------------------- slack 26.198 Slack (MET) : 26.198ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.426 27.950 clock uncertainty -0.074 27.876 SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 27.471 arrival time -1.273 ------------------------------------------------------------------- slack 26.198 Slack (MET) : 26.198ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.426 27.950 clock uncertainty -0.074 27.876 SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 27.471 arrival time -1.273 ------------------------------------------------------------------- slack 26.198 Slack (MET) : 26.198ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.426 27.950 clock uncertainty -0.074 27.876 SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 27.471 arrival time -1.273 ------------------------------------------------------------------- slack 26.198 Slack (MET) : 26.255ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.620ns (logic 0.718ns (19.836%) route 2.902ns (80.164%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.270 1.216 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.426 27.950 clock uncertainty -0.074 27.876 SLICE_X5Y75 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 27.471 arrival time -1.216 ------------------------------------------------------------------- slack 26.255 Slack (MET) : 26.255ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.620ns (logic 0.718ns (19.836%) route 2.902ns (80.164%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 2.270 1.216 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.426 27.950 clock uncertainty -0.074 27.876 SLICE_X5Y75 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 27.471 arrival time -1.216 ------------------------------------------------------------------- slack 26.255 Slack (MET) : 26.639ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.322ns (logic 0.718ns (21.614%) route 2.604ns (78.386%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.972 0.918 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X6Y74 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk SLICE_X6Y74 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C clock pessimism -0.426 27.950 clock uncertainty -0.074 27.876 SLICE_X6Y74 FDCE (Recov_fdce_C_CLR) -0.319 27.557 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 27.557 arrival time -0.918 ------------------------------------------------------------------- slack 26.639 Slack (MET) : 27.242ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.426 27.887 clock uncertainty -0.074 27.813 SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 27.408 arrival time -0.166 ------------------------------------------------------------------- slack 27.242 Slack (MET) : 27.242ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.426 27.887 clock uncertainty -0.074 27.813 SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 27.408 arrival time -0.166 ------------------------------------------------------------------- slack 27.242 Slack (MET) : 27.242ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.426 27.887 clock uncertainty -0.074 27.813 SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 27.408 arrival time -0.166 ------------------------------------------------------------------- slack 27.242 Slack (MET) : 27.242ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.426 27.887 clock uncertainty -0.074 27.813 SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 27.408 arrival time -0.166 ------------------------------------------------------------------- slack 27.242 Slack (MET) : 27.242ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.426 27.887 clock uncertainty -0.074 27.813 SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 27.408 arrival time -0.166 ------------------------------------------------------------------- slack 27.242 Slack (MET) : 27.242ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.426 27.887 clock uncertainty -0.074 27.813 SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 27.408 arrival time -0.166 ------------------------------------------------------------------- slack 27.242 Slack (MET) : 27.242ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.220 0.166 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X19Y59 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y59 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.426 27.887 clock uncertainty -0.074 27.813 SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 27.408 arrival time -0.166 ------------------------------------------------------------------- slack 27.242 Slack (MET) : 27.248ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.426 27.888 clock uncertainty -0.074 27.814 SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 27.409 arrival time -0.161 ------------------------------------------------------------------- slack 27.248 Slack (MET) : 27.248ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C clock pessimism -0.426 27.888 clock uncertainty -0.074 27.814 SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 27.409 arrival time -0.161 ------------------------------------------------------------------- slack 27.248 Slack (MET) : 27.248ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.426 27.888 clock uncertainty -0.074 27.814 SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 27.409 arrival time -0.161 ------------------------------------------------------------------- slack 27.248 Slack (MET) : 27.248ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) Source Clock Delay (SCD): -2.404ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.426 27.888 clock uncertainty -0.074 27.814 SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 27.409 arrival time -0.161 ------------------------------------------------------------------- slack 27.248 Slack (MET) : 27.338ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.252ns (logic 0.580ns (25.756%) route 1.672ns (74.244%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.298ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.928ns = ( 28.394 - 30.323 ) Source Clock Delay (SCD): -2.129ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.014 0.123 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.900 28.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.498 27.896 clock uncertainty -0.074 27.822 SLICE_X6Y50 FDCE (Recov_fdce_C_CLR) -0.361 27.461 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 27.461 arrival time -0.123 ------------------------------------------------------------------- slack 27.338 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: mlkem_clk_clk_pll To Clock: mlkem_clk_clk_pll Setup : 0 Failing Endpoints, Worst Slack 23.497ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 23.497ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 15.612ns (logic 0.609ns (3.901%) route 15.003ns (96.099%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.206ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.188ns = ( 37.812 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.752 13.124 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X41Y101 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.640 37.812 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X41Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324]/C clock pessimism -0.507 37.305 clock uncertainty -0.077 37.229 SLICE_X41Y101 FDCE (Recov_fdce_C_CLR) -0.608 36.621 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324] ------------------------------------------------------------------- required time 36.621 arrival time -13.124 ------------------------------------------------------------------- slack 23.497 Slack (MET) : 23.497ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 15.612ns (logic 0.609ns (3.901%) route 15.003ns (96.099%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.206ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.188ns = ( 37.812 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.752 13.124 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X41Y101 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.640 37.812 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X41Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931]/C clock pessimism -0.507 37.305 clock uncertainty -0.077 37.229 SLICE_X41Y101 FDCE (Recov_fdce_C_CLR) -0.608 36.621 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931] ------------------------------------------------------------------- required time 36.621 arrival time -13.124 ------------------------------------------------------------------- slack 23.497 Slack (MET) : 23.954ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 15.155ns (logic 0.609ns (4.018%) route 14.546ns (95.982%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.206ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.188ns = ( 37.812 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.295 12.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 SLICE_X38Y100 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.640 37.812 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X38Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293]/C clock pessimism -0.507 37.305 clock uncertainty -0.077 37.229 SLICE_X38Y100 FDCE (Recov_fdce_C_CLR) -0.608 36.621 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293] ------------------------------------------------------------------- required time 36.621 arrival time -12.667 ------------------------------------------------------------------- slack 23.954 Slack (MET) : 24.240ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365]/C clock pessimism -0.498 37.480 clock uncertainty -0.077 37.404 SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365] ------------------------------------------------------------------- required time 36.796 arrival time -12.556 ------------------------------------------------------------------- slack 24.240 Slack (MET) : 24.240ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461]/C clock pessimism -0.498 37.480 clock uncertainty -0.077 37.404 SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461] ------------------------------------------------------------------- required time 36.796 arrival time -12.556 ------------------------------------------------------------------- slack 24.240 Slack (MET) : 24.240ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542]/C clock pessimism -0.498 37.480 clock uncertainty -0.077 37.404 SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542] ------------------------------------------------------------------- required time 36.796 arrival time -12.556 ------------------------------------------------------------------- slack 24.240 Slack (MET) : 24.240ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732]/C clock pessimism -0.498 37.480 clock uncertainty -0.077 37.404 SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732] ------------------------------------------------------------------- required time 36.796 arrival time -12.556 ------------------------------------------------------------------- slack 24.240 Slack (MET) : 24.240ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805]/C clock pessimism -0.498 37.480 clock uncertainty -0.077 37.404 SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805] ------------------------------------------------------------------- required time 36.796 arrival time -12.556 ------------------------------------------------------------------- slack 24.240 Slack (MET) : 24.240ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893]/C clock pessimism -0.498 37.480 clock uncertainty -0.077 37.404 SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893] ------------------------------------------------------------------- required time 36.796 arrival time -12.556 ------------------------------------------------------------------- slack 24.240 Slack (MET) : 24.267ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.931ns (logic 0.609ns (4.079%) route 14.322ns (95.921%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.071 12.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 SLICE_X45Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X45Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X45Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729] ------------------------------------------------------------------- required time 36.709 arrival time -12.442 ------------------------------------------------------------------- slack 24.267 Slack (MET) : 24.267ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.931ns (logic 0.609ns (4.079%) route 14.322ns (95.921%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.071 12.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 SLICE_X45Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X45Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X45Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730] ------------------------------------------------------------------- required time 36.709 arrival time -12.442 ------------------------------------------------------------------- slack 24.267 Slack (MET) : 24.272ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 SLICE_X49Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X49Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X49Y97 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553] ------------------------------------------------------------------- required time 36.709 arrival time -12.437 ------------------------------------------------------------------- slack 24.272 Slack (MET) : 24.272ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 SLICE_X49Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X49Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X49Y97 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598] ------------------------------------------------------------------- required time 36.709 arrival time -12.437 ------------------------------------------------------------------- slack 24.272 Slack (MET) : 24.284ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 SLICE_X36Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X36Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269]/C clock pessimism -0.498 37.480 clock uncertainty -0.077 37.404 SLICE_X36Y99 FDCE (Recov_fdce_C_CLR) -0.564 36.840 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269] ------------------------------------------------------------------- required time 36.840 arrival time -12.556 ------------------------------------------------------------------- slack 24.284 Slack (MET) : 24.316ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.564 36.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652] ------------------------------------------------------------------- required time 36.753 arrival time -12.437 ------------------------------------------------------------------- slack 24.316 Slack (MET) : 24.316ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.564 36.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715] ------------------------------------------------------------------- required time 36.753 arrival time -12.437 ------------------------------------------------------------------- slack 24.316 Slack (MET) : 24.316ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.564 36.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718] ------------------------------------------------------------------- required time 36.753 arrival time -12.437 ------------------------------------------------------------------- slack 24.316 Slack (MET) : 24.326ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 SLICE_X36Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X36Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268]/C clock pessimism -0.498 37.480 clock uncertainty -0.077 37.404 SLICE_X36Y99 FDCE (Recov_fdce_C_CLR) -0.522 36.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268] ------------------------------------------------------------------- required time 36.882 arrival time -12.556 ------------------------------------------------------------------- slack 24.326 Slack (MET) : 24.341ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372] ------------------------------------------------------------------- required time 36.709 arrival time -12.367 ------------------------------------------------------------------- slack 24.341 Slack (MET) : 24.341ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373] ------------------------------------------------------------------- required time 36.709 arrival time -12.367 ------------------------------------------------------------------- slack 24.341 Slack (MET) : 24.341ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396] ------------------------------------------------------------------- required time 36.709 arrival time -12.367 ------------------------------------------------------------------- slack 24.341 Slack (MET) : 24.341ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864] ------------------------------------------------------------------- required time 36.709 arrival time -12.367 ------------------------------------------------------------------- slack 24.341 Slack (MET) : 24.341ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886] ------------------------------------------------------------------- required time 36.709 arrival time -12.367 ------------------------------------------------------------------- slack 24.341 Slack (MET) : 24.341ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887] ------------------------------------------------------------------- required time 36.709 arrival time -12.367 ------------------------------------------------------------------- slack 24.341 Slack (MET) : 24.358ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.522 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301] ------------------------------------------------------------------- required time 36.795 arrival time -12.437 ------------------------------------------------------------------- slack 24.358 Slack (MET) : 24.358ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.522 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525] ------------------------------------------------------------------- required time 36.795 arrival time -12.437 ------------------------------------------------------------------- slack 24.358 Slack (MET) : 24.358ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557]/C clock pessimism -0.498 37.393 clock uncertainty -0.077 37.317 SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.522 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557] ------------------------------------------------------------------- required time 36.795 arrival time -12.437 ------------------------------------------------------------------- slack 24.358 Slack (MET) : 24.441ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 SLICE_X41Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X41Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650]/C clock pessimism -0.498 37.477 clock uncertainty -0.077 37.401 SLICE_X41Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650] ------------------------------------------------------------------- required time 36.793 arrival time -12.352 ------------------------------------------------------------------- slack 24.441 Slack (MET) : 24.441ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 SLICE_X41Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X41Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651]/C clock pessimism -0.498 37.477 clock uncertainty -0.077 37.401 SLICE_X41Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651] ------------------------------------------------------------------- required time 36.793 arrival time -12.352 ------------------------------------------------------------------- slack 24.441 Slack (MET) : 24.527ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 SLICE_X40Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X40Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181]/C clock pessimism -0.498 37.477 clock uncertainty -0.077 37.401 SLICE_X40Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181] ------------------------------------------------------------------- required time 36.879 arrival time -12.352 ------------------------------------------------------------------- slack 24.527 Slack (MET) : 24.527ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 SLICE_X40Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X40Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196]/C clock pessimism -0.498 37.477 clock uncertainty -0.077 37.401 SLICE_X40Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196] ------------------------------------------------------------------- required time 36.879 arrival time -12.352 ------------------------------------------------------------------- slack 24.527 Slack (MET) : 24.527ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 SLICE_X40Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X40Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197]/C clock pessimism -0.498 37.477 clock uncertainty -0.077 37.401 SLICE_X40Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197] ------------------------------------------------------------------- required time 36.879 arrival time -12.352 ------------------------------------------------------------------- slack 24.527 Slack (MET) : 24.542ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176]/C clock pessimism -0.498 37.392 clock uncertainty -0.077 37.316 SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176] ------------------------------------------------------------------- required time 36.708 arrival time -12.166 ------------------------------------------------------------------- slack 24.542 Slack (MET) : 24.542ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517]/C clock pessimism -0.498 37.392 clock uncertainty -0.077 37.316 SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517] ------------------------------------------------------------------- required time 36.708 arrival time -12.166 ------------------------------------------------------------------- slack 24.542 Slack (MET) : 24.542ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570]/C clock pessimism -0.498 37.392 clock uncertainty -0.077 37.316 SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570] ------------------------------------------------------------------- required time 36.708 arrival time -12.166 ------------------------------------------------------------------- slack 24.542 Slack (MET) : 24.542ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730]/C clock pessimism -0.498 37.392 clock uncertainty -0.077 37.316 SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730] ------------------------------------------------------------------- required time 36.708 arrival time -12.166 ------------------------------------------------------------------- slack 24.542 Slack (MET) : 24.578ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.705ns (logic 0.609ns (4.142%) route 14.096ns (95.858%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.845 12.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X38Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X38Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540]/C clock pessimism -0.498 37.478 clock uncertainty -0.077 37.402 SLICE_X38Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540] ------------------------------------------------------------------- required time 36.794 arrival time -12.216 ------------------------------------------------------------------- slack 24.578 Slack (MET) : 24.578ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.705ns (logic 0.609ns (4.142%) route 14.096ns (95.858%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.845 12.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X38Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X38Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733]/C clock pessimism -0.498 37.478 clock uncertainty -0.077 37.402 SLICE_X38Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733] ------------------------------------------------------------------- required time 36.794 arrival time -12.216 ------------------------------------------------------------------- slack 24.578 Slack (MET) : 24.582ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.700ns (logic 0.609ns (4.143%) route 14.091ns (95.857%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.840 12.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X39Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X39Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053]/C clock pessimism -0.498 37.478 clock uncertainty -0.077 37.402 SLICE_X39Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053] ------------------------------------------------------------------- required time 36.794 arrival time -12.212 ------------------------------------------------------------------- slack 24.582 Slack (MET) : 24.582ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.700ns (logic 0.609ns (4.143%) route 14.091ns (95.857%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.840 12.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 SLICE_X39Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk SLICE_X39Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188]/C clock pessimism -0.498 37.478 clock uncertainty -0.077 37.402 SLICE_X39Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188] ------------------------------------------------------------------- required time 36.794 arrival time -12.212 ------------------------------------------------------------------- slack 24.582 Slack (MET) : 24.628ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 SLICE_X44Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X44Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517]/C clock pessimism -0.498 37.392 clock uncertainty -0.077 37.316 SLICE_X44Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517] ------------------------------------------------------------------- required time 36.794 arrival time -12.166 ------------------------------------------------------------------- slack 24.628 Slack (MET) : 24.628ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 SLICE_X44Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X44Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532]/C clock pessimism -0.498 37.392 clock uncertainty -0.077 37.316 SLICE_X44Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532] ------------------------------------------------------------------- required time 36.794 arrival time -12.166 ------------------------------------------------------------------- slack 24.628 Slack (MET) : 24.628ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 SLICE_X44Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X44Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533]/C clock pessimism -0.498 37.392 clock uncertainty -0.077 37.316 SLICE_X44Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533] ------------------------------------------------------------------- required time 36.794 arrival time -12.166 ------------------------------------------------------------------- slack 24.628 Slack (MET) : 24.654ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.628ns (logic 0.609ns (4.163%) route 14.019ns (95.837%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.768 12.139 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 SLICE_X38Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X38Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373]/C clock pessimism -0.498 37.477 clock uncertainty -0.077 37.401 SLICE_X38Y94 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373] ------------------------------------------------------------------- required time 36.793 arrival time -12.139 ------------------------------------------------------------------- slack 24.654 Slack (MET) : 24.658ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.624ns (logic 0.609ns (4.165%) route 14.015ns (95.835%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.764 12.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 SLICE_X39Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X39Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156]/C clock pessimism -0.498 37.477 clock uncertainty -0.077 37.401 SLICE_X39Y94 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156] ------------------------------------------------------------------- required time 36.793 arrival time -12.135 ------------------------------------------------------------------- slack 24.658 Slack (MET) : 24.680ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.559ns (logic 0.609ns (4.183%) route 13.950ns (95.817%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.120ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.699 12.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 SLICE_X44Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X44Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533]/C clock pessimism -0.498 37.391 clock uncertainty -0.077 37.315 SLICE_X44Y92 FDCE (Recov_fdce_C_CLR) -0.564 36.751 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533] ------------------------------------------------------------------- required time 36.751 arrival time -12.071 ------------------------------------------------------------------- slack 24.680 Slack (MET) : 24.722ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.559ns (logic 0.609ns (4.183%) route 13.950ns (95.817%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.120ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.699 12.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 SLICE_X44Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X44Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532]/C clock pessimism -0.498 37.391 clock uncertainty -0.077 37.315 SLICE_X44Y92 FDCE (Recov_fdce_C_CLR) -0.522 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532] ------------------------------------------------------------------- required time 36.793 arrival time -12.071 ------------------------------------------------------------------- slack 24.722 Slack (MET) : 25.212ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.068ns (logic 0.609ns (4.329%) route 13.459ns (95.671%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.025ns = ( 37.975 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.208 11.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 SLICE_X38Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.803 37.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X38Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204]/C clock pessimism -0.498 37.476 clock uncertainty -0.077 37.400 SLICE_X38Y92 FDCE (Recov_fdce_C_CLR) -0.608 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204] ------------------------------------------------------------------- required time 36.792 arrival time -11.580 ------------------------------------------------------------------- slack 25.212 Slack (MET) : 25.212ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.068ns (logic 0.609ns (4.329%) route 13.459ns (95.671%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.025ns = ( 37.975 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.208 11.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 SLICE_X38Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.803 37.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk SLICE_X38Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205]/C clock pessimism -0.498 37.476 clock uncertainty -0.077 37.400 SLICE_X38Y92 FDCE (Recov_fdce_C_CLR) -0.608 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205] ------------------------------------------------------------------- required time 36.792 arrival time -11.580 ------------------------------------------------------------------- slack 25.212 Slack (MET) : 25.217ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 14.064ns (logic 0.609ns (4.330%) route 13.455ns (95.670%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.025ns = ( 37.975 - 40.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24598, routed) 12.204 11.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 SLICE_X39Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.803 37.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X39Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204]/C clock pessimism -0.498 37.476 clock uncertainty -0.077 37.400 SLICE_X39Y92 FDCE (Recov_fdce_C_CLR) -0.608 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204] ------------------------------------------------------------------- required time 36.792 arrival time -11.575 ------------------------------------------------------------------- slack 25.217 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk To Clock: mlkem_clk_clk_pll Setup : 0 Failing Endpoints, Worst Slack 9.156ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 9.156ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 9.823ns (logic 0.606ns (6.169%) route 9.217ns (93.831%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.101ns = ( 37.899 - 40.000 ) Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 5.710 27.336 pll_clk.u_rst_mlkem/p_0_in SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.727 37.899 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C clock pessimism -0.601 37.298 clock uncertainty -0.197 37.101 SLICE_X118Y67 FDCE (Recov_fdce_C_CLR) -0.609 36.492 pll_clk.u_rst_mlkem/delay_reg[0] ------------------------------------------------------------------- required time 36.492 arrival time -27.336 ------------------------------------------------------------------- slack 9.156 Slack (MET) : 9.156ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 9.823ns (logic 0.606ns (6.169%) route 9.217ns (93.831%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.101ns = ( 37.899 - 40.000 ) Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 5.710 27.336 pll_clk.u_rst_mlkem/p_0_in SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.727 37.899 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C clock pessimism -0.601 37.298 clock uncertainty -0.197 37.101 SLICE_X118Y67 FDCE (Recov_fdce_C_CLR) -0.609 36.492 pll_clk.u_rst_mlkem/delay_reg[1] ------------------------------------------------------------------- required time 36.492 arrival time -27.336 ------------------------------------------------------------------- slack 9.156 Slack (MET) : 11.865ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 7.189ns (logic 0.606ns (8.429%) route 6.583ns (91.571%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.026ns = ( 37.974 - 40.000 ) Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 3.076 24.702 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.802 37.974 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C clock pessimism -0.601 37.373 clock uncertainty -0.197 37.176 SLICE_X25Y79 FDCE (Recov_fdce_C_CLR) -0.609 36.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg ------------------------------------------------------------------- required time 36.567 arrival time -24.702 ------------------------------------------------------------------- slack 11.865 Slack (MET) : 11.865ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 7.189ns (logic 0.606ns (8.429%) route 6.583ns (91.571%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.026ns = ( 37.974 - 40.000 ) Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 3.076 24.702 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r K21 0.000 40.000 r clk (IN) net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.802 37.974 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C clock pessimism -0.601 37.373 clock uncertainty -0.197 37.176 SLICE_X25Y79 FDCE (Recov_fdce_C_CLR) -0.609 36.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg ------------------------------------------------------------------- required time 36.567 arrival time -24.702 ------------------------------------------------------------------- slack 11.865 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: mlkem_clk_clk_pll To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 11.249ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 11.249ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 8.025ns (logic 0.580ns (7.227%) route 7.445ns (92.773%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.874 -1.158 pll_clk.u_rst_mlkem/Q[0] SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.124 -1.034 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1069, routed) 6.571 5.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C clock pessimism -0.601 17.388 clock uncertainty -0.197 17.191 SLICE_X13Y87 FDCE (Recov_fdce_C_CLR) -0.405 16.786 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg ------------------------------------------------------------------- required time 16.786 arrival time -5.537 ------------------------------------------------------------------- slack 11.249 Slack (MET) : 11.249ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 8.025ns (logic 0.580ns (7.227%) route 7.445ns (92.773%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) Source Clock Delay (SCD): -2.489ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.874 -1.158 pll_clk.u_rst_mlkem/Q[0] SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.124 -1.034 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1069, routed) 6.571 5.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C clock pessimism -0.601 17.388 clock uncertainty -0.197 17.191 SLICE_X13Y87 FDCE (Recov_fdce_C_CLR) -0.405 16.786 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg ------------------------------------------------------------------- required time 16.786 arrival time -5.537 ------------------------------------------------------------------- slack 11.249 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 4.581ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.581ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.588ns (logic 0.606ns (4.154%) route 13.982ns (95.846%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.132ns = ( 17.868 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 10.475 12.101 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X85Y50 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.696 17.868 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X85Y50 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/C clock pessimism -0.507 17.361 clock uncertainty -0.071 17.290 SLICE_X85Y50 FDCE (Recov_fdce_C_CLR) -0.609 16.681 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2] ------------------------------------------------------------------- required time 16.681 arrival time -12.101 ------------------------------------------------------------------- slack 4.581 Slack (MET) : 5.171ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.003ns (logic 0.606ns (4.328%) route 13.397ns (95.672%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 9.890 11.515 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X77Y52 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.701 17.873 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X77Y52 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/C clock pessimism -0.507 17.366 clock uncertainty -0.071 17.295 SLICE_X77Y52 FDCE (Recov_fdce_C_CLR) -0.609 16.686 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0] ------------------------------------------------------------------- required time 16.686 arrival time -11.515 ------------------------------------------------------------------- slack 5.171 Slack (MET) : 5.624ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.646ns (logic 0.606ns (4.441%) route 13.040ns (95.559%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 9.533 11.158 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X90Y57 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.711 17.883 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X90Y57 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/C clock pessimism -0.507 17.376 clock uncertainty -0.071 17.305 SLICE_X90Y57 FDCE (Recov_fdce_C_CLR) -0.523 16.782 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2] ------------------------------------------------------------------- required time 16.782 arrival time -11.158 ------------------------------------------------------------------- slack 5.624 Slack (MET) : 6.450ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.989 18.160 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk SLICE_X29Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/C clock pessimism -0.507 17.654 clock uncertainty -0.071 17.583 SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2] ------------------------------------------------------------------- required time 16.974 arrival time -10.524 ------------------------------------------------------------------- slack 6.450 Slack (MET) : 6.450ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.989 18.160 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk SLICE_X29Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/C clock pessimism -0.507 17.654 clock uncertainty -0.071 17.583 SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3] ------------------------------------------------------------------- required time 16.974 arrival time -10.524 ------------------------------------------------------------------- slack 6.450 Slack (MET) : 6.450ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.989 18.160 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk SLICE_X29Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/C clock pessimism -0.507 17.654 clock uncertainty -0.071 17.583 SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4] ------------------------------------------------------------------- required time 16.974 arrival time -10.524 ------------------------------------------------------------------- slack 6.450 Slack (MET) : 6.650ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X50Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12] ------------------------------------------------------------------- required time 16.697 arrival time -10.047 ------------------------------------------------------------------- slack 6.650 Slack (MET) : 6.650ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X50Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2] ------------------------------------------------------------------- required time 16.697 arrival time -10.047 ------------------------------------------------------------------- slack 6.650 Slack (MET) : 6.654ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12] ------------------------------------------------------------------- required time 16.697 arrival time -10.043 ------------------------------------------------------------------- slack 6.654 Slack (MET) : 6.654ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13] ------------------------------------------------------------------- required time 16.697 arrival time -10.043 ------------------------------------------------------------------- slack 6.654 Slack (MET) : 6.654ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14] ------------------------------------------------------------------- required time 16.697 arrival time -10.043 ------------------------------------------------------------------- slack 6.654 Slack (MET) : 6.654ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15] ------------------------------------------------------------------- required time 16.697 arrival time -10.043 ------------------------------------------------------------------- slack 6.654 Slack (MET) : 6.814ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11] ------------------------------------------------------------------- required time 16.698 arrival time -9.884 ------------------------------------------------------------------- slack 6.814 Slack (MET) : 6.814ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12] ------------------------------------------------------------------- required time 16.698 arrival time -9.884 ------------------------------------------------------------------- slack 6.814 Slack (MET) : 6.814ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19] ------------------------------------------------------------------- required time 16.698 arrival time -9.884 ------------------------------------------------------------------- slack 6.814 Slack (MET) : 6.814ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1] ------------------------------------------------------------------- required time 16.698 arrival time -9.884 ------------------------------------------------------------------- slack 6.814 Slack (MET) : 6.881ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk SLICE_X19Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/C clock pessimism -0.507 17.663 clock uncertainty -0.071 17.592 SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5] ------------------------------------------------------------------- required time 16.983 arrival time -10.102 ------------------------------------------------------------------- slack 6.881 Slack (MET) : 6.881ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk SLICE_X19Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/C clock pessimism -0.507 17.663 clock uncertainty -0.071 17.592 SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg ------------------------------------------------------------------- required time 16.983 arrival time -10.102 ------------------------------------------------------------------- slack 6.881 Slack (MET) : 6.947ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4] ------------------------------------------------------------------- required time 16.698 arrival time -9.751 ------------------------------------------------------------------- slack 6.947 Slack (MET) : 6.947ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5] ------------------------------------------------------------------- required time 16.698 arrival time -9.751 ------------------------------------------------------------------- slack 6.947 Slack (MET) : 6.947ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6] ------------------------------------------------------------------- required time 16.698 arrival time -9.751 ------------------------------------------------------------------- slack 6.947 Slack (MET) : 6.947ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7] ------------------------------------------------------------------- required time 16.698 arrival time -9.751 ------------------------------------------------------------------- slack 6.947 Slack (MET) : 6.955ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14] ------------------------------------------------------------------- required time 16.698 arrival time -9.743 ------------------------------------------------------------------- slack 6.955 Slack (MET) : 6.955ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15] ------------------------------------------------------------------- required time 16.698 arrival time -9.743 ------------------------------------------------------------------- slack 6.955 Slack (MET) : 6.955ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5] ------------------------------------------------------------------- required time 16.698 arrival time -9.743 ------------------------------------------------------------------- slack 6.955 Slack (MET) : 6.955ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6] ------------------------------------------------------------------- required time 16.698 arrival time -9.743 ------------------------------------------------------------------- slack 6.955 Slack (MET) : 6.955ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7] ------------------------------------------------------------------- required time 16.698 arrival time -9.743 ------------------------------------------------------------------- slack 6.955 Slack (MET) : 6.955ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8] ------------------------------------------------------------------- required time 16.698 arrival time -9.743 ------------------------------------------------------------------- slack 6.955 Slack (MET) : 6.967ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk SLICE_X18Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/C clock pessimism -0.507 17.663 clock uncertainty -0.071 17.592 SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7] ------------------------------------------------------------------- required time 17.069 arrival time -10.102 ------------------------------------------------------------------- slack 6.967 Slack (MET) : 6.967ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk SLICE_X18Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/C clock pessimism -0.507 17.663 clock uncertainty -0.071 17.592 SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8] ------------------------------------------------------------------- required time 17.069 arrival time -10.102 ------------------------------------------------------------------- slack 6.967 Slack (MET) : 6.967ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk SLICE_X18Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/C clock pessimism -0.507 17.663 clock uncertainty -0.071 17.592 SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9] ------------------------------------------------------------------- required time 17.069 arrival time -10.102 ------------------------------------------------------------------- slack 6.967 Slack (MET) : 6.996ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0] ------------------------------------------------------------------- required time 16.697 arrival time -9.702 ------------------------------------------------------------------- slack 6.996 Slack (MET) : 6.996ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10] ------------------------------------------------------------------- required time 16.697 arrival time -9.702 ------------------------------------------------------------------- slack 6.996 Slack (MET) : 6.996ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3] ------------------------------------------------------------------- required time 16.697 arrival time -9.702 ------------------------------------------------------------------- slack 6.996 Slack (MET) : 6.996ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4] ------------------------------------------------------------------- required time 16.697 arrival time -9.702 ------------------------------------------------------------------- slack 6.996 Slack (MET) : 6.996ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9] ------------------------------------------------------------------- required time 16.697 arrival time -9.702 ------------------------------------------------------------------- slack 6.996 Slack (MET) : 7.098ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10] ------------------------------------------------------------------- required time 16.698 arrival time -9.601 ------------------------------------------------------------------- slack 7.098 Slack (MET) : 7.098ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11] ------------------------------------------------------------------- required time 16.698 arrival time -9.601 ------------------------------------------------------------------- slack 7.098 Slack (MET) : 7.098ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8] ------------------------------------------------------------------- required time 16.698 arrival time -9.601 ------------------------------------------------------------------- slack 7.098 Slack (MET) : 7.098ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.134ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/C clock pessimism -0.507 17.378 clock uncertainty -0.071 17.307 SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9] ------------------------------------------------------------------- required time 16.698 arrival time -9.601 ------------------------------------------------------------------- slack 7.098 Slack (MET) : 7.115ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13] ------------------------------------------------------------------- required time 16.697 arrival time -9.583 ------------------------------------------------------------------- slack 7.115 Slack (MET) : 7.115ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16] ------------------------------------------------------------------- required time 16.697 arrival time -9.583 ------------------------------------------------------------------- slack 7.115 Slack (MET) : 7.115ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21] ------------------------------------------------------------------- required time 16.697 arrival time -9.583 ------------------------------------------------------------------- slack 7.115 Slack (MET) : 7.115ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22] ------------------------------------------------------------------- required time 16.697 arrival time -9.583 ------------------------------------------------------------------- slack 7.115 Slack (MET) : 7.115ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/C clock pessimism -0.507 17.377 clock uncertainty -0.071 17.306 SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23] ------------------------------------------------------------------- required time 16.697 arrival time -9.583 ------------------------------------------------------------------- slack 7.115 Slack (MET) : 7.136ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.711 17.883 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X55Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/C clock pessimism -0.507 17.376 clock uncertainty -0.071 17.305 SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17] ------------------------------------------------------------------- required time 16.696 arrival time -9.561 ------------------------------------------------------------------- slack 7.136 Slack (MET) : 7.136ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.711 17.883 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X55Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/C clock pessimism -0.507 17.376 clock uncertainty -0.071 17.305 SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18] ------------------------------------------------------------------- required time 16.696 arrival time -9.561 ------------------------------------------------------------------- slack 7.136 Slack (MET) : 7.143ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.414ns (logic 0.606ns (4.882%) route 11.808ns (95.118%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 8.301 9.926 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in SLICE_X18Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk SLICE_X18Y1 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/C clock pessimism -0.507 17.663 clock uncertainty -0.071 17.592 SLICE_X18Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6] ------------------------------------------------------------------- required time 17.069 arrival time -9.926 ------------------------------------------------------------------- slack 7.143 Slack (MET) : 7.222ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.714 17.886 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y62 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/C clock pessimism -0.507 17.379 clock uncertainty -0.071 17.308 SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0] ------------------------------------------------------------------- required time 16.699 arrival time -9.478 ------------------------------------------------------------------- slack 7.222 Slack (MET) : 7.222ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.714 17.886 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk SLICE_X51Y62 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/C clock pessimism -0.507 17.379 clock uncertainty -0.071 17.308 SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1] ------------------------------------------------------------------- required time 16.699 arrival time -9.478 ------------------------------------------------------------------- slack 7.222 -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: cpu_clk Max Delay 59 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 9.445ns (logic 0.606ns (6.416%) route 8.839ns (93.584%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.470ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 5.332 6.958 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 9.445ns (logic 0.606ns (6.416%) route 8.839ns (93.584%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.470ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 5.332 6.958 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_cpu/delay_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 9.183ns (logic 0.606ns (6.599%) route 8.577ns (93.401%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.738ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.750ns Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 5.070 6.696 pll_clk.u_rst_cpu/p_0_in_0 SLICE_X0Y48 FDCE f pll_clk.u_rst_cpu/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.079 -1.750 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[0]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_cpu/delay_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 9.183ns (logic 0.606ns (6.599%) route 8.577ns (93.401%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.738ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.750ns Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4130, routed) 5.070 6.696 pll_clk.u_rst_cpu/p_0_in_0 SLICE_X0Y48 FDCE f pll_clk.u_rst_cpu/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.079 -1.750 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.254ns (logic 0.419ns (9.850%) route 3.835ns (90.150%)) Logic Levels: 0 Clock Path Skew: 0.544ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.939ns Source Clock Delay (SCD): -2.483ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.859 -2.483 u_fft_mlkem_axi_slave/sys_clk SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.419 -2.064 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/Q net (fo=1, routed) 3.835 1.771 u_cpu/u_csr/interrupt[3] SLICE_X50Y37 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.890 -1.939 u_cpu/u_csr/cpu_clk SLICE_X50Y37 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.608ns (logic 0.595ns (37.010%) route 1.013ns (62.990%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.498ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.243 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 1.013 1.256 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.565ns (logic 0.612ns (39.107%) route 0.953ns (60.893%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.262 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.953 1.215 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] SLICE_X15Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.566ns (logic 0.612ns (39.088%) route 0.954ns (60.912%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.498ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.260 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 0.954 1.214 u_Axi_CDC/rFifo/_zz_ram_port10__2[18] SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.491ns (logic 0.482ns (32.335%) route 1.009ns (67.665%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.498ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 1.009 1.138 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.465ns (logic 0.612ns (41.773%) route 0.853ns (58.227%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.498ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.260 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.853 1.113 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.455ns (logic 0.612ns (42.062%) route 0.843ns (57.938%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.262 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.843 1.105 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.417ns (logic 0.480ns (33.882%) route 0.937ns (66.118%)) Logic Levels: 0 Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.498ns Source Clock Delay (SCD): -0.353ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.127 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 0.937 1.063 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.406ns (logic 0.595ns (42.317%) route 0.811ns (57.683%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.245 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.811 1.056 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.401ns (logic 0.491ns (35.055%) route 0.910ns (64.945%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.141 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.910 1.050 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.394ns (logic 0.480ns (34.421%) route 0.914ns (65.579%)) Logic Levels: 0 Clock Path Skew: -0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.498ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 0.914 1.044 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.361ns (logic 0.480ns (35.268%) route 0.881ns (64.732%)) Logic Levels: 0 Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.497ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.128 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 0.881 1.009 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.354ns (logic 0.485ns (35.824%) route 0.869ns (64.176%)) Logic Levels: 0 Clock Path Skew: -0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.498ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.135 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.869 1.004 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.323ns (logic 0.612ns (46.260%) route 0.711ns (53.740%)) Logic Levels: 0 Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.353ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.259 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 0.711 0.970 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.317ns (logic 0.595ns (45.169%) route 0.722ns (54.831%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.245 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.722 0.967 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.310ns (logic 0.595ns (45.409%) route 0.715ns (54.591%)) Logic Levels: 0 Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.243 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.715 0.958 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.304ns (logic 0.491ns (37.657%) route 0.813ns (62.343%)) Logic Levels: 0 Clock Path Skew: -0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.498ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.141 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 0.813 0.954 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.294ns (logic 0.612ns (47.295%) route 0.682ns (52.705%)) Logic Levels: 0 Clock Path Skew: -0.213ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.353ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.259 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.682 0.941 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.696 -0.566 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.256ns (logic 0.482ns (38.384%) route 0.774ns (61.616%)) Logic Levels: 0 Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.353ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.129 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 0.774 0.903 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.248ns (logic 0.595ns (47.682%) route 0.653ns (52.318%)) Logic Levels: 0 Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.353ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.242 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.653 0.895 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.241ns (logic 0.491ns (39.556%) route 0.750ns (60.444%)) Logic Levels: 0 Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.139 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.750 0.889 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.241ns (logic 0.485ns (39.089%) route 0.756ns (60.911%)) Logic Levels: 0 Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.133 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.756 0.889 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.233ns (logic 0.482ns (39.088%) route 0.751ns (60.912%)) Logic Levels: 0 Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 0.751 0.883 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.235ns (logic 0.491ns (39.769%) route 0.744ns (60.231%)) Logic Levels: 0 Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.139 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.744 0.882 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.232ns (logic 0.595ns (48.288%) route 0.637ns (51.712%)) Logic Levels: 0 Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.353ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.242 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.637 0.879 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.225ns (logic 0.482ns (39.361%) route 0.743ns (60.639%)) Logic Levels: 0 Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 0.743 0.872 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.222ns (logic 0.482ns (39.449%) route 0.740ns (60.551%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 0.740 0.872 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.215ns (logic 0.480ns (39.516%) route 0.735ns (60.484%)) Logic Levels: 0 Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.128 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 0.735 0.863 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.194ns (logic 0.480ns (40.215%) route 0.714ns (59.785%)) Logic Levels: 0 Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 0.714 0.843 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.695 -0.567 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_confreg/int_out_or_q2_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.180ns (logic 0.175ns (14.825%) route 1.005ns (85.175%)) Logic Levels: 0 Clock Path Skew: -0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.509ns Source Clock Delay (SCD): -0.337ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.971 -0.337 u_confreg/sys_clk SLICE_X11Y58 FDRE r u_confreg/int_out_or_q2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y58 FDRE (Prop_fdre_C_Q) 0.175 -0.162 r u_confreg/int_out_or_q2_reg/Q net (fo=1, routed) 1.005 0.843 u_cpu/u_csr/interrupt[0] SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.135ns (logic 0.491ns (43.278%) route 0.644ns (56.722%)) Logic Levels: 0 Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.353ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 0.644 0.781 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.130ns (logic 0.485ns (42.936%) route 0.645ns (57.064%)) Logic Levels: 0 Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.353ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.645 0.776 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.122ns (logic 0.485ns (43.231%) route 0.637ns (56.769%)) Logic Levels: 0 Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.135 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 0.637 0.772 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.696 -0.566 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.111ns (logic 0.491ns (44.191%) route 0.620ns (55.809%)) Logic Levels: 0 Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.353ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.620 0.758 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.695 -0.567 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.097ns (logic 0.485ns (44.212%) route 0.612ns (55.788%)) Logic Levels: 0 Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.133 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 0.612 0.745 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.696 -0.566 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.089ns (logic 0.482ns (44.271%) route 0.607ns (55.729%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.569ns Source Clock Delay (SCD): -0.350ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y77 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 0.607 0.739 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.693 -0.569 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_matmul_axi_slave/done_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.975ns (logic 0.204ns (20.919%) route 0.771ns (79.081%)) Logic Levels: 0 Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.508ns Source Clock Delay (SCD): -0.393ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.915 -0.393 u_matmul_axi_slave/sys_clk SLICE_X46Y72 FDRE r u_matmul_axi_slave/done_reg/C ------------------------------------------------------------------- ------------------- SLICE_X46Y72 FDRE (Prop_fdre_C_Q) 0.204 -0.189 r u_matmul_axi_slave/done_reg/Q net (fo=12, routed) 0.771 0.582 u_cpu/u_csr/interrupt[2] SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.755 -0.508 u_cpu/u_csr/cpu_clk SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C Slack: inf Source: u_cdma_matmul_bridge/seq_done_flag_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.752ns (logic 0.231ns (30.703%) route 0.521ns (69.297%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.921 -0.387 u_cdma_matmul_bridge/sys_clk SLICE_X61Y63 FDRE r u_cdma_matmul_bridge/seq_done_flag_reg/C ------------------------------------------------------------------- ------------------- SLICE_X61Y63 FDRE (Prop_fdre_C_Q) 0.175 -0.212 r u_cdma_matmul_bridge/seq_done_flag_reg/Q net (fo=3, routed) 0.521 0.309 u_snix_axil_cdma_mux_8ch/cdma_matmul_seq_irq SLICE_X57Y58 LUT5 (Prop_lut5_I4_O) 0.056 0.365 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O net (fo=1, routed) 0.000 0.365 u_cpu/u_csr/interrupt[1] SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.652 -0.610 u_cpu/u_csr/cpu_clk SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.576ns (logic 0.160ns (27.764%) route 0.416ns (72.236%)) Logic Levels: 0 Clock Path Skew: -0.308ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.539ns Source Clock Delay (SCD): -0.231ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.160 -0.071 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.416 0.345 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.723 -0.539 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.577ns (logic 0.175ns (30.321%) route 0.402ns (69.679%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.574ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.175 -0.172 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.402 0.230 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.688 -0.574 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.550ns (logic 0.160ns (29.072%) route 0.390ns (70.928%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.568ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.962 -0.346 u_Axi_CDC/bFifo/sys_clk SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.160 -0.186 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.390 0.204 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.549ns (logic 0.175ns (31.853%) route 0.374ns (68.147%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.568ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.962 -0.346 u_Axi_CDC/bFifo/sys_clk SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.175 -0.171 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.374 0.203 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.482ns (logic 0.175ns (36.304%) route 0.307ns (63.696%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.568ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.962 -0.346 u_Axi_CDC/bFifo/sys_clk SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.175 -0.171 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.307 0.136 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.363ns (logic 0.175ns (48.223%) route 0.188ns (51.777%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.465ns Source Clock Delay (SCD): -0.231ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.175 -0.056 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.188 0.132 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.446ns (logic 0.160ns (35.900%) route 0.286ns (64.100%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.553ns Source Clock Delay (SCD): -0.321ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.987 -0.321 u_Axi_CDC/rFifo/sys_clk SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.160 -0.161 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=4, routed) 0.286 0.125 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.709 -0.553 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.316ns (logic 0.175ns (55.416%) route 0.141ns (44.584%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.465ns Source Clock Delay (SCD): -0.231ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.175 -0.056 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.141 0.085 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: cpu_clk To Clock: sys_clk Max Delay 162 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.565ns (logic 0.595ns (38.011%) route 0.970ns (61.989%)) Logic Levels: 0 Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.544ns Source Clock Delay (SCD): -0.232ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.363 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.970 1.333 u_Axi_CDC/wFifo/_zz_ram_port10__0[1] SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.442ns (logic 0.612ns (42.441%) route 0.830ns (57.559%)) Logic Levels: 0 Clock Path Skew: -0.317ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.548ns Source Clock Delay (SCD): -0.231ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/WCLK SLICE_X6Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y48 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.381 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/O net (fo=1, routed) 0.830 1.211 u_Axi_CDC/wFifo/_zz_ram_port10__0[36] SLICE_X4Y69 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.714 -0.548 u_Axi_CDC/wFifo/sys_clk SLICE_X4Y69 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.394ns (logic 0.485ns (34.784%) route 0.909ns (65.216%)) Logic Levels: 0 Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.544ns Source Clock Delay (SCD): -0.232ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.909 1.162 u_Axi_CDC/wFifo/_zz_ram_port10__0[16] SLICE_X6Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk SLICE_X6Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.251ns (logic 0.480ns (38.383%) route 0.771ns (61.617%)) Logic Levels: 0 Clock Path Skew: -0.315ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.544ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.251 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 0.771 1.021 u_Axi_CDC/wFifo/_zz_ram_port10__0[23] SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Fast Process Corner) Data Path Delay: 1.198ns (logic 0.231ns (19.278%) route 0.967ns (80.722%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.541ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.175 -0.054 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.272 0.218 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.056 0.274 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.695 0.969 u_Axi_CDC/awFifo/bufferCC_12/p_0_in SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Fast Process Corner) Data Path Delay: 1.198ns (logic 0.231ns (19.278%) route 0.967ns (80.722%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.541ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 pll_clk.u_rst_cpu/cpu_clk SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.175 -0.054 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.272 0.218 pll_clk.u_rst_cpu/cpu_resetn SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.056 0.274 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.695 0.969 u_Axi_CDC/awFifo/bufferCC_12/p_0_in SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.183ns (logic 0.485ns (41.003%) route 0.698ns (58.997%)) Logic Levels: 0 Clock Path Skew: -0.316ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.545ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.256 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.698 0.954 u_Axi_CDC/wFifo/_zz_ram_port10__0[22] SLICE_X4Y66 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.717 -0.545 u_Axi_CDC/wFifo/sys_clk SLICE_X4Y66 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.172ns (logic 0.595ns (50.766%) route 0.577ns (49.234%)) Logic Levels: 0 Clock Path Skew: -0.313ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.544ns Source Clock Delay (SCD): -0.231ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.364 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.577 0.941 u_Axi_CDC/wFifo/_zz_ram_port10__0[31] SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.160ns (logic 0.485ns (41.821%) route 0.675ns (58.179%)) Logic Levels: 0 Clock Path Skew: -0.309ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.538ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.256 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.675 0.931 u_Axi_CDC/wFifo/_zz_ram_port10__0[10] SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.146ns (logic 0.612ns (53.398%) route 0.534ns (46.602%)) Logic Levels: 0 Clock Path Skew: -0.309ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.540ns Source Clock Delay (SCD): -0.231ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.381 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 0.534 0.915 u_Axi_CDC/wFifo/_zz_ram_port10__0[30] SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.722 -0.540 u_Axi_CDC/wFifo/sys_clk SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.116ns (logic 0.595ns (53.305%) route 0.521ns (46.695%)) Logic Levels: 0 Clock Path Skew: -0.308ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.540ns Source Clock Delay (SCD): -0.232ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.363 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.521 0.884 u_Axi_CDC/wFifo/_zz_ram_port10__0[13] SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.722 -0.540 u_Axi_CDC/wFifo/sys_clk SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.107ns (logic 0.480ns (43.345%) route 0.627ns (56.655%)) Logic Levels: 0 Clock Path Skew: -0.315ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.544ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.251 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 0.627 0.878 u_Axi_CDC/wFifo/_zz_ram_port10__0[29] SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.202ns (logic 0.612ns (50.922%) route 0.590ns (49.078%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.574ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.260 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/O net (fo=1, routed) 0.590 0.850 u_Axi_CDC/arFifo/_zz_ram_port10__1[18] SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/arFifo/sys_clk SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.188ns (logic 0.595ns (50.069%) route 0.593ns (49.931%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.574ns Source Clock Delay (SCD): -0.341ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X22Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y58 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.254 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/O net (fo=1, routed) 0.593 0.847 u_Axi_CDC/awFifo/_zz_ram_port10[19] SLICE_X22Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk SLICE_X22Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.021ns (logic 0.595ns (58.252%) route 0.426ns (41.748%)) Logic Levels: 0 Clock Path Skew: -0.315ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.544ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.366 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.426 0.792 u_Axi_CDC/wFifo/_zz_ram_port10__0[7] SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.128ns (logic 0.480ns (42.561%) route 0.648ns (57.439%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.571ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.128 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/O net (fo=1, routed) 0.648 0.776 u_Axi_CDC/arFifo/_zz_ram_port10__1[23] SLICE_X14Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.691 -0.571 u_Axi_CDC/arFifo/sys_clk SLICE_X14Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.005ns (logic 0.480ns (47.778%) route 0.525ns (52.222%)) Logic Levels: 0 Clock Path Skew: -0.308ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.539ns Source Clock Delay (SCD): -0.231ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.249 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/O net (fo=1, routed) 0.525 0.773 u_Axi_CDC/wFifo/_zz_ram_port10__0[35] SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.002ns (logic 0.482ns (48.095%) route 0.520ns (51.905%)) Logic Levels: 0 Clock Path Skew: -0.309ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.538ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 0.520 0.773 u_Axi_CDC/wFifo/_zz_ram_port10__0[21] SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.001ns (logic 0.480ns (47.953%) route 0.521ns (52.047%)) Logic Levels: 0 Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.539ns Source Clock Delay (SCD): -0.232ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.248 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 0.521 0.769 u_Axi_CDC/wFifo/_zz_ram_port10__0[17] SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.109ns (logic 0.612ns (55.196%) route 0.497ns (44.804%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.573ns Source Clock Delay (SCD): -0.340ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.968 -0.340 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X20Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y60 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.272 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/O net (fo=1, routed) 0.497 0.769 u_Axi_CDC/arFifo/_zz_ram_port10__1[24] SLICE_X12Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/arFifo/sys_clk SLICE_X12Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.116ns (logic 0.485ns (43.457%) route 0.631ns (56.543%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.576ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.133 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/O net (fo=1, routed) 0.631 0.764 u_Axi_CDC/arFifo/_zz_ram_port10__1[22] SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/arFifo/sys_clk SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.987ns (logic 0.612ns (62.028%) route 0.375ns (37.972%)) Logic Levels: 0 Clock Path Skew: -0.309ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.538ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.383 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.375 0.757 u_Axi_CDC/wFifo/_zz_ram_port10__0[6] SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.973ns (logic 0.612ns (62.874%) route 0.361ns (37.126%)) Logic Levels: 0 Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.539ns Source Clock Delay (SCD): -0.232ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.380 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.361 0.741 u_Axi_CDC/wFifo/_zz_ram_port10__0[12] SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.966ns (logic 0.491ns (50.838%) route 0.475ns (49.162%)) Logic Levels: 0 Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.539ns Source Clock Delay (SCD): -0.232ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.259 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.475 0.734 u_Axi_CDC/wFifo/_zz_ram_port10__0[14] SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.960ns (logic 0.595ns (62.000%) route 0.365ns (38.000%)) Logic Levels: 0 Clock Path Skew: -0.309ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.538ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.366 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.365 0.730 u_Axi_CDC/wFifo/_zz_ram_port10__0[25] SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.949ns (logic 0.485ns (51.100%) route 0.464ns (48.900%)) Logic Levels: 0 Clock Path Skew: -0.308ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.539ns Source Clock Delay (SCD): -0.231ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.254 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/O net (fo=1, routed) 0.464 0.718 u_Axi_CDC/wFifo/_zz_ram_port10__0[34] SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.047ns (logic 0.595ns (56.827%) route 0.452ns (43.173%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.571ns Source Clock Delay (SCD): -0.340ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.968 -0.340 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X20Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y60 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.255 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/O net (fo=1, routed) 0.452 0.707 u_Axi_CDC/arFifo/_zz_ram_port10__1[25] SLICE_X18Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.691 -0.571 u_Axi_CDC/arFifo/sys_clk SLICE_X18Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.928ns (logic 0.482ns (51.961%) route 0.446ns (48.039%)) Logic Levels: 0 Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.536ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 0.446 0.698 u_Axi_CDC/wFifo/_zz_ram_port10__0[9] SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.726 -0.536 u_Axi_CDC/wFifo/sys_clk SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.040ns (logic 0.485ns (46.647%) route 0.555ns (53.353%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.576ns Source Clock Delay (SCD): -0.345ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X18Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y67 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.140 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/O net (fo=1, routed) 0.555 0.695 u_Axi_CDC/arFifo/_zz_ram_port10__1[46] SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/arFifo/sys_clk SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.920ns (logic 0.612ns (66.545%) route 0.308ns (33.455%)) Logic Levels: 0 Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.539ns Source Clock Delay (SCD): -0.232ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.380 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.308 0.687 u_Axi_CDC/wFifo/_zz_ram_port10__0[0] SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.025ns (logic 0.612ns (59.711%) route 0.413ns (40.289%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.573ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X22Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y60 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.270 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/O net (fo=1, routed) 0.413 0.683 u_Axi_CDC/arFifo/_zz_ram_port10__1[12] SLICE_X21Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/arFifo/sys_clk SLICE_X21Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.021ns (logic 0.612ns (59.936%) route 0.409ns (40.064%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.574ns Source Clock Delay (SCD): -0.341ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X22Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y58 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/O net (fo=1, routed) 0.409 0.680 u_Axi_CDC/awFifo/_zz_ram_port10[18] SLICE_X22Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk SLICE_X22Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.026ns (logic 0.482ns (46.999%) route 0.544ns (53.001%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.574ns Source Clock Delay (SCD): -0.352ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.130 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/O net (fo=1, routed) 0.544 0.673 u_Axi_CDC/arFifo/_zz_ram_port10__1[21] SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/arFifo/sys_clk SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.019ns (logic 0.595ns (58.363%) route 0.424ns (41.637%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.576ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X22Y67 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.247 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/O net (fo=1, routed) 0.424 0.671 u_Axi_CDC/awFifo/_zz_ram_port10[31] SLICE_X23Y67 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/awFifo/sys_clk SLICE_X23Y67 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.898ns (logic 0.612ns (68.152%) route 0.286ns (31.848%)) Logic Levels: 0 Clock Path Skew: -0.308ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.537ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.383 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 0.286 0.669 u_Axi_CDC/wFifo/_zz_ram_port10__0[18] SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.725 -0.537 u_Axi_CDC/wFifo/sys_clk SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.896ns (logic 0.595ns (66.419%) route 0.301ns (33.581%)) Logic Levels: 0 Clock Path Skew: -0.309ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.538ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.366 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.301 0.667 u_Axi_CDC/wFifo/_zz_ram_port10__0[19] SLICE_X3Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk SLICE_X3Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.012ns (logic 0.485ns (47.912%) route 0.527ns (52.088%)) Logic Levels: 0 Clock Path Skew: -0.264ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.612ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.137 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 0.527 0.664 u_Axi_CDC/arFifo/_zz_ram_port10__1[4] SLICE_X46Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.650 -0.612 u_Axi_CDC/arFifo/sys_clk SLICE_X46Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.892ns (logic 0.480ns (53.815%) route 0.412ns (46.185%)) Logic Levels: 0 Clock Path Skew: -0.306ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.538ns Source Clock Delay (SCD): -0.232ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.248 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 0.412 0.660 u_Axi_CDC/wFifo/_zz_ram_port10__0[5] SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.880ns (logic 0.612ns (69.559%) route 0.268ns (30.441%)) Logic Levels: 0 Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.536ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.383 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.268 0.651 u_Axi_CDC/wFifo/_zz_ram_port10__0[24] SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.726 -0.536 u_Axi_CDC/wFifo/sys_clk SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.879ns (logic 0.482ns (54.834%) route 0.397ns (45.166%)) Logic Levels: 0 Clock Path Skew: -0.315ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.544ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 0.397 0.650 u_Axi_CDC/wFifo/_zz_ram_port10__0[27] SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.990ns (logic 0.612ns (61.797%) route 0.378ns (38.203%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.574ns Source Clock Delay (SCD): -0.341ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X22Y59 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y59 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/O net (fo=1, routed) 0.378 0.649 u_Axi_CDC/awFifo/_zz_ram_port10[12] SLICE_X24Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk SLICE_X24Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.981ns (logic 0.612ns (62.415%) route 0.369ns (37.585%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.570ns Source Clock Delay (SCD): -0.341ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X22Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y57 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/O net (fo=1, routed) 0.369 0.639 u_Axi_CDC/awFifo/_zz_ram_port10[24] SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.692 -0.570 u_Axi_CDC/awFifo/sys_clk SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.866ns (logic 0.485ns (56.026%) route 0.381ns (43.974%)) Logic Levels: 0 Clock Path Skew: -0.309ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.538ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.256 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 0.381 0.636 u_Axi_CDC/wFifo/_zz_ram_port10__0[28] SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.867ns (logic 0.491ns (56.612%) route 0.376ns (43.388%)) Logic Levels: 0 Clock Path Skew: -0.308ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.540ns Source Clock Delay (SCD): -0.232ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.259 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.376 0.635 u_Axi_CDC/wFifo/_zz_ram_port10__0[2] SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.722 -0.540 u_Axi_CDC/wFifo/sys_clk SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.955ns (logic 0.612ns (64.074%) route 0.343ns (35.926%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.568ns Source Clock Delay (SCD): -0.338ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y57 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.274 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/O net (fo=1, routed) 0.343 0.617 u_Axi_CDC/awFifo/_zz_ram_port10[6] SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/awFifo/sys_clk SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.947ns (logic 0.595ns (62.805%) route 0.352ns (37.195%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.573ns Source Clock Delay (SCD): -0.341ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.254 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/O net (fo=1, routed) 0.352 0.606 u_Axi_CDC/awFifo/_zz_ram_port10[43] SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/awFifo/sys_clk SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.953ns (logic 0.612ns (64.216%) route 0.341ns (35.784%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.577ns Source Clock Delay (SCD): -0.348ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.264 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 0.341 0.605 u_Axi_CDC/arFifo/_zz_ram_port10__1[0] SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.685 -0.577 u_Axi_CDC/arFifo/sys_clk SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.833ns (logic 0.491ns (58.937%) route 0.342ns (41.063%)) Logic Levels: 0 Clock Path Skew: -0.308ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.537ns Source Clock Delay (SCD): -0.229ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.262 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 0.342 0.604 u_Axi_CDC/wFifo/_zz_ram_port10__0[8] SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.725 -0.537 u_Axi_CDC/wFifo/sys_clk SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.937ns (logic 0.595ns (63.501%) route 0.342ns (36.499%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.568ns Source Clock Delay (SCD): -0.338ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y57 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.257 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 0.342 0.599 u_Axi_CDC/awFifo/_zz_ram_port10[7] SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/awFifo/sys_clk SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.914ns (logic 0.612ns (66.980%) route 0.302ns (33.020%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.573ns Source Clock Delay (SCD): -0.341ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/O net (fo=1, routed) 0.302 0.573 u_Axi_CDC/awFifo/_zz_ram_port10[42] SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/awFifo/sys_clk SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: clkfbout_clk_pll To Clock: Max Delay 1 Endpoint Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT (clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Path Group: (none) Path Type: Max at Fast Process Corner Data Path Delay: 1.519ns (logic 0.029ns (1.909%) route 1.490ns (98.091%)) Logic Levels: 1 (BUFG=1) Clock Uncertainty: 0.169ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.075ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clkfbout_clk_pll fall edge) 10.000 10.000 f K21 0.000 10.000 f clk (IN) net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 10.419 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 10.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.847 8.053 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT net (fo=1, routed) 0.611 8.663 pll_clk.u_clk_pll/inst/clkfbout_clk_pll BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 8.692 f pll_clk.u_clk_pll/inst/clkf_buf/O net (fo=1, routed) 0.880 9.572 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: Max Delay 41 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_clk (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.589ns (logic 3.629ns (42.252%) route 4.960ns (57.748%)) Logic Levels: 2 (BUFG=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk fall edge) 10.000 10.000 f K21 0.000 10.000 f clk (IN) net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 11.463 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 12.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 3.725 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 5.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 5.658 f pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 3.123 8.781 video_clk_OBUF H22 OBUF (Prop_obuf_I_O) 3.533 12.314 f video_clk_OBUF_inst/O net (fo=0) 0.000 12.314 video_clk H22 f video_clk (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_RECT_L_W_reg[22]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 14.637ns (logic 5.878ns (40.155%) route 8.759ns (59.845%)) Logic Levels: 9 (CARRY4=4 LUT2=2 LUT4=1 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.941 -2.401 u_axi_dvi/sys_clk SLICE_X11Y83 FDRE r u_axi_dvi/DVI_RECT_L_W_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X11Y83 FDRE (Prop_fdre_C_Q) 0.456 -1.945 r u_axi_dvi/DVI_RECT_L_W_reg[22]/Q net (fo=3, routed) 1.109 -0.836 u_axi_dvi/p_0_in6_in[6] SLICE_X10Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.712 r u_axi_dvi/video_red_OBUF[2]_inst_i_271/O net (fo=1, routed) 0.000 -0.712 u_axi_dvi/video_red_OBUF[2]_inst_i_271_n_0 SLICE_X10Y83 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.380 -0.332 r u_axi_dvi/video_red_OBUF[2]_inst_i_239/CO[3] net (fo=1, routed) 0.000 -0.332 u_axi_dvi/video_red_OBUF[2]_inst_i_239_n_0 SLICE_X10Y84 CARRY4 (Prop_carry4_CI_O[3]) 0.315 -0.017 r u_axi_dvi/video_red_OBUF[2]_inst_i_200/O[3] net (fo=1, routed) 0.864 0.847 u_axi_dvi/video_red_OBUF[2]_inst_i_200_n_4 SLICE_X11Y84 LUT2 (Prop_lut2_I1_O) 0.307 1.154 r u_axi_dvi/video_red_OBUF[2]_inst_i_132/O net (fo=1, routed) 0.000 1.154 u_axi_dvi/video_red_OBUF[2]_inst_i_132_n_0 SLICE_X11Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 1.555 r u_axi_dvi/video_red_OBUF[2]_inst_i_67/CO[3] net (fo=1, routed) 0.000 1.555 u_axi_dvi/video_red_OBUF[2]_inst_i_67_n_0 SLICE_X11Y85 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.669 f u_axi_dvi/video_red_OBUF[2]_inst_i_31/CO[3] net (fo=1, routed) 1.273 2.942 u_axi_dvi/video_red_OBUF[2]_inst_i_31_n_0 SLICE_X16Y85 LUT4 (Prop_lut4_I0_O) 0.124 3.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O net (fo=1, routed) 0.670 3.736 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 SLICE_X16Y85 LUT5 (Prop_lut5_I4_O) 0.124 3.860 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 4.844 8.704 video_red_OBUF[0] K23 OBUF (Prop_obuf_I_O) 3.533 12.236 r video_red_OBUF[0]_inst/O net (fo=0) 0.000 12.236 video_red[0] K23 r video_red[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_RECT_L_W_reg[22]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 14.524ns (logic 5.905ns (40.660%) route 8.618ns (59.340%)) Logic Levels: 9 (CARRY4=4 LUT2=2 LUT4=1 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.941 -2.401 u_axi_dvi/sys_clk SLICE_X11Y83 FDRE r u_axi_dvi/DVI_RECT_L_W_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X11Y83 FDRE (Prop_fdre_C_Q) 0.456 -1.945 r u_axi_dvi/DVI_RECT_L_W_reg[22]/Q net (fo=3, routed) 1.109 -0.836 u_axi_dvi/p_0_in6_in[6] SLICE_X10Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.712 r u_axi_dvi/video_red_OBUF[2]_inst_i_271/O net (fo=1, routed) 0.000 -0.712 u_axi_dvi/video_red_OBUF[2]_inst_i_271_n_0 SLICE_X10Y83 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.380 -0.332 r u_axi_dvi/video_red_OBUF[2]_inst_i_239/CO[3] net (fo=1, routed) 0.000 -0.332 u_axi_dvi/video_red_OBUF[2]_inst_i_239_n_0 SLICE_X10Y84 CARRY4 (Prop_carry4_CI_O[3]) 0.315 -0.017 r u_axi_dvi/video_red_OBUF[2]_inst_i_200/O[3] net (fo=1, routed) 0.864 0.847 u_axi_dvi/video_red_OBUF[2]_inst_i_200_n_4 SLICE_X11Y84 LUT2 (Prop_lut2_I1_O) 0.307 1.154 r u_axi_dvi/video_red_OBUF[2]_inst_i_132/O net (fo=1, routed) 0.000 1.154 u_axi_dvi/video_red_OBUF[2]_inst_i_132_n_0 SLICE_X11Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 1.555 r u_axi_dvi/video_red_OBUF[2]_inst_i_67/CO[3] net (fo=1, routed) 0.000 1.555 u_axi_dvi/video_red_OBUF[2]_inst_i_67_n_0 SLICE_X11Y85 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.669 f u_axi_dvi/video_red_OBUF[2]_inst_i_31/CO[3] net (fo=1, routed) 1.273 2.942 u_axi_dvi/video_red_OBUF[2]_inst_i_31_n_0 SLICE_X16Y85 LUT4 (Prop_lut4_I0_O) 0.124 3.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O net (fo=1, routed) 0.670 3.736 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 SLICE_X16Y85 LUT5 (Prop_lut5_I4_O) 0.124 3.860 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 4.703 8.563 video_red_OBUF[0] F24 OBUF (Prop_obuf_I_O) 3.560 12.123 r video_red_OBUF[1]_inst/O net (fo=0) 0.000 12.123 video_red[1] F24 r video_red[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_RECT_L_W_reg[22]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 14.257ns (logic 5.932ns (41.605%) route 8.325ns (58.395%)) Logic Levels: 9 (CARRY4=4 LUT2=2 LUT4=1 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.941 -2.401 u_axi_dvi/sys_clk SLICE_X11Y83 FDRE r u_axi_dvi/DVI_RECT_L_W_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X11Y83 FDRE (Prop_fdre_C_Q) 0.456 -1.945 r u_axi_dvi/DVI_RECT_L_W_reg[22]/Q net (fo=3, routed) 1.109 -0.836 u_axi_dvi/p_0_in6_in[6] SLICE_X10Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.712 r u_axi_dvi/video_red_OBUF[2]_inst_i_271/O net (fo=1, routed) 0.000 -0.712 u_axi_dvi/video_red_OBUF[2]_inst_i_271_n_0 SLICE_X10Y83 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.380 -0.332 r u_axi_dvi/video_red_OBUF[2]_inst_i_239/CO[3] net (fo=1, routed) 0.000 -0.332 u_axi_dvi/video_red_OBUF[2]_inst_i_239_n_0 SLICE_X10Y84 CARRY4 (Prop_carry4_CI_O[3]) 0.315 -0.017 r u_axi_dvi/video_red_OBUF[2]_inst_i_200/O[3] net (fo=1, routed) 0.864 0.847 u_axi_dvi/video_red_OBUF[2]_inst_i_200_n_4 SLICE_X11Y84 LUT2 (Prop_lut2_I1_O) 0.307 1.154 r u_axi_dvi/video_red_OBUF[2]_inst_i_132/O net (fo=1, routed) 0.000 1.154 u_axi_dvi/video_red_OBUF[2]_inst_i_132_n_0 SLICE_X11Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 1.555 r u_axi_dvi/video_red_OBUF[2]_inst_i_67/CO[3] net (fo=1, routed) 0.000 1.555 u_axi_dvi/video_red_OBUF[2]_inst_i_67_n_0 SLICE_X11Y85 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.669 f u_axi_dvi/video_red_OBUF[2]_inst_i_31/CO[3] net (fo=1, routed) 1.273 2.942 u_axi_dvi/video_red_OBUF[2]_inst_i_31_n_0 SLICE_X16Y85 LUT4 (Prop_lut4_I0_O) 0.124 3.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O net (fo=1, routed) 0.670 3.736 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 SLICE_X16Y85 LUT5 (Prop_lut5_I4_O) 0.124 3.860 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 4.410 8.270 video_red_OBUF[0] E26 OBUF (Prop_obuf_I_O) 3.587 11.856 r video_red_OBUF[2]_inst/O net (fo=0) 0.000 11.856 video_red[2] E26 r video_red[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_vsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 12.474ns (logic 4.441ns (35.600%) route 8.033ns (64.400%)) Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.934 -2.408 u_axi_dvi/sys_clk SLICE_X18Y79 FDRE r u_axi_dvi/vdata_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X18Y79 FDRE (Prop_fdre_C_Q) 0.518 -1.890 r u_axi_dvi/vdata_reg[3]/Q net (fo=11, routed) 1.619 -0.271 u_axi_dvi/vdata_reg_n_0_[3] SLICE_X18Y86 LUT2 (Prop_lut2_I0_O) 0.124 -0.147 f u_axi_dvi/vdata[11]_i_4/O net (fo=3, routed) 0.682 0.535 u_axi_dvi/vdata[11]_i_4_n_0 SLICE_X18Y86 LUT6 (Prop_lut6_I5_O) 0.124 0.659 r u_axi_dvi/video_vsync_OBUF_inst_i_2/O net (fo=1, routed) 0.789 1.448 u_axi_dvi/video_vsync_OBUF_inst_i_2_n_0 SLICE_X17Y86 LUT4 (Prop_lut4_I0_O) 0.124 1.572 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O net (fo=1, routed) 4.943 6.515 video_vsync_OBUF H24 OBUF (Prop_obuf_I_O) 3.551 10.066 r video_vsync_OBUF_inst/O net (fo=0) 0.000 10.066 video_vsync H24 r video_vsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_de (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 12.135ns (logic 4.451ns (36.677%) route 7.684ns (63.323%)) Logic Levels: 4 (LUT2=1 LUT6=2 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.934 -2.408 u_axi_dvi/sys_clk SLICE_X18Y79 FDRE r u_axi_dvi/vdata_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X18Y79 FDRE (Prop_fdre_C_Q) 0.518 -1.890 f u_axi_dvi/vdata_reg[3]/Q net (fo=11, routed) 1.619 -0.271 u_axi_dvi/vdata_reg_n_0_[3] SLICE_X18Y86 LUT2 (Prop_lut2_I0_O) 0.124 -0.147 r u_axi_dvi/vdata[11]_i_4/O net (fo=3, routed) 0.305 0.158 u_axi_dvi/vdata[11]_i_4_n_0 SLICE_X17Y86 LUT6 (Prop_lut6_I2_O) 0.124 0.282 r u_axi_dvi/video_de_OBUF_inst_i_2/O net (fo=1, routed) 1.030 1.313 u_axi_dvi/video_de_OBUF_inst_i_2_n_0 SLICE_X14Y86 LUT6 (Prop_lut6_I0_O) 0.124 1.437 r u_axi_dvi/video_de_OBUF_inst_i_1/O net (fo=1, routed) 4.730 6.166 video_de_OBUF G24 OBUF (Prop_obuf_I_O) 3.561 9.727 r video_de_OBUF_inst/O net (fo=0) 0.000 9.727 video_de G24 r video_de (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_hsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.932ns (logic 4.311ns (36.128%) route 7.621ns (63.872%)) Logic Levels: 3 (LUT5=2 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.936 -2.406 u_axi_dvi/sys_clk SLICE_X12Y81 FDRE r u_axi_dvi/hdata_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.888 r u_axi_dvi/hdata_reg[3]/Q net (fo=11, routed) 1.940 0.053 u_axi_dvi/hdata_reg_n_0_[3] SLICE_X8Y82 LUT5 (Prop_lut5_I2_O) 0.124 0.177 f u_axi_dvi/video_hsync_OBUF_inst_i_2/O net (fo=1, routed) 0.953 1.130 u_axi_dvi/video_hsync_OBUF_inst_i_2_n_0 SLICE_X9Y86 LUT5 (Prop_lut5_I4_O) 0.124 1.254 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O net (fo=1, routed) 4.728 5.982 video_hsync_OBUF J24 OBUF (Prop_obuf_I_O) 3.545 9.527 r video_hsync_OBUF_inst/O net (fo=0) 0.000 9.527 video_hsync J24 r video_hsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[8]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[8] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.822ns (logic 4.079ns (34.503%) route 7.743ns (65.497%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.016 -2.326 u_confreg/sys_clk SLICE_X2Y81 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.808 r u_confreg/led_data_reg[8]_lopt_replica/Q net (fo=1, routed) 7.743 5.935 lopt_14 C23 OBUF (Prop_obuf_I_O) 3.561 9.496 r leds_OBUF[8]_inst/O net (fo=0) 0.000 9.496 leds[8] C23 r leds[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[15]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[15] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.646ns (logic 4.019ns (34.509%) route 7.627ns (65.491%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk SLICE_X0Y95 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[15]_lopt_replica/Q net (fo=1, routed) 7.627 5.768 lopt_6 B20 OBUF (Prop_obuf_I_O) 3.563 9.331 r leds_OBUF[15]_inst/O net (fo=0) 0.000 9.331 leds[15] B20 r leds[15] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[4]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.447ns (logic 4.018ns (35.101%) route 7.429ns (64.899%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.025 -2.317 u_confreg/sys_clk SLICE_X3Y89 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.456 -1.861 r u_confreg/led_data_reg[4]_lopt_replica/Q net (fo=1, routed) 7.429 5.569 lopt_10 C22 OBUF (Prop_obuf_I_O) 3.562 9.131 r leds_OBUF[4]_inst/O net (fo=0) 0.000 9.131 leds[4] C22 r leds[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.583ns (logic 3.995ns (34.493%) route 7.588ns (65.507%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q net (fo=1, routed) 7.588 5.556 dpy0_OBUF[4] E18 OBUF (Prop_obuf_I_O) 3.539 9.095 r dpy0_OBUF[4]_inst/O net (fo=0) 0.000 9.095 dpy0[4] E18 r dpy0[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[5]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.360ns (logic 4.147ns (36.509%) route 7.213ns (63.491%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk SLICE_X0Y95 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.419 -1.896 r u_confreg/led_data_reg[5]_lopt_replica/Q net (fo=1, routed) 7.213 5.317 lopt_11 C21 OBUF (Prop_obuf_I_O) 3.728 9.045 r leds_OBUF[5]_inst/O net (fo=0) 0.000 9.045 leds[5] C21 r leds[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[9]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[9] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.061ns (logic 4.038ns (36.509%) route 7.023ns (63.491%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.022 -2.320 u_confreg/sys_clk SLICE_X0Y86 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.456 -1.864 r u_confreg/led_data_reg[9]_lopt_replica/Q net (fo=1, routed) 7.023 5.159 lopt_15 A23 OBUF (Prop_obuf_I_O) 3.582 8.741 r leds_OBUF[9]_inst/O net (fo=0) 0.000 8.741 leds[9] A23 r leds[9] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/mcr_reg[4]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_TX (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.130ns (logic 4.308ns (38.708%) route 6.822ns (61.292%)) Logic Levels: 2 (LUT4=1 OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.939 -2.403 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X8Y66 FDRE r u_axi_uart_controller/uart0/regs/mcr_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y66 FDRE (Prop_fdre_C_Q) 0.478 -1.925 r u_axi_uart_controller/uart0/regs/mcr_reg[4]/Q net (fo=8, routed) 1.213 -0.712 u_axi_uart_controller/uart0/regs/transmitter/counter_b_reg[7]_0[0] SLICE_X1Y60 LUT4 (Prop_lut4_I3_O) 0.301 -0.411 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_1/O net (fo=1, routed) 5.609 5.198 UART_TX_IOBUF_inst/I H18 OBUFT (Prop_obuft_I_O) 3.529 8.727 r UART_TX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 8.727 UART_TX H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.508ns (logic 3.970ns (37.784%) route 6.537ns (62.216%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q net (fo=1, routed) 6.537 4.680 dpy1_OBUF[3] F17 OBUF (Prop_obuf_I_O) 3.514 8.194 r dpy1_OBUF[3]_inst/O net (fo=0) 0.000 8.194 dpy1[3] F17 r dpy1[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.468ns (logic 4.014ns (38.349%) route 6.454ns (61.651%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q net (fo=1, routed) 6.454 4.422 dpy0_OBUF[2] B21 OBUF (Prop_obuf_I_O) 3.558 7.981 r dpy0_OBUF[2]_inst/O net (fo=0) 0.000 7.981 dpy0[2] B21 r dpy0[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[3]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.251ns (logic 4.018ns (39.198%) route 6.233ns (60.802%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk SLICE_X0Y98 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[3]_lopt_replica/Q net (fo=1, routed) 6.233 4.375 lopt_9 D23 OBUF (Prop_obuf_I_O) 3.562 7.937 r leds_OBUF[3]_inst/O net (fo=0) 0.000 7.937 leds[3] D23 r leds[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[2]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.239ns (logic 4.043ns (39.483%) route 6.196ns (60.517%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk SLICE_X0Y98 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[2]_lopt_replica/Q net (fo=1, routed) 6.196 4.339 lopt_8 A24 OBUF (Prop_obuf_I_O) 3.587 7.926 r leds_OBUF[2]_inst/O net (fo=0) 0.000 7.926 leds[2] A24 r leds[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[11]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[11] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.633ns (logic 4.023ns (41.758%) route 5.611ns (58.242%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk SLICE_X0Y96 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[11]_lopt_replica/Q net (fo=1, routed) 5.611 3.752 lopt_2 A18 OBUF (Prop_obuf_I_O) 3.567 7.319 r leds_OBUF[11]_inst/O net (fo=0) 0.000 7.319 leds[11] A18 r leds[11] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.588ns (logic 3.993ns (41.645%) route 5.595ns (58.355%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q net (fo=1, routed) 5.595 3.738 dpy1_OBUF[6] F15 OBUF (Prop_obuf_I_O) 3.537 7.275 r dpy1_OBUF[6]_inst/O net (fo=0) 0.000 7.275 dpy1[6] F15 r dpy1[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[6]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.545ns (logic 4.133ns (43.294%) route 5.413ns (56.706%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk SLICE_X0Y95 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.419 -1.896 r u_confreg/led_data_reg[6]_lopt_replica/Q net (fo=1, routed) 5.413 3.517 lopt_12 E20 OBUF (Prop_obuf_I_O) 3.714 7.231 r leds_OBUF[6]_inst/O net (fo=0) 0.000 7.231 leds[6] E20 r leds[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.552ns (logic 4.002ns (41.895%) route 5.550ns (58.105%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q net (fo=1, routed) 5.550 3.519 dpy0_OBUF[5] C19 OBUF (Prop_obuf_I_O) 3.546 7.065 r dpy0_OBUF[5]_inst/O net (fo=0) 0.000 7.065 dpy0[5] C19 r dpy0[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.354ns (logic 3.998ns (42.735%) route 5.357ns (57.265%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q net (fo=1, routed) 5.357 3.499 dpy1_OBUF[2] E17 OBUF (Prop_obuf_I_O) 3.542 7.041 r dpy1_OBUF[2]_inst/O net (fo=0) 0.000 7.041 dpy1[2] E17 r dpy1[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/sclk_reg_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_RX (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.365ns (logic 4.162ns (44.443%) route 5.203ns (55.557%)) Logic Levels: 2 (LUT2=1 OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.944 -2.398 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X10Y64 FDRE r u_axi_uart_controller/uart0/regs/sclk_reg_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y64 FDRE (Prop_fdre_C_Q) 0.518 -1.880 r u_axi_uart_controller/uart0/regs/sclk_reg_reg/Q net (fo=2, routed) 0.521 -1.358 u_axi_uart_controller/uart0/regs/sclk_reg_reg_n_0 SLICE_X10Y64 LUT2 (Prop_lut2_I0_O) 0.124 -1.234 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/O net (fo=1, routed) 4.682 3.448 UART_RX_IOBUF_inst/I J20 OBUFT (Prop_obuft_I_O) 3.520 6.968 r UART_RX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 6.968 UART_RX J20 r UART_RX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.190ns (logic 4.001ns (43.538%) route 5.189ns (56.462%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q net (fo=1, routed) 5.189 3.157 dpy0_OBUF[1] D19 OBUF (Prop_obuf_I_O) 3.545 6.703 r dpy0_OBUF[1]_inst/O net (fo=0) 0.000 6.703 dpy0[1] D19 r dpy0[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.973ns (logic 3.998ns (44.549%) route 4.976ns (55.451%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q net (fo=1, routed) 4.976 3.118 dpy1_OBUF[4] E16 OBUF (Prop_obuf_I_O) 3.542 6.660 r dpy1_OBUF[4]_inst/O net (fo=0) 0.000 6.660 dpy1[4] E16 r dpy1[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.071ns (logic 4.029ns (44.418%) route 5.042ns (55.582%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q net (fo=1, routed) 5.042 3.010 dpy0_OBUF[3] A19 OBUF (Prop_obuf_I_O) 3.573 6.583 r dpy0_OBUF[3]_inst/O net (fo=0) 0.000 6.583 dpy0[3] A19 r dpy0[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.824ns (logic 4.005ns (45.390%) route 4.819ns (54.610%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q net (fo=1, routed) 4.819 2.961 dpy1_OBUF[1] D16 OBUF (Prop_obuf_I_O) 3.549 6.510 r dpy1_OBUF[1]_inst/O net (fo=0) 0.000 6.510 dpy1[1] D16 r dpy1[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[12]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[12] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.826ns (logic 3.998ns (45.302%) route 4.828ns (54.698%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.025 -2.317 u_confreg/sys_clk SLICE_X3Y89 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.456 -1.861 r u_confreg/led_data_reg[12]_lopt_replica/Q net (fo=1, routed) 4.828 2.967 lopt_3 D20 OBUF (Prop_obuf_I_O) 3.542 6.510 r leds_OBUF[12]_inst/O net (fo=0) 0.000 6.510 leds[12] D20 r leds[12] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.940ns (logic 4.016ns (44.923%) route 4.924ns (55.077%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q net (fo=1, routed) 4.924 2.892 dpy0_OBUF[0] B19 OBUF (Prop_obuf_I_O) 3.560 6.452 r dpy0_OBUF[0]_inst/O net (fo=0) 0.000 6.452 dpy0[0] B19 r dpy0[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.755ns (logic 3.990ns (45.576%) route 4.765ns (54.424%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q net (fo=1, routed) 4.765 2.907 dpy1_OBUF[5] G16 OBUF (Prop_obuf_I_O) 3.534 6.441 r dpy1_OBUF[5]_inst/O net (fo=0) 0.000 6.441 dpy1[5] G16 r dpy1[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.735ns (logic 4.021ns (46.039%) route 4.713ns (53.961%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q net (fo=1, routed) 4.713 2.856 dpy1_OBUF[0] A17 OBUF (Prop_obuf_I_O) 3.565 6.421 r dpy1_OBUF[0]_inst/O net (fo=0) 0.000 6.421 dpy1[0] A17 r dpy1[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.710ns (logic 3.976ns (45.648%) route 4.734ns (54.352%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q net (fo=1, routed) 4.734 2.877 dpy1_OBUF[7] G17 OBUF (Prop_obuf_I_O) 3.520 6.397 r dpy1_OBUF[7]_inst/O net (fo=0) 0.000 6.397 dpy1[7] G17 r dpy1[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[14]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[14] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.585ns (logic 4.019ns (46.814%) route 4.566ns (53.186%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk SLICE_X0Y95 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[14]_lopt_replica/Q net (fo=1, routed) 4.566 2.707 lopt_5 A20 OBUF (Prop_obuf_I_O) 3.563 6.270 r leds_OBUF[14]_inst/O net (fo=0) 0.000 6.270 leds[14] A20 r leds[14] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.741ns (logic 4.012ns (45.901%) route 4.729ns (54.099%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q net (fo=1, routed) 4.729 2.697 dpy0_OBUF[6] B17 OBUF (Prop_obuf_I_O) 3.556 6.254 r dpy0_OBUF[6]_inst/O net (fo=0) 0.000 6.254 dpy0[6] B17 r dpy0[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[10]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[10] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.566ns (logic 4.003ns (46.730%) route 4.563ns (53.270%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.022 -2.320 u_confreg/sys_clk SLICE_X0Y86 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.456 -1.864 r u_confreg/led_data_reg[10]_lopt_replica/Q net (fo=1, routed) 4.563 2.700 lopt_1 D21 OBUF (Prop_obuf_I_O) 3.547 6.247 r leds_OBUF[10]_inst/O net (fo=0) 0.000 6.247 leds[10] D21 r leds[10] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.730ns (logic 4.001ns (45.828%) route 4.729ns (54.172%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q net (fo=1, routed) 4.729 2.697 dpy0_OBUF[7] C17 OBUF (Prop_obuf_I_O) 3.545 6.242 r dpy0_OBUF[7]_inst/O net (fo=0) 0.000 6.242 dpy0[7] C17 r dpy0[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[7]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.548ns (logic 4.164ns (48.712%) route 4.384ns (51.288%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk SLICE_X0Y95 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.419 -1.896 r u_confreg/led_data_reg[7]_lopt_replica/Q net (fo=1, routed) 4.384 2.489 lopt_13 B22 OBUF (Prop_obuf_I_O) 3.745 6.234 r leds_OBUF[7]_inst/O net (fo=0) 0.000 6.234 leds[7] B22 r leds[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[13]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[13] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.473ns (logic 4.027ns (47.524%) route 4.446ns (52.476%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk SLICE_X1Y98 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X1Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[13]_lopt_replica/Q net (fo=1, routed) 4.446 2.588 lopt_4 A22 OBUF (Prop_obuf_I_O) 3.571 6.159 r leds_OBUF[13]_inst/O net (fo=0) 0.000 6.159 leds[13] A22 r leds[13] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[1]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.398ns (logic 3.997ns (47.597%) route 4.401ns (52.403%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk SLICE_X0Y98 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[1]_lopt_replica/Q net (fo=1, routed) 4.401 2.543 lopt_7 E21 OBUF (Prop_obuf_I_O) 3.541 6.084 r leds_OBUF[1]_inst/O net (fo=0) 0.000 6.084 leds[1] E21 r leds[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.138ns (logic 4.031ns (49.529%) route 4.108ns (50.471%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk SLICE_X0Y96 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[0]_lopt_replica/Q net (fo=1, routed) 4.108 2.249 lopt B24 OBUF (Prop_obuf_I_O) 3.575 5.824 r leds_OBUF[0]_inst/O net (fo=0) 0.000 5.824 leds[0] B24 r leds[0] (OUT) ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: To Clock: sys_clk Max Delay 43 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: dip_sw[8] (input port) Destination: u_confreg/s_rdata_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 11.851ns (logic 1.724ns (14.546%) route 10.127ns (85.454%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.940ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.940ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M6 0.000 0.000 r dip_sw[8] (IN) net (fo=0) 0.000 0.000 dip_sw[8] M6 IBUF (Prop_ibuf_I_O) 1.476 1.476 r dip_sw_IBUF[8]_inst/O net (fo=1, routed) 9.460 10.936 u_confreg/dip_sw_IBUF[8] SLICE_X5Y79 LUT5 (Prop_lut5_I4_O) 0.124 11.060 r u_confreg/s_rdata[8]_i_4/O net (fo=1, routed) 0.667 11.727 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.124 11.851 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O net (fo=1, routed) 0.000 11.851 u_confreg/u_int_ctrl_n_23 SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.888 -1.940 u_confreg/sys_clk SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/C Slack: inf Source: dip_sw[20] (input port) Destination: u_confreg/s_rdata_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 11.647ns (logic 1.723ns (14.794%) route 9.924ns (85.206%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.931ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M4 0.000 0.000 r dip_sw[20] (IN) net (fo=0) 0.000 0.000 dip_sw[20] M4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r dip_sw_IBUF[20]_inst/O net (fo=1, routed) 9.163 10.638 u_confreg/dip_sw_IBUF[20] SLICE_X7Y92 LUT5 (Prop_lut5_I4_O) 0.124 10.762 r u_confreg/s_rdata[20]_i_4/O net (fo=1, routed) 0.761 11.523 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.124 11.647 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O net (fo=1, routed) 0.000 11.647 u_confreg/u_int_ctrl_n_11 SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/C Slack: inf Source: dip_sw[13] (input port) Destination: u_confreg/s_rdata_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 11.183ns (logic 1.734ns (15.504%) route 9.449ns (84.496%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.932ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K3 0.000 0.000 r dip_sw[13] (IN) net (fo=0) 0.000 0.000 dip_sw[13] K3 IBUF (Prop_ibuf_I_O) 1.486 1.486 r dip_sw_IBUF[13]_inst/O net (fo=1, routed) 8.863 10.349 u_confreg/dip_sw_IBUF[13] SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.124 10.473 r u_confreg/s_rdata[13]_i_4/O net (fo=1, routed) 0.586 11.059 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.124 11.183 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O net (fo=1, routed) 0.000 11.183 u_confreg/u_int_ctrl_n_18 SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.896 -1.932 u_confreg/sys_clk SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/C Slack: inf Source: dip_sw[1] (input port) Destination: u_confreg/s_rdata_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 11.155ns (logic 1.746ns (15.651%) route 9.409ns (84.349%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J3 0.000 0.000 r dip_sw[1] (IN) net (fo=0) 0.000 0.000 dip_sw[1] J3 IBUF (Prop_ibuf_I_O) 1.498 1.498 r dip_sw_IBUF[1]_inst/O net (fo=1, routed) 8.467 9.965 u_confreg/dip_sw_IBUF[1] SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.124 10.089 r u_confreg/s_rdata[1]_i_4/O net (fo=1, routed) 0.942 11.031 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 11.155 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O net (fo=1, routed) 0.000 11.155 u_confreg/u_int_ctrl_n_30 SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/C Slack: inf Source: dip_sw[11] (input port) Destination: u_confreg/s_rdata_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 11.052ns (logic 1.719ns (15.556%) route 9.333ns (84.444%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.937ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.937ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L7 0.000 0.000 r dip_sw[11] (IN) net (fo=0) 0.000 0.000 dip_sw[11] L7 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[11]_inst/O net (fo=1, routed) 8.677 10.148 u_confreg/dip_sw_IBUF[11] SLICE_X4Y82 LUT5 (Prop_lut5_I4_O) 0.124 10.272 r u_confreg/s_rdata[11]_i_4/O net (fo=1, routed) 0.656 10.928 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.124 11.052 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O net (fo=1, routed) 0.000 11.052 u_confreg/u_int_ctrl_n_20 SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.891 -1.937 u_confreg/sys_clk SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/C Slack: inf Source: dip_sw[25] (input port) Destination: u_confreg/s_rdata_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.711ns (logic 1.737ns (16.220%) route 8.974ns (83.780%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R3 0.000 0.000 r dip_sw[25] (IN) net (fo=0) 0.000 0.000 dip_sw[25] R3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[25]_inst/O net (fo=1, routed) 8.245 9.734 u_confreg/dip_sw_IBUF[25] SLICE_X9Y88 LUT5 (Prop_lut5_I4_O) 0.124 9.858 r u_confreg/s_rdata[25]_i_4/O net (fo=1, routed) 0.729 10.587 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 10.711 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O net (fo=1, routed) 0.000 10.711 u_confreg/u_int_ctrl_n_6 SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/C Slack: inf Source: dip_sw[19] (input port) Destination: u_confreg/s_rdata_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.426ns (logic 1.726ns (16.557%) route 8.700ns (83.443%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.934ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L4 0.000 0.000 r dip_sw[19] (IN) net (fo=0) 0.000 0.000 dip_sw[19] L4 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[19]_inst/O net (fo=1, routed) 8.546 10.024 u_confreg/dip_sw_IBUF[19] SLICE_X7Y86 LUT5 (Prop_lut5_I4_O) 0.124 10.148 r u_confreg/s_rdata[19]_i_4/O net (fo=1, routed) 0.154 10.302 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 SLICE_X7Y86 LUT6 (Prop_lut6_I4_O) 0.124 10.426 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O net (fo=1, routed) 0.000 10.426 u_confreg/u_int_ctrl_n_12 SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.894 -1.934 u_confreg/sys_clk SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/C Slack: inf Source: touch_btn[2] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.138ns (logic 1.487ns (14.666%) route 8.651ns (85.334%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -1.936ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.936ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P3 0.000 0.000 r touch_btn[2] (IN) net (fo=0) 0.000 0.000 touch_btn[2] P3 IBUF (Prop_ibuf_I_O) 1.487 1.487 r touch_btn_IBUF[2]_inst/O net (fo=1, routed) 8.651 10.138 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.892 -1.936 u_confreg/u_int_ctrl/sys_clk SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C Slack: inf Source: dip_sw[9] (input port) Destination: u_confreg/s_rdata_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.432ns (logic 1.718ns (20.372%) route 6.714ns (79.628%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.938ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.938ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N7 0.000 0.000 r dip_sw[9] (IN) net (fo=0) 0.000 0.000 dip_sw[9] N7 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[9]_inst/O net (fo=1, routed) 6.067 7.537 u_confreg/dip_sw_IBUF[9] SLICE_X1Y80 LUT5 (Prop_lut5_I4_O) 0.124 7.661 r u_confreg/s_rdata[9]_i_4/O net (fo=1, routed) 0.647 8.308 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 SLICE_X1Y80 LUT6 (Prop_lut6_I4_O) 0.124 8.432 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O net (fo=1, routed) 0.000 8.432 u_confreg/u_int_ctrl_n_22 SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.890 -1.938 u_confreg/sys_clk SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/C Slack: inf Source: dip_sw[4] (input port) Destination: u_confreg/s_rdata_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.408ns (logic 1.736ns (20.649%) route 6.672ns (79.351%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.934ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P4 0.000 0.000 r dip_sw[4] (IN) net (fo=0) 0.000 0.000 dip_sw[4] P4 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[4]_inst/O net (fo=1, routed) 6.006 7.495 u_confreg/dip_sw_IBUF[4] SLICE_X2Y85 LUT5 (Prop_lut5_I4_O) 0.124 7.619 r u_confreg/s_rdata[4]_i_4/O net (fo=1, routed) 0.666 8.284 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 SLICE_X2Y83 LUT6 (Prop_lut6_I4_O) 0.124 8.408 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O net (fo=1, routed) 0.000 8.408 u_confreg/u_int_ctrl_n_27 SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.894 -1.934 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/C Slack: inf Source: dip_sw[10] (input port) Destination: u_confreg/s_rdata_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.284ns (logic 1.720ns (20.765%) route 6.564ns (79.235%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M7 0.000 0.000 r dip_sw[10] (IN) net (fo=0) 0.000 0.000 dip_sw[10] M7 IBUF (Prop_ibuf_I_O) 1.472 1.472 r dip_sw_IBUF[10]_inst/O net (fo=1, routed) 6.100 7.572 u_confreg/dip_sw_IBUF[10] SLICE_X8Y80 LUT5 (Prop_lut5_I4_O) 0.124 7.696 r u_confreg/s_rdata[10]_i_4/O net (fo=1, routed) 0.464 8.160 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 8.284 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O net (fo=1, routed) 0.000 8.284 u_confreg/u_int_ctrl_n_21 SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/C Slack: inf Source: dip_sw[23] (input port) Destination: u_confreg/s_rdata_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.265ns (logic 1.766ns (21.372%) route 6.499ns (78.628%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N1 0.000 0.000 r dip_sw[23] (IN) net (fo=0) 0.000 0.000 dip_sw[23] N1 IBUF (Prop_ibuf_I_O) 1.518 1.518 r dip_sw_IBUF[23]_inst/O net (fo=1, routed) 5.411 6.929 u_confreg/dip_sw_IBUF[23] SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.124 7.053 r u_confreg/s_rdata[23]_i_4/O net (fo=1, routed) 1.088 8.141 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 8.265 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O net (fo=1, routed) 0.000 8.265 u_confreg/u_int_ctrl_n_8 SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/C Slack: inf Source: dip_sw[5] (input port) Destination: u_confreg/s_rdata_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.233ns (logic 1.718ns (20.872%) route 6.515ns (79.128%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L5 0.000 0.000 r dip_sw[5] (IN) net (fo=0) 0.000 0.000 dip_sw[5] L5 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[5]_inst/O net (fo=1, routed) 5.514 6.985 u_confreg/dip_sw_IBUF[5] SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.124 7.109 r u_confreg/s_rdata[5]_i_4/O net (fo=1, routed) 1.000 8.109 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 8.233 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O net (fo=1, routed) 0.000 8.233 u_confreg/u_int_ctrl_n_26 SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/C Slack: inf Source: dip_sw[26] (input port) Destination: u_confreg/s_rdata_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.161ns (logic 1.757ns (21.535%) route 6.403ns (78.465%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T4 0.000 0.000 r dip_sw[26] (IN) net (fo=0) 0.000 0.000 dip_sw[26] T4 IBUF (Prop_ibuf_I_O) 1.509 1.509 r dip_sw_IBUF[26]_inst/O net (fo=1, routed) 5.313 6.823 u_confreg/dip_sw_IBUF[26] SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.947 r u_confreg/s_rdata[26]_i_4/O net (fo=1, routed) 1.090 8.037 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.124 8.161 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O net (fo=1, routed) 0.000 8.161 u_confreg/u_int_ctrl_n_5 SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.817 -2.011 u_confreg/sys_clk SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/C Slack: inf Source: dip_sw[17] (input port) Destination: u_confreg/s_rdata_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.117ns (logic 1.752ns (21.585%) route 6.365ns (78.415%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.931ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K1 0.000 0.000 r dip_sw[17] (IN) net (fo=0) 0.000 0.000 dip_sw[17] K1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[17]_inst/O net (fo=1, routed) 5.516 7.020 u_confreg/dip_sw_IBUF[17] SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.124 7.144 r u_confreg/s_rdata[17]_i_4/O net (fo=1, routed) 0.849 7.993 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.124 8.117 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O net (fo=1, routed) 0.000 8.117 u_confreg/u_int_ctrl_n_14 SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/C Slack: inf Source: dip_sw[2] (input port) Destination: u_confreg/s_rdata_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.080ns (logic 1.743ns (21.573%) route 6.337ns (78.427%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.017ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M2 0.000 0.000 r dip_sw[2] (IN) net (fo=0) 0.000 0.000 dip_sw[2] M2 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[2]_inst/O net (fo=1, routed) 5.346 6.841 u_confreg/dip_sw_IBUF[2] SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.965 r u_confreg/s_rdata[2]_i_4/O net (fo=1, routed) 0.991 7.956 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 8.080 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O net (fo=1, routed) 0.000 8.080 u_confreg/u_int_ctrl_n_29 SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/C Slack: inf Source: dip_sw[6] (input port) Destination: u_confreg/s_rdata_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.077ns (logic 1.736ns (21.494%) route 6.341ns (78.506%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.936ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.936ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L3 0.000 0.000 r dip_sw[6] (IN) net (fo=0) 0.000 0.000 dip_sw[6] L3 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[6]_inst/O net (fo=1, routed) 5.394 6.882 u_confreg/dip_sw_IBUF[6] SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.124 7.006 r u_confreg/s_rdata[6]_i_4/O net (fo=1, routed) 0.947 7.953 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.124 8.077 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O net (fo=1, routed) 0.000 8.077 u_confreg/u_int_ctrl_n_25 SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.892 -1.936 u_confreg/sys_clk SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/C Slack: inf Source: dip_sw[14] (input port) Destination: u_confreg/s_rdata_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.038ns (logic 1.763ns (21.934%) route 6.275ns (78.066%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.931ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J1 0.000 0.000 r dip_sw[14] (IN) net (fo=0) 0.000 0.000 dip_sw[14] J1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r dip_sw_IBUF[14]_inst/O net (fo=1, routed) 5.331 6.846 u_confreg/dip_sw_IBUF[14] SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.970 r u_confreg/s_rdata[14]_i_4/O net (fo=1, routed) 0.944 7.914 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 8.038 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O net (fo=1, routed) 0.000 8.038 u_confreg/u_int_ctrl_n_17 SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/C Slack: inf Source: dip_sw[15] (input port) Destination: u_confreg/s_rdata_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.951ns (logic 1.742ns (21.911%) route 6.209ns (78.089%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.931ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L2 0.000 0.000 r dip_sw[15] (IN) net (fo=0) 0.000 0.000 dip_sw[15] L2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[15]_inst/O net (fo=1, routed) 5.453 6.948 u_confreg/dip_sw_IBUF[15] SLICE_X1Y95 LUT5 (Prop_lut5_I4_O) 0.124 7.072 r u_confreg/s_rdata[15]_i_4/O net (fo=1, routed) 0.755 7.827 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.951 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O net (fo=1, routed) 0.000 7.951 u_confreg/u_int_ctrl_n_16 SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/C Slack: inf Source: dip_sw[0] (input port) Destination: u_confreg/s_rdata_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.807ns (logic 1.743ns (22.326%) route 6.064ns (77.674%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.937ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.937ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T3 0.000 0.000 r dip_sw[0] (IN) net (fo=0) 0.000 0.000 dip_sw[0] T3 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[0]_inst/O net (fo=1, routed) 5.166 6.661 u_confreg/dip_sw_IBUF[0] SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.785 r u_confreg/s_rdata[0]_i_4/O net (fo=1, routed) 0.898 7.683 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.124 7.807 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O net (fo=1, routed) 0.000 7.807 u_confreg/u_int_ctrl_n_31 SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.891 -1.937 u_confreg/sys_clk SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/C Slack: inf Source: dip_sw[3] (input port) Destination: u_confreg/s_rdata_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.770ns (logic 1.752ns (22.553%) route 6.018ns (77.447%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.940ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.940ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P1 0.000 0.000 r dip_sw[3] (IN) net (fo=0) 0.000 0.000 dip_sw[3] P1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[3]_inst/O net (fo=1, routed) 5.171 6.676 u_confreg/dip_sw_IBUF[3] SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.800 r u_confreg/s_rdata[3]_i_4/O net (fo=1, routed) 0.846 7.646 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.124 7.770 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O net (fo=1, routed) 0.000 7.770 u_confreg/u_int_ctrl_n_28 SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.888 -1.940 u_confreg/sys_clk SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/C Slack: inf Source: dip_sw[21] (input port) Destination: u_confreg/s_rdata_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.691ns (logic 1.736ns (22.574%) route 5.955ns (77.426%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N2 0.000 0.000 r dip_sw[21] (IN) net (fo=0) 0.000 0.000 dip_sw[21] N2 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[21]_inst/O net (fo=1, routed) 5.069 6.557 u_confreg/dip_sw_IBUF[21] SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.681 r u_confreg/s_rdata[21]_i_4/O net (fo=1, routed) 0.886 7.567 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.691 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O net (fo=1, routed) 0.000 7.691 u_confreg/u_int_ctrl_n_10 SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/C Slack: inf Source: dip_sw[16] (input port) Destination: u_confreg/s_rdata_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.536ns (logic 1.748ns (23.196%) route 5.788ns (76.804%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.931ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K2 0.000 0.000 r dip_sw[16] (IN) net (fo=0) 0.000 0.000 dip_sw[16] K2 IBUF (Prop_ibuf_I_O) 1.500 1.500 r dip_sw_IBUF[16]_inst/O net (fo=1, routed) 5.492 6.993 u_confreg/dip_sw_IBUF[16] SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.124 7.117 r u_confreg/s_rdata[16]_i_4/O net (fo=1, routed) 0.296 7.412 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.536 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O net (fo=1, routed) 0.000 7.536 u_confreg/u_int_ctrl_n_15 SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/C Slack: inf Source: dip_sw[24] (input port) Destination: u_confreg/s_rdata_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.500ns (logic 1.714ns (22.860%) route 5.785ns (77.140%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.931ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P5 0.000 0.000 r dip_sw[24] (IN) net (fo=0) 0.000 0.000 dip_sw[24] P5 IBUF (Prop_ibuf_I_O) 1.466 1.466 r dip_sw_IBUF[24]_inst/O net (fo=1, routed) 4.979 6.445 u_confreg/dip_sw_IBUF[24] SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.569 r u_confreg/s_rdata[24]_i_4/O net (fo=1, routed) 0.806 7.376 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.500 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O net (fo=1, routed) 0.000 7.500 u_confreg/u_int_ctrl_n_7 SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/C Slack: inf Source: dip_sw[18] (input port) Destination: u_confreg/s_rdata_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.469ns (logic 1.737ns (23.257%) route 5.732ns (76.743%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N3 0.000 0.000 r dip_sw[18] (IN) net (fo=0) 0.000 0.000 dip_sw[18] N3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[18]_inst/O net (fo=1, routed) 5.052 6.541 u_confreg/dip_sw_IBUF[18] SLICE_X8Y87 LUT5 (Prop_lut5_I4_O) 0.124 6.665 r u_confreg/s_rdata[18]_i_4/O net (fo=1, routed) 0.680 7.345 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.124 7.469 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O net (fo=1, routed) 0.000 7.469 u_confreg/u_int_ctrl_n_13 SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.817 -2.011 u_confreg/sys_clk SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/C Slack: inf Source: dip_sw[7] (input port) Destination: u_confreg/s_rdata_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.415ns (logic 1.719ns (23.186%) route 5.696ns (76.814%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.933ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N6 0.000 0.000 r dip_sw[7] (IN) net (fo=0) 0.000 0.000 dip_sw[7] N6 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[7]_inst/O net (fo=1, routed) 5.542 7.013 u_confreg/dip_sw_IBUF[7] SLICE_X1Y84 LUT5 (Prop_lut5_I4_O) 0.124 7.137 r u_confreg/s_rdata[7]_i_4/O net (fo=1, routed) 0.154 7.291 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 SLICE_X1Y84 LUT6 (Prop_lut6_I4_O) 0.124 7.415 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O net (fo=1, routed) 0.000 7.415 u_confreg/u_int_ctrl_n_24 SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.895 -1.933 u_confreg/sys_clk SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/C Slack: inf Source: dip_sw[12] (input port) Destination: u_confreg/s_rdata_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.331ns (logic 1.717ns (23.423%) route 5.614ns (76.577%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.936ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.936ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M5 0.000 0.000 r dip_sw[12] (IN) net (fo=0) 0.000 0.000 dip_sw[12] M5 IBUF (Prop_ibuf_I_O) 1.469 1.469 r dip_sw_IBUF[12]_inst/O net (fo=1, routed) 5.177 6.646 u_confreg/dip_sw_IBUF[12] SLICE_X5Y86 LUT5 (Prop_lut5_I4_O) 0.124 6.770 r u_confreg/s_rdata[12]_i_4/O net (fo=1, routed) 0.437 7.207 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.124 7.331 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O net (fo=1, routed) 0.000 7.331 u_confreg/u_int_ctrl_n_19 SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.892 -1.936 u_confreg/sys_clk SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/C Slack: inf Source: dip_sw[30] (input port) Destination: u_confreg/s_rdata_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.316ns (logic 1.707ns (23.334%) route 5.609ns (76.666%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.930ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.930ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R6 0.000 0.000 r dip_sw[30] (IN) net (fo=0) 0.000 0.000 dip_sw[30] R6 IBUF (Prop_ibuf_I_O) 1.459 1.459 r dip_sw_IBUF[30]_inst/O net (fo=1, routed) 4.515 5.975 u_confreg/dip_sw_IBUF[30] SLICE_X2Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.099 r u_confreg/s_rdata[30]_i_4/O net (fo=1, routed) 1.093 7.192 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.316 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O net (fo=1, routed) 0.000 7.316 u_confreg/u_int_ctrl_n_1 SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.898 -1.930 u_confreg/sys_clk SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/C Slack: inf Source: dip_sw[29] (input port) Destination: u_confreg/s_rdata_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.273ns (logic 1.726ns (23.732%) route 5.547ns (76.268%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.930ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.930ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T5 0.000 0.000 r dip_sw[29] (IN) net (fo=0) 0.000 0.000 dip_sw[29] T5 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[29]_inst/O net (fo=1, routed) 4.537 6.015 u_confreg/dip_sw_IBUF[29] SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.124 6.139 r u_confreg/s_rdata[29]_i_4/O net (fo=1, routed) 1.010 7.149 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.273 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O net (fo=1, routed) 0.000 7.273 u_confreg/u_int_ctrl_n_2 SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.898 -1.930 u_confreg/sys_clk SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/C Slack: inf Source: touch_btn[3] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.267ns (logic 1.513ns (20.816%) route 5.755ns (79.184%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -1.938ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.938ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- U2 0.000 0.000 r touch_btn[3] (IN) net (fo=0) 0.000 0.000 touch_btn[3] U2 IBUF (Prop_ibuf_I_O) 1.513 1.513 r touch_btn_IBUF[3]_inst/O net (fo=1, routed) 5.755 7.267 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.890 -1.938 u_confreg/u_int_ctrl/sys_clk SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C Slack: inf Source: touch_btn[1] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.239ns (logic 1.515ns (20.930%) route 5.724ns (79.070%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -2.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M1 0.000 0.000 r touch_btn[1] (IN) net (fo=0) 0.000 0.000 touch_btn[1] M1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r touch_btn_IBUF[1]_inst/O net (fo=1, routed) 5.724 7.239 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.819 -2.009 u_confreg/u_int_ctrl/sys_clk SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C Slack: inf Source: dip_sw[28] (input port) Destination: u_confreg/s_rdata_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.116ns (logic 1.716ns (24.110%) route 5.400ns (75.890%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.931ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R5 0.000 0.000 r dip_sw[28] (IN) net (fo=0) 0.000 0.000 dip_sw[28] R5 IBUF (Prop_ibuf_I_O) 1.468 1.468 r dip_sw_IBUF[28]_inst/O net (fo=1, routed) 4.960 6.427 u_confreg/dip_sw_IBUF[28] SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.551 r u_confreg/s_rdata[28]_i_4/O net (fo=1, routed) 0.440 6.992 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.116 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O net (fo=1, routed) 0.000 7.116 u_confreg/u_int_ctrl_n_3 SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/C Slack: inf Source: dip_sw[22] (input port) Destination: u_confreg/s_rdata_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.094ns (logic 1.710ns (24.108%) route 5.384ns (75.892%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.932ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P6 0.000 0.000 r dip_sw[22] (IN) net (fo=0) 0.000 0.000 dip_sw[22] P6 IBUF (Prop_ibuf_I_O) 1.462 1.462 r dip_sw_IBUF[22]_inst/O net (fo=1, routed) 4.542 6.004 u_confreg/dip_sw_IBUF[22] SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.124 6.128 r u_confreg/s_rdata[22]_i_4/O net (fo=1, routed) 0.842 6.970 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 SLICE_X4Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.094 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O net (fo=1, routed) 0.000 7.094 u_confreg/u_int_ctrl_n_9 SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.896 -1.932 u_confreg/sys_clk SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.945ns (logic 1.963ns (28.269%) route 4.982ns (71.731%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) Clock Path Skew: -1.929ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 3.916 5.391 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.117 5.508 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.683 6.191 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X2Y60 LUT5 (Prop_lut5_I1_O) 0.372 6.563 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O net (fo=1, routed) 0.382 6.945 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.899 -1.929 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C Slack: inf Source: dip_sw[27] (input port) Destination: u_confreg/s_rdata_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.892ns (logic 1.753ns (25.432%) route 5.139ns (74.568%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R1 0.000 0.000 r dip_sw[27] (IN) net (fo=0) 0.000 0.000 dip_sw[27] R1 IBUF (Prop_ibuf_I_O) 1.505 1.505 r dip_sw_IBUF[27]_inst/O net (fo=1, routed) 4.238 5.743 u_confreg/dip_sw_IBUF[27] SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.124 5.867 r u_confreg/s_rdata[27]_i_4/O net (fo=1, routed) 0.902 6.768 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 6.892 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O net (fo=1, routed) 0.000 6.892 u_confreg/u_int_ctrl_n_4 SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/C Slack: inf Source: dip_sw[31] (input port) Destination: u_confreg/s_rdata_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.857ns (logic 1.742ns (25.399%) route 5.116ns (74.601%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.932ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R2 0.000 0.000 r dip_sw[31] (IN) net (fo=0) 0.000 0.000 dip_sw[31] R2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[31]_inst/O net (fo=1, routed) 4.636 6.130 u_confreg/dip_sw_IBUF[31] SLICE_X2Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.254 r u_confreg/s_rdata[31]_i_6/O net (fo=1, routed) 0.480 6.733 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.124 6.857 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O net (fo=1, routed) 0.000 6.857 u_confreg/u_int_ctrl_n_0 SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.896 -1.932 u_confreg/sys_clk SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.182ns (logic 1.939ns (31.371%) route 4.243ns (68.629%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) Clock Path Skew: -1.930ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.930ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 3.916 5.391 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.117 5.508 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.326 5.834 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X2Y61 LUT6 (Prop_lut6_I2_O) 0.348 6.182 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O net (fo=1, routed) 0.000 6.182 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.898 -1.930 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.135ns (logic 1.598ns (26.054%) route 4.537ns (73.946%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -1.929ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 r UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 3.916 5.391 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X2Y60 LUT5 (Prop_lut5_I0_O) 0.124 5.515 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O net (fo=1, routed) 0.620 6.135 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.899 -1.929 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C Slack: inf Source: touch_btn[0] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.929ns (logic 1.499ns (25.283%) route 4.430ns (74.717%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -2.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T2 0.000 0.000 r touch_btn[0] (IN) net (fo=0) 0.000 0.000 touch_btn[0] T2 IBUF (Prop_ibuf_I_O) 1.499 1.499 r touch_btn_IBUF[0]_inst/O net (fo=1, routed) 4.430 5.929 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.819 -2.009 u_confreg/u_int_ctrl/sys_clk SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C Slack: inf Source: UART_RX (input port) Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.784ns (logic 1.590ns (27.483%) route 4.194ns (72.517%)) Logic Levels: 2 (IBUF=1 LUT4=1) Clock Path Skew: -1.930ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.930ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J20 0.000 0.000 r UART_RX (INOUT) net (fo=1, unset) 0.000 0.000 UART_RX_IOBUF_inst/IO J20 IBUF (Prop_ibuf_I_O) 1.466 1.466 r UART_RX_IOBUF_inst/IBUF/O net (fo=1, routed) 4.194 5.660 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_RX_IBUF SLICE_X1Y61 LUT4 (Prop_lut4_I3_O) 0.124 5.784 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O net (fo=1, routed) 0.000 5.784 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.898 -1.930 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.395ns (logic 1.598ns (29.628%) route 3.796ns (70.372%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -1.932ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 3.796 5.271 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF SLICE_X4Y61 LUT5 (Prop_lut5_I2_O) 0.124 5.395 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O net (fo=1, routed) 0.000 5.395 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.896 -1.932 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED (internal pin) Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 4.648ns (logic 0.124ns (2.668%) route 4.524ns (97.332%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED net (fo=1, routed) 3.378 3.378 pll_clk.u_rst_sys/locked SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.124 3.502 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 1.146 4.648 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.736 -2.092 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED (internal pin) Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 4.648ns (logic 0.124ns (2.668%) route 4.524ns (97.332%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED net (fo=1, routed) 3.378 3.378 pll_clk.u_rst_sys/locked SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.124 3.502 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 1.146 4.648 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10004, routed) 1.736 -2.092 pll_clk.u_rst_sys/sys_clk SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C