/** * user-sample - CIC-IEC 2026 Stage 3 Evaluation Program * * (ULTIMATE PERFORMANCE DMA + PING-PONG BUFFER ARCHITECTURE v2) * * Optimizations over v1: * 1. Pre-fire DMA Ch0 load at loop tail → fully overlaps with IP compute * 2. Inlined wait loops → zero function-call overhead in hot path * 3. Inlined DMA start → skips redundant STATUS_BUSY_BIT check * 4. XOR bank toggle → avoids g%2 recomputation per iteration */ #include #include /* ─── UART 16550 direct access (bypasses slow printf/picolibc) ──────── */ #define UART_THR (*(volatile unsigned char *)0xbf000000) #define UART_LSR (*(volatile unsigned char *)0xbf000005) #define LSR_THRE 0x20 static inline void uart_tx(unsigned char c) { while (!(UART_LSR & LSR_THRE)) {} UART_THR = c; } static void uart_puts(const char *s) { while (*s) uart_tx(*s++); } static void uart_puthex(unsigned int val) { int i; for (i = 28; i >= 0; i -= 4) { unsigned char nibble = (val >> i) & 0xF; uart_tx(nibble < 10 ? '0' + nibble : 'a' + nibble - 10); } } static void uart_putdec(unsigned int val) { char buf[10]; int i = 0; if (val == 0) { uart_tx('0'); return; } while (val != 0) { buf[i++] = (char)('0' + (val % 10)); val /= 10; } while (i > 0) { uart_tx((unsigned char)buf[--i]); } } /* ─── Configurable group count (default 5000) ──────────────────────── */ #ifndef MATMUL_GROUP_NUM #define MATMUL_GROUP_NUM 5000 #endif /* ─── BSP globals ─────────────────────────────────────────────────── */ unsigned long UART_BASE = 0xbf000000; unsigned long CONFREG_TIMER_BASE = 0xbf20f100; unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L; unsigned long CORE_CLOCKS_PER_SEC = 33000000L; /* ─── Memory layout ────────────────────────────────────────────────── */ #define EXTRAM_BASE_PHYS 0x1c400000 #define EXTRAM_BASE_UNCACHED (0xA0000000 | (EXTRAM_BASE_PHYS & 0x1FFFFFFF)) #define SRC_BASE_WORDS 0 #define DST_BASE_WORDS (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32) #define RESULT_WORDS (MATMUL_GROUP_NUM * 48) /* ExtRAM Physical Addresses for DMA */ #define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4) + (g) * 128) #define EXTRAM_PHYS_C(g) (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4) + (g) * 192) /* ─── MATMUL IP registers (Ping-Pong Memory Map) ──────────────────── */ #define MATMUL_BASE_PHYS 0x1f500000 #define MATMUL_BASE_UNCACHED 0xbf500000 #define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000) #define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004) #define MATMUL_BASE_PHYS_FOR_DMA MATMUL_BASE_PHYS #define CTRL_START_B0 0x1 #define CTRL_START_B1 0x2 #define STATUS_DONE 0x2 #define STATUS_ERROR 0x4 #define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010) /* ─── Pre-computed DMA burst control word ──────────────────────────── */ #define DMA_CTRL_VAL (CTRL_BURST_SIZE(2) | CTRL_BURST_LEN(63) | CTRL_START_BIT) #define MATMUL_EP_ID 0 /* ═══════════════════════════════════════════════════════════════════ */ int main(void) { if (MATMUL_GROUP_NUM <= 0) return 0; /* ── Hot-path local volatile pointers (one-time addr calc) ──────── */ volatile unsigned int *mat_crc = (volatile unsigned int *)MATMUL_CRC; volatile dma_seq_regs_t *seq = DMA_SEQ; unsigned int crc; unsigned int cycle_start, cycle_end, cycles, time_us; /* ── Start marker (must be first output) ──────────────────── */ uart_puts("MATMUL_START\r\n"); cycle_start = get_clock_count(); seq->STATUS = SEQ_DONE_BIT; seq->SRC_BASE = EXTRAM_PHYS_AB(0); seq->DST_BASE = EXTRAM_PHYS_C(0); seq->GROUPS = MATMUL_GROUP_NUM; seq->MAT_BASE = MATMUL_BASE_PHYS_FOR_DMA; seq->SRC_STRIDE = 128; seq->DST_STRIDE = 192; seq->CTRL = SEQ_START_BIT; while (!(seq->STATUS & SEQ_DONE_BIT)) {} seq->STATUS = SEQ_DONE_BIT; cycle_end = get_clock_count(); cycles = cycle_end - cycle_start; time_us = cycles / (CORE_CLOCKS_PER_SEC / 1000000UL); /* ── Read hardware CRC32 ──────────────────────────────────── */ crc = *mat_crc; uart_puts("MATMUL_CRC32="); uart_puthex(crc); uart_puts("\r\nMATMUL_CYCLES="); uart_putdec(cycles); uart_puts("\r\nMATMUL_TIME_US="); uart_putdec(time_us); uart_puts("\r\nMATMUL_DONE\r\n"); return 0; }