# Pipelined Multiplier for Matmul IP

## Goal

Replace 4× shift_add_mult (32 cycle/op) with 4× 3-stage pipelined multipliers (1 result/cycle after fill), reducing compute from 420 cycle/group to ~15 cycle/group.

## Requirements

1. **Multiplier**: 32×32→64, 3-stage pipeline, LUT-only (no DSP)
2. **FSM**: simplified from 4-state (C_IDLE/C_CALC/C_WAIT_MULT/C_ACCUM) to 2-state (C_IDLE/C_RUN)
3. **Pipeline matching**: 3-entry shift register for calc_idx/cur_bank delay line
4. **Accumulation**: unchanged (4-way sum registered)
5. **Interface**: same ports as shift_add_mult (clk, rstn, start, a, b, p, done) for drop-in replacement

## Acceptance Criteria

- [ ] Simulation: CRC32 matches (10 groups)
- [ ] Lint clean
- [ ] Compile passes
- [ ] No DSP used
- [ ] WNS ≥ 0 (timing passes for sys_clk=50MHz)
- [ ] Expected time improvement: compute ~420 cycle → ~15 cycle

## Technical Approach

### Multiplier Design

```verilog
(* use_dsp = "no" *)
module pipelined_mult (
    input clk, rstn, start,
    input [31:0] a, b,
    output [63:0] p,
    output done
);
    // 3-stage: reg(a,b) → compute product → output
endmodule
```

### FSM Reduction

```
Before: C_IDLE → C_CALC(1) → C_WAIT_MULT(32) → C_ACCUM(1)
                          ←──────── 12 rounds ────────→  = 420 cycles

After:  C_IDLE → C_RUN(12 + 3 pipe delay) → C_IDLE
         Issue 4 mults/cycle for 12 cycles
         Results arrive 3 cycles later → accumulate
         Total: 12 + 3 + 1 = 16 cycles
```

## Out of Scope

- More than 4 multipliers
- Changes to DMA, CRC32, interrupts
- FFT integration