# Report evidence

Generated logs and Vivado reports used by `system_design_report.tex` live here:

- `soc/`: UART output from SoC simulations
- `build/`: software build logs for the five selected examples
- `vivado/`: timing, utilization, CDC, DRC, route and power reports
- `board/`: official matmul evaluation plus FFT/FFT-DMA board UART logs

Run `../tools/run_report_tests.sh refresh` after replacing evidence. Large generated
artifacts such as `.vcd`, `.wdb`, `.jou`, `.str`, implementation checkpoints and
bitstreams do not belong in Git. SoC VCD files may be generated here temporarily with
`SAVE_VCD=1`; archive them separately when they are needed as report evidence.