Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 | Date : Wed Jul 8 02:57:57 2026 | Host : fedora running 64-bit unknown | Command : report_timing -delay_type max -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_withdsp/timing_setup_paths.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Report Slack (MET) : 0.424ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.252ns (logic 7.003ns (45.917%) route 8.249ns (54.083%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.455 7.318 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X1Y124 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 SLICE_X1Y124 LUT6 (Prop_lut6_I5_O) 0.124 7.442 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.937 9.379 base_ram_be_n_OBUF[3] K25 r base_ram_be_n_OBUF[3]_inst/I K25 OBUF (Prop_obuf_I_O) 3.551 12.930 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.930 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.930 ------------------------------------------------------------------- slack 0.424 Slack (MET) : 0.424ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.252ns (logic 7.003ns (45.917%) route 8.249ns (54.083%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.455 7.318 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X1Y124 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 SLICE_X1Y124 LUT6 (Prop_lut6_I5_O) 0.124 7.442 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.937 9.379 base_ram_be_n_OBUF[3] K25 r base_ram_be_n_OBUF[3]_inst/I K25 OBUF (Prop_obuf_I_O) 3.551 12.930 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.930 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.930 ------------------------------------------------------------------- slack 0.424 Slack (MET) : 0.424ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.252ns (logic 7.003ns (45.917%) route 8.249ns (54.083%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.455 7.318 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X1Y124 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 SLICE_X1Y124 LUT6 (Prop_lut6_I5_O) 0.124 7.442 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.937 9.379 base_ram_be_n_OBUF[3] K25 r base_ram_be_n_OBUF[3]_inst/I K25 OBUF (Prop_obuf_I_O) 3.551 12.930 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.930 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.930 ------------------------------------------------------------------- slack 0.424 Slack (MET) : 0.424ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.252ns (logic 7.003ns (45.917%) route 8.249ns (54.083%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.455 7.318 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X1Y124 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 SLICE_X1Y124 LUT6 (Prop_lut6_I5_O) 0.124 7.442 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.937 9.379 base_ram_be_n_OBUF[3] K25 r base_ram_be_n_OBUF[3]_inst/I K25 OBUF (Prop_obuf_I_O) 3.551 12.930 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.930 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.930 ------------------------------------------------------------------- slack 0.424 Slack (MET) : 0.424ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.252ns (logic 7.003ns (45.917%) route 8.249ns (54.083%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.455 7.318 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X1Y124 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 SLICE_X1Y124 LUT6 (Prop_lut6_I5_O) 0.124 7.442 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.937 9.379 base_ram_be_n_OBUF[3] K25 r base_ram_be_n_OBUF[3]_inst/I K25 OBUF (Prop_obuf_I_O) 3.551 12.930 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.930 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.930 ------------------------------------------------------------------- slack 0.424 Slack (MET) : 0.424ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.252ns (logic 7.003ns (45.917%) route 8.249ns (54.083%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.455 7.318 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X1Y124 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 SLICE_X1Y124 LUT6 (Prop_lut6_I5_O) 0.124 7.442 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.937 9.379 base_ram_be_n_OBUF[3] K25 r base_ram_be_n_OBUF[3]_inst/I K25 OBUF (Prop_obuf_I_O) 3.551 12.930 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.930 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.930 ------------------------------------------------------------------- slack 0.424 Slack (MET) : 0.424ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.252ns (logic 7.003ns (45.917%) route 8.249ns (54.083%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.455 7.318 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X1Y124 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 SLICE_X1Y124 LUT6 (Prop_lut6_I5_O) 0.124 7.442 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.937 9.379 base_ram_be_n_OBUF[3] K25 r base_ram_be_n_OBUF[3]_inst/I K25 OBUF (Prop_obuf_I_O) 3.551 12.930 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.930 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.930 ------------------------------------------------------------------- slack 0.424 Slack (MET) : 0.424ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.252ns (logic 7.003ns (45.917%) route 8.249ns (54.083%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.455 7.318 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X1Y124 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 SLICE_X1Y124 LUT6 (Prop_lut6_I5_O) 0.124 7.442 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.937 9.379 base_ram_be_n_OBUF[3] K25 r base_ram_be_n_OBUF[3]_inst/I K25 OBUF (Prop_obuf_I_O) 3.551 12.930 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.930 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.930 ------------------------------------------------------------------- slack 0.424 Slack (MET) : 0.424ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.252ns (logic 7.003ns (45.917%) route 8.249ns (54.083%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.455 7.318 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X1Y124 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 SLICE_X1Y124 LUT6 (Prop_lut6_I5_O) 0.124 7.442 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.937 9.379 base_ram_be_n_OBUF[3] K25 r base_ram_be_n_OBUF[3]_inst/I K25 OBUF (Prop_obuf_I_O) 3.551 12.930 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.930 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.930 ------------------------------------------------------------------- slack 0.424 Slack (MET) : 0.424ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.252ns (logic 7.003ns (45.917%) route 8.249ns (54.083%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.455 7.318 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X1Y124 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 SLICE_X1Y124 LUT6 (Prop_lut6_I5_O) 0.124 7.442 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.937 9.379 base_ram_be_n_OBUF[3] K25 r base_ram_be_n_OBUF[3]_inst/I K25 OBUF (Prop_obuf_I_O) 3.551 12.930 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.930 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.930 ------------------------------------------------------------------- slack 0.424 Slack (MET) : 0.569ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.107ns (logic 7.010ns (46.402%) route 8.097ns (53.598%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.640 9.227 ext_ram_data_IOBUF[24]_inst/T AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 12.785 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.785 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.785 ------------------------------------------------------------------- slack 0.569 Slack (MET) : 0.569ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.107ns (logic 7.010ns (46.402%) route 8.097ns (53.598%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.640 9.227 ext_ram_data_IOBUF[24]_inst/T AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 12.785 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.785 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.785 ------------------------------------------------------------------- slack 0.569 Slack (MET) : 0.569ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.107ns (logic 7.010ns (46.402%) route 8.097ns (53.598%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.640 9.227 ext_ram_data_IOBUF[24]_inst/T AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 12.785 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.785 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.785 ------------------------------------------------------------------- slack 0.569 Slack (MET) : 0.569ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.107ns (logic 7.010ns (46.402%) route 8.097ns (53.598%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.640 9.227 ext_ram_data_IOBUF[24]_inst/T AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 12.785 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.785 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.785 ------------------------------------------------------------------- slack 0.569 Slack (MET) : 0.569ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.107ns (logic 7.010ns (46.402%) route 8.097ns (53.598%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.640 9.227 ext_ram_data_IOBUF[24]_inst/T AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 12.785 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.785 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.785 ------------------------------------------------------------------- slack 0.569 Slack (MET) : 0.569ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.107ns (logic 7.010ns (46.402%) route 8.097ns (53.598%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.640 9.227 ext_ram_data_IOBUF[24]_inst/T AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 12.785 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.785 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.785 ------------------------------------------------------------------- slack 0.569 Slack (MET) : 0.569ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.107ns (logic 7.010ns (46.402%) route 8.097ns (53.598%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.640 9.227 ext_ram_data_IOBUF[24]_inst/T AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 12.785 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.785 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.785 ------------------------------------------------------------------- slack 0.569 Slack (MET) : 0.569ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.107ns (logic 7.010ns (46.402%) route 8.097ns (53.598%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.640 9.227 ext_ram_data_IOBUF[24]_inst/T AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 12.785 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.785 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.785 ------------------------------------------------------------------- slack 0.569 Slack (MET) : 0.569ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.107ns (logic 7.010ns (46.402%) route 8.097ns (53.598%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.640 9.227 ext_ram_data_IOBUF[24]_inst/T AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 12.785 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.785 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.785 ------------------------------------------------------------------- slack 0.569 Slack (MET) : 0.569ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.107ns (logic 7.010ns (46.402%) route 8.097ns (53.598%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.640 9.227 ext_ram_data_IOBUF[24]_inst/T AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 12.785 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.785 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.785 ------------------------------------------------------------------- slack 0.569 Slack (MET) : 0.577ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.190ns (logic 5.298ns (34.876%) route 9.893ns (65.124%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.861 9.248 ext_ram_data_IOBUF[30]_inst/I AA19 r ext_ram_data_IOBUF[30]_inst/OBUFT/I AA19 OBUFT (Prop_obuft_I_O) 3.529 12.777 r ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.777 ext_ram_data[30] AA19 r ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.777 ------------------------------------------------------------------- slack 0.577 Slack (MET) : 0.577ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.190ns (logic 5.298ns (34.876%) route 9.893ns (65.124%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.861 9.248 ext_ram_data_IOBUF[30]_inst/I AA19 r ext_ram_data_IOBUF[30]_inst/OBUFT/I AA19 OBUFT (Prop_obuft_I_O) 3.529 12.777 r ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.777 ext_ram_data[30] AA19 r ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.777 ------------------------------------------------------------------- slack 0.577 Slack (MET) : 0.577ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.190ns (logic 5.298ns (34.876%) route 9.893ns (65.124%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.861 9.248 ext_ram_data_IOBUF[30]_inst/I AA19 r ext_ram_data_IOBUF[30]_inst/OBUFT/I AA19 OBUFT (Prop_obuft_I_O) 3.529 12.777 r ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.777 ext_ram_data[30] AA19 r ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.777 ------------------------------------------------------------------- slack 0.577 Slack (MET) : 0.577ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.190ns (logic 5.298ns (34.876%) route 9.893ns (65.124%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.861 9.248 ext_ram_data_IOBUF[30]_inst/I AA19 r ext_ram_data_IOBUF[30]_inst/OBUFT/I AA19 OBUFT (Prop_obuft_I_O) 3.529 12.777 r ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.777 ext_ram_data[30] AA19 r ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.777 ------------------------------------------------------------------- slack 0.577 Slack (MET) : 0.577ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.190ns (logic 5.298ns (34.876%) route 9.893ns (65.124%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 f u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.861 9.248 ext_ram_data_IOBUF[30]_inst/I AA19 r ext_ram_data_IOBUF[30]_inst/OBUFT/I AA19 OBUFT (Prop_obuft_I_O) 3.529 12.777 r ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.777 ext_ram_data[30] AA19 r ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.777 ------------------------------------------------------------------- slack 0.577 Slack (MET) : 0.577ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.190ns (logic 5.298ns (34.876%) route 9.893ns (65.124%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 f u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.861 9.248 ext_ram_data_IOBUF[30]_inst/I AA19 r ext_ram_data_IOBUF[30]_inst/OBUFT/I AA19 OBUFT (Prop_obuft_I_O) 3.529 12.777 r ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.777 ext_ram_data[30] AA19 r ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.777 ------------------------------------------------------------------- slack 0.577 Slack (MET) : 0.577ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.190ns (logic 5.298ns (34.876%) route 9.893ns (65.124%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 f u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.861 9.248 ext_ram_data_IOBUF[30]_inst/I AA19 r ext_ram_data_IOBUF[30]_inst/OBUFT/I AA19 OBUFT (Prop_obuft_I_O) 3.529 12.777 r ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.777 ext_ram_data[30] AA19 r ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.777 ------------------------------------------------------------------- slack 0.577 Slack (MET) : 0.577ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.190ns (logic 5.298ns (34.876%) route 9.893ns (65.124%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 f u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.861 9.248 ext_ram_data_IOBUF[30]_inst/I AA19 r ext_ram_data_IOBUF[30]_inst/OBUFT/I AA19 OBUFT (Prop_obuft_I_O) 3.529 12.777 r ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.777 ext_ram_data[30] AA19 r ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.777 ------------------------------------------------------------------- slack 0.577 Slack (MET) : 0.577ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.190ns (logic 5.298ns (34.876%) route 9.893ns (65.124%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 f u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.861 9.248 ext_ram_data_IOBUF[30]_inst/I AA19 f ext_ram_data_IOBUF[30]_inst/OBUFT/I AA19 OBUFT (Prop_obuft_I_O) 3.529 12.777 f ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.777 ext_ram_data[30] AA19 f ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.777 ------------------------------------------------------------------- slack 0.577 Slack (MET) : 0.577ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.190ns (logic 5.298ns (34.876%) route 9.893ns (65.124%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 f u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.861 9.248 ext_ram_data_IOBUF[30]_inst/I AA19 f ext_ram_data_IOBUF[30]_inst/OBUFT/I AA19 OBUFT (Prop_obuft_I_O) 3.529 12.777 f ext_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.777 ext_ram_data[30] AA19 f ext_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.777 ------------------------------------------------------------------- slack 0.577 Slack (MET) : 0.647ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.120ns (logic 5.412ns (35.791%) route 9.709ns (64.209%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.261 3.015 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X18Y81 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/RADR1 SLICE_X18Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.161 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.789 3.950 u_snix_axil_cdma_mux_8ch/ep_rd_c1[0] SLICE_X16Y80 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 SLICE_X16Y80 LUT6 (Prop_lut6_I1_O) 0.328 4.278 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.775 5.054 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_2 SLICE_X13Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/I4 SLICE_X13Y80 LUT5 (Prop_lut5_I4_O) 0.124 5.178 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/O net (fo=5, routed) 0.627 5.805 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X8Y81 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/I0 SLICE_X8Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.929 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.233 9.162 base_ram_data_IOBUF[0]_inst/I L24 r base_ram_data_IOBUF[0]_inst/OBUFT/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.707 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.707 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.707 ------------------------------------------------------------------- slack 0.647 Slack (MET) : 0.647ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.120ns (logic 5.412ns (35.791%) route 9.709ns (64.209%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.261 3.015 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X18Y81 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/RADR1 SLICE_X18Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.161 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.789 3.950 u_snix_axil_cdma_mux_8ch/ep_rd_c1[0] SLICE_X16Y80 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 SLICE_X16Y80 LUT6 (Prop_lut6_I1_O) 0.328 4.278 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.775 5.054 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_2 SLICE_X13Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/I4 SLICE_X13Y80 LUT5 (Prop_lut5_I4_O) 0.124 5.178 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/O net (fo=5, routed) 0.627 5.805 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X8Y81 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/I0 SLICE_X8Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.929 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.233 9.162 base_ram_data_IOBUF[0]_inst/I L24 r base_ram_data_IOBUF[0]_inst/OBUFT/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.707 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.707 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.707 ------------------------------------------------------------------- slack 0.647 Slack (MET) : 0.647ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.120ns (logic 5.412ns (35.791%) route 9.709ns (64.209%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.261 3.015 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X18Y81 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/RADR1 SLICE_X18Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.161 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.789 3.950 u_snix_axil_cdma_mux_8ch/ep_rd_c1[0] SLICE_X16Y80 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 SLICE_X16Y80 LUT6 (Prop_lut6_I1_O) 0.328 4.278 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.775 5.054 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_2 SLICE_X13Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/I4 SLICE_X13Y80 LUT5 (Prop_lut5_I4_O) 0.124 5.178 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/O net (fo=5, routed) 0.627 5.805 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X8Y81 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/I0 SLICE_X8Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.929 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.233 9.162 base_ram_data_IOBUF[0]_inst/I L24 r base_ram_data_IOBUF[0]_inst/OBUFT/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.707 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.707 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.707 ------------------------------------------------------------------- slack 0.647 Slack (MET) : 0.647ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.120ns (logic 5.412ns (35.791%) route 9.709ns (64.209%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.261 3.015 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X18Y81 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/RADR1 SLICE_X18Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.161 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.789 3.950 u_snix_axil_cdma_mux_8ch/ep_rd_c1[0] SLICE_X16Y80 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 SLICE_X16Y80 LUT6 (Prop_lut6_I1_O) 0.328 4.278 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.775 5.054 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_2 SLICE_X13Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/I4 SLICE_X13Y80 LUT5 (Prop_lut5_I4_O) 0.124 5.178 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/O net (fo=5, routed) 0.627 5.805 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X8Y81 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/I0 SLICE_X8Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.929 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.233 9.162 base_ram_data_IOBUF[0]_inst/I L24 r base_ram_data_IOBUF[0]_inst/OBUFT/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.707 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.707 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.707 ------------------------------------------------------------------- slack 0.647 Slack (MET) : 0.647ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.120ns (logic 5.412ns (35.791%) route 9.709ns (64.209%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.261 3.015 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X18Y81 f u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/RADR1 SLICE_X18Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.161 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.789 3.950 u_snix_axil_cdma_mux_8ch/ep_rd_c1[0] SLICE_X16Y80 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 SLICE_X16Y80 LUT6 (Prop_lut6_I1_O) 0.328 4.278 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.775 5.054 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_2 SLICE_X13Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/I4 SLICE_X13Y80 LUT5 (Prop_lut5_I4_O) 0.124 5.178 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/O net (fo=5, routed) 0.627 5.805 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X8Y81 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/I0 SLICE_X8Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.929 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.233 9.162 base_ram_data_IOBUF[0]_inst/I L24 r base_ram_data_IOBUF[0]_inst/OBUFT/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.707 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.707 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.707 ------------------------------------------------------------------- slack 0.647 Slack (MET) : 0.647ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.120ns (logic 5.412ns (35.791%) route 9.709ns (64.209%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.261 3.015 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X18Y81 f u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/RADR1 SLICE_X18Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.161 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.789 3.950 u_snix_axil_cdma_mux_8ch/ep_rd_c1[0] SLICE_X16Y80 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 SLICE_X16Y80 LUT6 (Prop_lut6_I1_O) 0.328 4.278 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.775 5.054 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_2 SLICE_X13Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/I4 SLICE_X13Y80 LUT5 (Prop_lut5_I4_O) 0.124 5.178 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/O net (fo=5, routed) 0.627 5.805 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X8Y81 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/I0 SLICE_X8Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.929 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.233 9.162 base_ram_data_IOBUF[0]_inst/I L24 r base_ram_data_IOBUF[0]_inst/OBUFT/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.707 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.707 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.707 ------------------------------------------------------------------- slack 0.647 Slack (MET) : 0.647ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.120ns (logic 5.412ns (35.791%) route 9.709ns (64.209%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.261 3.015 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X18Y81 f u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/RADR1 SLICE_X18Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.161 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.789 3.950 u_snix_axil_cdma_mux_8ch/ep_rd_c1[0] SLICE_X16Y80 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 SLICE_X16Y80 LUT6 (Prop_lut6_I1_O) 0.328 4.278 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.775 5.054 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_2 SLICE_X13Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/I4 SLICE_X13Y80 LUT5 (Prop_lut5_I4_O) 0.124 5.178 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/O net (fo=5, routed) 0.627 5.805 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X8Y81 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/I0 SLICE_X8Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.929 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.233 9.162 base_ram_data_IOBUF[0]_inst/I L24 r base_ram_data_IOBUF[0]_inst/OBUFT/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.707 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.707 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.707 ------------------------------------------------------------------- slack 0.647 Slack (MET) : 0.647ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.120ns (logic 5.412ns (35.791%) route 9.709ns (64.209%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.261 3.015 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X18Y81 f u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/RADR1 SLICE_X18Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.161 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.789 3.950 u_snix_axil_cdma_mux_8ch/ep_rd_c1[0] SLICE_X16Y80 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 SLICE_X16Y80 LUT6 (Prop_lut6_I1_O) 0.328 4.278 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.775 5.054 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_2 SLICE_X13Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/I4 SLICE_X13Y80 LUT5 (Prop_lut5_I4_O) 0.124 5.178 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/O net (fo=5, routed) 0.627 5.805 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X8Y81 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/I0 SLICE_X8Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.929 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.233 9.162 base_ram_data_IOBUF[0]_inst/I L24 r base_ram_data_IOBUF[0]_inst/OBUFT/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.707 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.707 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.707 ------------------------------------------------------------------- slack 0.647 Slack (MET) : 0.647ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.120ns (logic 5.412ns (35.791%) route 9.709ns (64.209%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.261 3.015 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X18Y81 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/RADR1 SLICE_X18Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.161 f u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.789 3.950 u_snix_axil_cdma_mux_8ch/ep_rd_c1[0] SLICE_X16Y80 f u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 SLICE_X16Y80 LUT6 (Prop_lut6_I1_O) 0.328 4.278 f u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.775 5.054 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_2 SLICE_X13Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/I4 SLICE_X13Y80 LUT5 (Prop_lut5_I4_O) 0.124 5.178 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/O net (fo=5, routed) 0.627 5.805 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X8Y81 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/I0 SLICE_X8Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.929 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.233 9.162 base_ram_data_IOBUF[0]_inst/I L24 f base_ram_data_IOBUF[0]_inst/OBUFT/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.707 f base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.707 base_ram_data[0] L24 f base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.707 ------------------------------------------------------------------- slack 0.647 Slack (MET) : 0.647ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.120ns (logic 5.412ns (35.791%) route 9.709ns (64.209%)) Logic Levels: 9 (LUT2=1 LUT3=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.261 3.015 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/ADDRA1 SLICE_X18Y81 r u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/RADR1 SLICE_X18Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.161 f u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.789 3.950 u_snix_axil_cdma_mux_8ch/ep_rd_c1[0] SLICE_X16Y80 f u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 SLICE_X16Y80 LUT6 (Prop_lut6_I1_O) 0.328 4.278 f u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O net (fo=1, routed) 0.775 5.054 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_2 SLICE_X13Y80 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/I4 SLICE_X13Y80 LUT5 (Prop_lut5_I4_O) 0.124 5.178 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_64/O net (fo=5, routed) 0.627 5.805 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X8Y81 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/I0 SLICE_X8Y81 LUT3 (Prop_lut3_I0_O) 0.124 5.929 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.233 9.162 base_ram_data_IOBUF[0]_inst/I L24 f base_ram_data_IOBUF[0]_inst/OBUFT/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.707 f base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.707 base_ram_data[0] L24 f base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.707 ------------------------------------------------------------------- slack 0.647 Slack (MET) : 0.678ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.089ns (logic 5.264ns (34.886%) route 9.825ns (65.114%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.511 3.265 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 SLICE_X22Y81 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/RADR1 SLICE_X22Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.411 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/O net (fo=1, routed) 0.484 3.895 u_matmul_axi_slave/ep_rd_c1_39[48] SLICE_X23Y81 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/I0 SLICE_X23Y81 LUT4 (Prop_lut4_I0_O) 0.328 4.223 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/O net (fo=3, routed) 0.615 4.838 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[13] SLICE_X20Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/I2 SLICE_X20Y83 LUT6 (Prop_lut6_I2_O) 0.124 4.962 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/O net (fo=2, routed) 4.193 9.155 ext_ram_data_IOBUF[16]_inst/I AB16 r ext_ram_data_IOBUF[16]_inst/OBUFT/I AB16 OBUFT (Prop_obuft_I_O) 3.521 12.676 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.676 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.676 ------------------------------------------------------------------- slack 0.678 Slack (MET) : 0.678ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.089ns (logic 5.264ns (34.886%) route 9.825ns (65.114%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.511 3.265 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 SLICE_X22Y81 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/RADR1 SLICE_X22Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.411 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/O net (fo=1, routed) 0.484 3.895 u_matmul_axi_slave/ep_rd_c1_39[48] SLICE_X23Y81 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/I0 SLICE_X23Y81 LUT4 (Prop_lut4_I0_O) 0.328 4.223 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/O net (fo=3, routed) 0.615 4.838 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[13] SLICE_X20Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/I2 SLICE_X20Y83 LUT6 (Prop_lut6_I2_O) 0.124 4.962 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/O net (fo=2, routed) 4.193 9.155 ext_ram_data_IOBUF[16]_inst/I AB16 r ext_ram_data_IOBUF[16]_inst/OBUFT/I AB16 OBUFT (Prop_obuft_I_O) 3.521 12.676 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.676 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.676 ------------------------------------------------------------------- slack 0.678 Slack (MET) : 0.678ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.089ns (logic 5.264ns (34.886%) route 9.825ns (65.114%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.511 3.265 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 SLICE_X22Y81 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/RADR1 SLICE_X22Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.411 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/O net (fo=1, routed) 0.484 3.895 u_matmul_axi_slave/ep_rd_c1_39[48] SLICE_X23Y81 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/I0 SLICE_X23Y81 LUT4 (Prop_lut4_I0_O) 0.328 4.223 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/O net (fo=3, routed) 0.615 4.838 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[13] SLICE_X20Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/I2 SLICE_X20Y83 LUT6 (Prop_lut6_I2_O) 0.124 4.962 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/O net (fo=2, routed) 4.193 9.155 ext_ram_data_IOBUF[16]_inst/I AB16 r ext_ram_data_IOBUF[16]_inst/OBUFT/I AB16 OBUFT (Prop_obuft_I_O) 3.521 12.676 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.676 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.676 ------------------------------------------------------------------- slack 0.678 Slack (MET) : 0.678ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.089ns (logic 5.264ns (34.886%) route 9.825ns (65.114%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.511 3.265 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 SLICE_X22Y81 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/RADR1 SLICE_X22Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.411 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/O net (fo=1, routed) 0.484 3.895 u_matmul_axi_slave/ep_rd_c1_39[48] SLICE_X23Y81 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/I0 SLICE_X23Y81 LUT4 (Prop_lut4_I0_O) 0.328 4.223 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/O net (fo=3, routed) 0.615 4.838 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[13] SLICE_X20Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/I2 SLICE_X20Y83 LUT6 (Prop_lut6_I2_O) 0.124 4.962 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/O net (fo=2, routed) 4.193 9.155 ext_ram_data_IOBUF[16]_inst/I AB16 r ext_ram_data_IOBUF[16]_inst/OBUFT/I AB16 OBUFT (Prop_obuft_I_O) 3.521 12.676 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.676 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.676 ------------------------------------------------------------------- slack 0.678 Slack (MET) : 0.678ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.089ns (logic 5.264ns (34.886%) route 9.825ns (65.114%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.511 3.265 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 SLICE_X22Y81 f u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/RADR1 SLICE_X22Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.411 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/O net (fo=1, routed) 0.484 3.895 u_matmul_axi_slave/ep_rd_c1_39[48] SLICE_X23Y81 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/I0 SLICE_X23Y81 LUT4 (Prop_lut4_I0_O) 0.328 4.223 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/O net (fo=3, routed) 0.615 4.838 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[13] SLICE_X20Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/I2 SLICE_X20Y83 LUT6 (Prop_lut6_I2_O) 0.124 4.962 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/O net (fo=2, routed) 4.193 9.155 ext_ram_data_IOBUF[16]_inst/I AB16 r ext_ram_data_IOBUF[16]_inst/OBUFT/I AB16 OBUFT (Prop_obuft_I_O) 3.521 12.676 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.676 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.676 ------------------------------------------------------------------- slack 0.678 Slack (MET) : 0.678ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.089ns (logic 5.264ns (34.886%) route 9.825ns (65.114%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.511 3.265 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 SLICE_X22Y81 f u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/RADR1 SLICE_X22Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.411 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/O net (fo=1, routed) 0.484 3.895 u_matmul_axi_slave/ep_rd_c1_39[48] SLICE_X23Y81 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/I0 SLICE_X23Y81 LUT4 (Prop_lut4_I0_O) 0.328 4.223 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/O net (fo=3, routed) 0.615 4.838 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[13] SLICE_X20Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/I2 SLICE_X20Y83 LUT6 (Prop_lut6_I2_O) 0.124 4.962 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/O net (fo=2, routed) 4.193 9.155 ext_ram_data_IOBUF[16]_inst/I AB16 r ext_ram_data_IOBUF[16]_inst/OBUFT/I AB16 OBUFT (Prop_obuft_I_O) 3.521 12.676 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.676 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.676 ------------------------------------------------------------------- slack 0.678 Slack (MET) : 0.678ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.089ns (logic 5.264ns (34.886%) route 9.825ns (65.114%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.511 3.265 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 SLICE_X22Y81 f u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/RADR1 SLICE_X22Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.411 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/O net (fo=1, routed) 0.484 3.895 u_matmul_axi_slave/ep_rd_c1_39[48] SLICE_X23Y81 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/I0 SLICE_X23Y81 LUT4 (Prop_lut4_I0_O) 0.328 4.223 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/O net (fo=3, routed) 0.615 4.838 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[13] SLICE_X20Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/I2 SLICE_X20Y83 LUT6 (Prop_lut6_I2_O) 0.124 4.962 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/O net (fo=2, routed) 4.193 9.155 ext_ram_data_IOBUF[16]_inst/I AB16 r ext_ram_data_IOBUF[16]_inst/OBUFT/I AB16 OBUFT (Prop_obuft_I_O) 3.521 12.676 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.676 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.676 ------------------------------------------------------------------- slack 0.678 Slack (MET) : 0.678ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.089ns (logic 5.264ns (34.886%) route 9.825ns (65.114%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.511 3.265 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 SLICE_X22Y81 f u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/RADR1 SLICE_X22Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.411 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/O net (fo=1, routed) 0.484 3.895 u_matmul_axi_slave/ep_rd_c1_39[48] SLICE_X23Y81 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/I0 SLICE_X23Y81 LUT4 (Prop_lut4_I0_O) 0.328 4.223 r u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/O net (fo=3, routed) 0.615 4.838 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[13] SLICE_X20Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/I2 SLICE_X20Y83 LUT6 (Prop_lut6_I2_O) 0.124 4.962 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/O net (fo=2, routed) 4.193 9.155 ext_ram_data_IOBUF[16]_inst/I AB16 r ext_ram_data_IOBUF[16]_inst/OBUFT/I AB16 OBUFT (Prop_obuft_I_O) 3.521 12.676 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.676 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.676 ------------------------------------------------------------------- slack 0.678 Slack (MET) : 0.678ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.089ns (logic 5.264ns (34.886%) route 9.825ns (65.114%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.511 3.265 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 SLICE_X22Y81 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/RADR1 SLICE_X22Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.411 f u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/O net (fo=1, routed) 0.484 3.895 u_matmul_axi_slave/ep_rd_c1_39[48] SLICE_X23Y81 f u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/I0 SLICE_X23Y81 LUT4 (Prop_lut4_I0_O) 0.328 4.223 f u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/O net (fo=3, routed) 0.615 4.838 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[13] SLICE_X20Y83 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/I2 SLICE_X20Y83 LUT6 (Prop_lut6_I2_O) 0.124 4.962 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/O net (fo=2, routed) 4.193 9.155 ext_ram_data_IOBUF[16]_inst/I AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/I AB16 OBUFT (Prop_obuft_I_O) 3.521 12.676 f ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.676 ext_ram_data[16] AB16 f ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.676 ------------------------------------------------------------------- slack 0.678 Slack (MET) : 0.678ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.089ns (logic 5.264ns (34.886%) route 9.825ns (65.114%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.511 3.265 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 SLICE_X22Y81 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/RADR1 SLICE_X22Y81 RAMD32 (Prop_ramd32_RADR1_O) 0.146 3.411 f u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/O net (fo=1, routed) 0.484 3.895 u_matmul_axi_slave/ep_rd_c1_39[48] SLICE_X23Y81 f u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/I0 SLICE_X23Y81 LUT4 (Prop_lut4_I0_O) 0.328 4.223 f u_matmul_axi_slave/ram_reg_0_7_12_17_i_7__0/O net (fo=3, routed) 0.615 4.838 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[13] SLICE_X20Y83 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/I2 SLICE_X20Y83 LUT6 (Prop_lut6_I2_O) 0.124 4.962 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[16]_inst_i_1/O net (fo=2, routed) 4.193 9.155 ext_ram_data_IOBUF[16]_inst/I AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/I AB16 OBUFT (Prop_obuft_I_O) 3.521 12.676 f ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.676 ext_ram_data[16] AB16 f ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.676 ------------------------------------------------------------------- slack 0.678 Slack (MET) : 0.749ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.019ns (logic 5.313ns (35.377%) route 9.706ns (64.623%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.674 9.061 base_ram_data_IOBUF[30]_inst/I M24 r base_ram_data_IOBUF[30]_inst/OBUFT/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.605 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.605 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.605 ------------------------------------------------------------------- slack 0.749 Slack (MET) : 0.749ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.019ns (logic 5.313ns (35.377%) route 9.706ns (64.623%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.674 9.061 base_ram_data_IOBUF[30]_inst/I M24 r base_ram_data_IOBUF[30]_inst/OBUFT/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.605 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.605 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.605 ------------------------------------------------------------------- slack 0.749 Slack (MET) : 0.749ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.019ns (logic 5.313ns (35.377%) route 9.706ns (64.623%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.674 9.061 base_ram_data_IOBUF[30]_inst/I M24 r base_ram_data_IOBUF[30]_inst/OBUFT/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.605 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.605 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.605 ------------------------------------------------------------------- slack 0.749 Slack (MET) : 0.749ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.019ns (logic 5.313ns (35.377%) route 9.706ns (64.623%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.674 9.061 base_ram_data_IOBUF[30]_inst/I M24 r base_ram_data_IOBUF[30]_inst/OBUFT/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.605 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.605 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.605 ------------------------------------------------------------------- slack 0.749 Slack (MET) : 0.749ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.019ns (logic 5.313ns (35.377%) route 9.706ns (64.623%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 f u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.674 9.061 base_ram_data_IOBUF[30]_inst/I M24 r base_ram_data_IOBUF[30]_inst/OBUFT/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.605 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.605 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.605 ------------------------------------------------------------------- slack 0.749 Slack (MET) : 0.749ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.019ns (logic 5.313ns (35.377%) route 9.706ns (64.623%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 f u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.674 9.061 base_ram_data_IOBUF[30]_inst/I M24 r base_ram_data_IOBUF[30]_inst/OBUFT/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.605 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.605 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.605 ------------------------------------------------------------------- slack 0.749 Slack (MET) : 0.749ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.019ns (logic 5.313ns (35.377%) route 9.706ns (64.623%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 f u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.674 9.061 base_ram_data_IOBUF[30]_inst/I M24 r base_ram_data_IOBUF[30]_inst/OBUFT/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.605 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.605 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.605 ------------------------------------------------------------------- slack 0.749 Slack (MET) : 0.749ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.019ns (logic 5.313ns (35.377%) route 9.706ns (64.623%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 f u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.674 9.061 base_ram_data_IOBUF[30]_inst/I M24 r base_ram_data_IOBUF[30]_inst/OBUFT/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.605 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.605 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.605 ------------------------------------------------------------------- slack 0.749 Slack (MET) : 0.749ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.019ns (logic 5.313ns (35.377%) route 9.706ns (64.623%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 f u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.674 9.061 base_ram_data_IOBUF[30]_inst/I M24 f base_ram_data_IOBUF[30]_inst/OBUFT/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.605 f base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.605 base_ram_data[30] M24 f base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.605 ------------------------------------------------------------------- slack 0.749 Slack (MET) : 0.749ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.019ns (logic 5.313ns (35.377%) route 9.706ns (64.623%)) Logic Levels: 8 (LUT2=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.862ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.414ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.862 -2.414 SLICE_X20Y76 FDRE 0.000 -2.414 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C SLICE_X20Y76 FDRE (Prop_fdre_C_Q) 0.478 -1.936 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q net (fo=77, routed) 0.621 -1.315 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] SLICE_X20Y76 f u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/I1 SLICE_X20Y76 LUT2 (Prop_lut2_I1_O) 0.295 -1.020 r u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3/O net (fo=54, routed) 1.201 0.181 u_snix_axil_cdma_mux_8ch/rr_ptr[1]_i_3_n_0 SLICE_X18Y76 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I3 SLICE_X18Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.305 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=3, routed) 0.606 0.912 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 SLICE_X18Y78 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I3 SLICE_X18Y78 LUT6 (Prop_lut6_I3_O) 0.124 1.036 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.594 1.630 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X16Y78 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X16Y78 LUT5 (Prop_lut5_I4_O) 0.124 1.754 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.258 3.013 u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/ADDRB1 SLICE_X14Y80 r u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/RADR1 SLICE_X14Y80 RAMD32 (Prop_ramd32_RADR1_O) 0.152 3.165 f u_matmul_axi_slave/b1_c_reg_r2_0_15_60_65/RAMB/O net (fo=1, routed) 0.865 4.029 u_matmul_axi_slave/ep_rd_c1_39[62] SLICE_X16Y82 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I0 SLICE_X16Y82 LUT4 (Prop_lut4_I0_O) 0.348 4.377 f u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=3, routed) 0.885 5.263 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/_zz_ram_port1_reg[31]_1 SLICE_X24Y82 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I2 SLICE_X24Y82 LUT6 (Prop_lut6_I2_O) 0.124 5.387 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.674 9.061 base_ram_data_IOBUF[30]_inst/I M24 f base_ram_data_IOBUF[30]_inst/OBUFT/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.605 f base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.605 base_ram_data[30] M24 f base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.605 ------------------------------------------------------------------- slack 0.749 Slack (MET) : 0.758ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.918ns (logic 7.005ns (46.961%) route 7.912ns (53.039%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[25]_inst/T AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.596 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.596 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.596 ------------------------------------------------------------------- slack 0.758 Slack (MET) : 0.758ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.918ns (logic 7.005ns (46.961%) route 7.912ns (53.039%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[25]_inst/T AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.596 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.596 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.596 ------------------------------------------------------------------- slack 0.758 Slack (MET) : 0.758ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.918ns (logic 7.005ns (46.961%) route 7.912ns (53.039%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[25]_inst/T AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.596 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.596 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.596 ------------------------------------------------------------------- slack 0.758 Slack (MET) : 0.758ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.918ns (logic 7.005ns (46.961%) route 7.912ns (53.039%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[25]_inst/T AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.596 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.596 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.596 ------------------------------------------------------------------- slack 0.758 Slack (MET) : 0.758ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.918ns (logic 7.005ns (46.961%) route 7.912ns (53.039%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[25]_inst/T AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.596 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.596 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.596 ------------------------------------------------------------------- slack 0.758 Slack (MET) : 0.758ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.918ns (logic 7.005ns (46.961%) route 7.912ns (53.039%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[25]_inst/T AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.596 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.596 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.596 ------------------------------------------------------------------- slack 0.758 Slack (MET) : 0.758ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.918ns (logic 7.005ns (46.961%) route 7.912ns (53.039%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[25]_inst/T AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.596 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.596 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.596 ------------------------------------------------------------------- slack 0.758 Slack (MET) : 0.758ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.918ns (logic 7.005ns (46.961%) route 7.912ns (53.039%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[25]_inst/T AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.596 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.596 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.596 ------------------------------------------------------------------- slack 0.758 Slack (MET) : 0.758ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.918ns (logic 7.005ns (46.961%) route 7.912ns (53.039%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[25]_inst/T AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.596 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.596 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.596 ------------------------------------------------------------------- slack 0.758 Slack (MET) : 0.758ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.918ns (logic 7.005ns (46.961%) route 7.912ns (53.039%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[25]_inst/T AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.596 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.596 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.596 ------------------------------------------------------------------- slack 0.758 Slack (MET) : 0.770ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.906ns (logic 6.994ns (46.921%) route 7.912ns (53.079%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[18]_inst/T AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/T AB17 OBUFT (TriStatE_obuft_T_O) 3.542 12.584 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.584 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.584 ------------------------------------------------------------------- slack 0.770 Slack (MET) : 0.770ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.906ns (logic 6.994ns (46.921%) route 7.912ns (53.079%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[18]_inst/T AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/T AB17 OBUFT (TriStatE_obuft_T_O) 3.542 12.584 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.584 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.584 ------------------------------------------------------------------- slack 0.770 Slack (MET) : 0.770ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.906ns (logic 6.994ns (46.921%) route 7.912ns (53.079%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[18]_inst/T AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/T AB17 OBUFT (TriStatE_obuft_T_O) 3.542 12.584 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.584 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.584 ------------------------------------------------------------------- slack 0.770 Slack (MET) : 0.770ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.906ns (logic 6.994ns (46.921%) route 7.912ns (53.079%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[18]_inst/T AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/T AB17 OBUFT (TriStatE_obuft_T_O) 3.542 12.584 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.584 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.584 ------------------------------------------------------------------- slack 0.770 Slack (MET) : 0.770ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.906ns (logic 6.994ns (46.921%) route 7.912ns (53.079%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[18]_inst/T AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/T AB17 OBUFT (TriStatE_obuft_T_O) 3.542 12.584 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.584 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.584 ------------------------------------------------------------------- slack 0.770 Slack (MET) : 0.770ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.906ns (logic 6.994ns (46.921%) route 7.912ns (53.079%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[18]_inst/T AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/T AB17 OBUFT (TriStatE_obuft_T_O) 3.542 12.584 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.584 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.584 ------------------------------------------------------------------- slack 0.770 Slack (MET) : 0.770ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.906ns (logic 6.994ns (46.921%) route 7.912ns (53.079%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[18]_inst/T AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/T AB17 OBUFT (TriStatE_obuft_T_O) 3.542 12.584 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.584 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.584 ------------------------------------------------------------------- slack 0.770 Slack (MET) : 0.770ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.906ns (logic 6.994ns (46.921%) route 7.912ns (53.079%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[18]_inst/T AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/T AB17 OBUFT (TriStatE_obuft_T_O) 3.542 12.584 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.584 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.584 ------------------------------------------------------------------- slack 0.770 Slack (MET) : 0.770ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.906ns (logic 6.994ns (46.921%) route 7.912ns (53.079%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[18]_inst/T AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/T AB17 OBUFT (TriStatE_obuft_T_O) 3.542 12.584 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.584 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.584 ------------------------------------------------------------------- slack 0.770 Slack (MET) : 0.770ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.906ns (logic 6.994ns (46.921%) route 7.912ns (53.079%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.601 5.464 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y64 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X1Y64 LUT3 (Prop_lut3_I2_O) 0.124 5.588 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.455 9.042 ext_ram_data_IOBUF[18]_inst/T AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/T AB17 OBUFT (TriStatE_obuft_T_O) 3.542 12.584 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.584 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.584 ------------------------------------------------------------------- slack 0.770 Slack (MET) : 0.803ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.873ns (logic 6.998ns (47.053%) route 7.875ns (52.947%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.612 9.005 base_ram_data_IOBUF[31]_inst/T M22 f base_ram_data_IOBUF[31]_inst/OBUFT/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.551 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.551 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.551 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.873ns (logic 6.998ns (47.053%) route 7.875ns (52.947%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.612 9.005 base_ram_data_IOBUF[31]_inst/T M22 f base_ram_data_IOBUF[31]_inst/OBUFT/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.551 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.551 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.551 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.873ns (logic 6.998ns (47.053%) route 7.875ns (52.947%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.612 9.005 base_ram_data_IOBUF[31]_inst/T M22 f base_ram_data_IOBUF[31]_inst/OBUFT/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.551 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.551 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.551 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.873ns (logic 6.998ns (47.053%) route 7.875ns (52.947%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.612 9.005 base_ram_data_IOBUF[31]_inst/T M22 f base_ram_data_IOBUF[31]_inst/OBUFT/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.551 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.551 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.551 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.873ns (logic 6.998ns (47.053%) route 7.875ns (52.947%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.612 9.005 base_ram_data_IOBUF[31]_inst/T M22 f base_ram_data_IOBUF[31]_inst/OBUFT/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.551 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.551 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.551 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.873ns (logic 6.998ns (47.053%) route 7.875ns (52.947%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.612 9.005 base_ram_data_IOBUF[31]_inst/T M22 f base_ram_data_IOBUF[31]_inst/OBUFT/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.551 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.551 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.551 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.873ns (logic 6.998ns (47.053%) route 7.875ns (52.947%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.612 9.005 base_ram_data_IOBUF[31]_inst/T M22 f base_ram_data_IOBUF[31]_inst/OBUFT/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.551 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.551 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.551 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.873ns (logic 6.998ns (47.053%) route 7.875ns (52.947%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.612 9.005 base_ram_data_IOBUF[31]_inst/T M22 f base_ram_data_IOBUF[31]_inst/OBUFT/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.551 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.551 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.551 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.873ns (logic 6.998ns (47.053%) route 7.875ns (52.947%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.612 9.005 base_ram_data_IOBUF[31]_inst/T M22 f base_ram_data_IOBUF[31]_inst/OBUFT/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.551 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.551 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.551 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.873ns (logic 6.998ns (47.053%) route 7.875ns (52.947%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.407 5.269 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y73 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y73 LUT3 (Prop_lut3_I2_O) 0.124 5.393 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.612 9.005 base_ram_data_IOBUF[31]_inst/T M22 f base_ram_data_IOBUF[31]_inst/OBUFT/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.551 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.551 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.551 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.822ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.853ns (logic 6.983ns (47.014%) route 7.870ns (52.986%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.486 7.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y133 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/I5 SLICE_X0Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 1.529 9.000 base_ram_be_n_OBUF[0] L20 r base_ram_be_n_OBUF[0]_inst/I L20 OBUF (Prop_obuf_I_O) 3.531 12.532 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.532 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.532 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.853ns (logic 6.983ns (47.014%) route 7.870ns (52.986%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.486 7.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y133 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/I5 SLICE_X0Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 1.529 9.000 base_ram_be_n_OBUF[0] L20 r base_ram_be_n_OBUF[0]_inst/I L20 OBUF (Prop_obuf_I_O) 3.531 12.532 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.532 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.532 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.853ns (logic 6.983ns (47.014%) route 7.870ns (52.986%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.486 7.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y133 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/I5 SLICE_X0Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 1.529 9.000 base_ram_be_n_OBUF[0] L20 r base_ram_be_n_OBUF[0]_inst/I L20 OBUF (Prop_obuf_I_O) 3.531 12.532 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.532 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.532 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.853ns (logic 6.983ns (47.014%) route 7.870ns (52.986%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.486 7.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y133 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/I5 SLICE_X0Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 1.529 9.000 base_ram_be_n_OBUF[0] L20 r base_ram_be_n_OBUF[0]_inst/I L20 OBUF (Prop_obuf_I_O) 3.531 12.532 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.532 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.532 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.853ns (logic 6.983ns (47.014%) route 7.870ns (52.986%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.486 7.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y133 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/I5 SLICE_X0Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 1.529 9.000 base_ram_be_n_OBUF[0] L20 r base_ram_be_n_OBUF[0]_inst/I L20 OBUF (Prop_obuf_I_O) 3.531 12.532 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.532 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.532 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.853ns (logic 6.983ns (47.014%) route 7.870ns (52.986%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.486 7.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y133 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/I5 SLICE_X0Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 1.529 9.000 base_ram_be_n_OBUF[0] L20 r base_ram_be_n_OBUF[0]_inst/I L20 OBUF (Prop_obuf_I_O) 3.531 12.532 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.532 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.532 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.853ns (logic 6.983ns (47.014%) route 7.870ns (52.986%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.486 7.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y133 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/I5 SLICE_X0Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 1.529 9.000 base_ram_be_n_OBUF[0] L20 r base_ram_be_n_OBUF[0]_inst/I L20 OBUF (Prop_obuf_I_O) 3.531 12.532 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.532 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.532 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.853ns (logic 6.983ns (47.014%) route 7.870ns (52.986%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.486 7.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y133 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/I5 SLICE_X0Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 1.529 9.000 base_ram_be_n_OBUF[0] L20 r base_ram_be_n_OBUF[0]_inst/I L20 OBUF (Prop_obuf_I_O) 3.531 12.532 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.532 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.532 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.853ns (logic 6.983ns (47.014%) route 7.870ns (52.986%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.486 7.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y133 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/I5 SLICE_X0Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 1.529 9.000 base_ram_be_n_OBUF[0] L20 r base_ram_be_n_OBUF[0]_inst/I L20 OBUF (Prop_obuf_I_O) 3.531 12.532 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.532 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.532 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.853ns (logic 6.983ns (47.014%) route 7.870ns (52.986%)) Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.954ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.322ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.954 -2.322 SLICE_X4Y64 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/C SLICE_X4Y64 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[1]/Q net (fo=54, routed) 0.798 -1.068 u_axi_ram/u_axi_sram_sp/len[1] SLICE_X4Y64 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I2 SLICE_X4Y64 LUT4 (Prop_lut4_I2_O) 0.124 -0.944 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.578 -0.366 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1 SLICE_X1Y65 LUT5 (Prop_lut5_I1_O) 0.124 -0.242 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O net (fo=1, routed) 0.585 0.343 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0 SLICE_X2Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5 SLICE_X2Y65 LUT6 (Prop_lut6_I5_O) 0.124 0.467 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O net (fo=1, routed) 0.000 0.467 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0 SLICE_X2Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0] SLICE_X2Y65 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.980 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 0.980 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X2Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X2Y66 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.097 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.097 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X2Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X2Y67 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.214 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.214 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X2Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X2Y68 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.331 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.331 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X2Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X2Y69 CARRY4 (Prop_carry4_CI_O[1]) 0.323 1.654 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 1.005 2.659 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X1Y68 LUT6 (Prop_lut6_I5_O) 0.306 2.965 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.965 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X1Y68 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X1Y68 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.535 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.727 4.263 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y72 LUT6 (Prop_lut6_I5_O) 0.313 4.576 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.163 4.738 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y72 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y72 LUT6 (Prop_lut6_I1_O) 0.124 4.862 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.486 7.348 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X0Y133 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/I5 SLICE_X0Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 1.529 9.000 base_ram_be_n_OBUF[0] L20 r base_ram_be_n_OBUF[0]_inst/I L20 OBUF (Prop_obuf_I_O) 3.531 12.532 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.532 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 0.000 14.326 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.532 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 1.137ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.134ns (logic 7.449ns (25.568%) route 21.685ns (74.432%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 1.102 24.909 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X36Y20 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/I5 SLICE_X36Y20 LUT6 (Prop_lut6_I5_O) 0.124 25.033 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/O net (fo=1, routed) 0.905 25.938 u_cpu/id_stage/ds_to_es_bus_r[181]_i_9_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I1 SLICE_X36Y25 LUT6 (Prop_lut6_I1_O) 0.124 26.062 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.733 26.795 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.919 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.919 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.081 28.056 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 28.056 arrival time -26.919 ------------------------------------------------------------------- slack 1.137 Slack (MET) : 1.137ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.134ns (logic 7.449ns (25.568%) route 21.685ns (74.432%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 1.102 24.909 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X36Y20 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/I5 SLICE_X36Y20 LUT6 (Prop_lut6_I5_O) 0.124 25.033 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/O net (fo=1, routed) 0.905 25.938 u_cpu/id_stage/ds_to_es_bus_r[181]_i_9_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I1 SLICE_X36Y25 LUT6 (Prop_lut6_I1_O) 0.124 26.062 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.733 26.795 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.919 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.919 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.081 28.056 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 28.056 arrival time -26.919 ------------------------------------------------------------------- slack 1.137 Slack (MET) : 1.137ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.134ns (logic 7.449ns (25.568%) route 21.685ns (74.432%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 1.102 24.909 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X36Y20 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/I5 SLICE_X36Y20 LUT6 (Prop_lut6_I5_O) 0.124 25.033 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/O net (fo=1, routed) 0.905 25.938 u_cpu/id_stage/ds_to_es_bus_r[181]_i_9_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I1 SLICE_X36Y25 LUT6 (Prop_lut6_I1_O) 0.124 26.062 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.733 26.795 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.919 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.919 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.081 28.056 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 28.056 arrival time -26.919 ------------------------------------------------------------------- slack 1.137 Slack (MET) : 1.137ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.134ns (logic 7.449ns (25.568%) route 21.685ns (74.432%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 1.102 24.909 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X36Y20 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/I5 SLICE_X36Y20 LUT6 (Prop_lut6_I5_O) 0.124 25.033 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/O net (fo=1, routed) 0.905 25.938 u_cpu/id_stage/ds_to_es_bus_r[181]_i_9_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I1 SLICE_X36Y25 LUT6 (Prop_lut6_I1_O) 0.124 26.062 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.733 26.795 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.919 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.919 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.081 28.056 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 28.056 arrival time -26.919 ------------------------------------------------------------------- slack 1.137 Slack (MET) : 1.137ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.134ns (logic 7.449ns (25.568%) route 21.685ns (74.432%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 1.102 24.909 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X36Y20 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/I5 SLICE_X36Y20 LUT6 (Prop_lut6_I5_O) 0.124 25.033 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/O net (fo=1, routed) 0.905 25.938 u_cpu/id_stage/ds_to_es_bus_r[181]_i_9_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I1 SLICE_X36Y25 LUT6 (Prop_lut6_I1_O) 0.124 26.062 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.733 26.795 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.919 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.919 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.081 28.056 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 28.056 arrival time -26.919 ------------------------------------------------------------------- slack 1.137 Slack (MET) : 1.137ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.134ns (logic 7.449ns (25.568%) route 21.685ns (74.432%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 1.102 24.909 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X36Y20 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/I5 SLICE_X36Y20 LUT6 (Prop_lut6_I5_O) 0.124 25.033 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/O net (fo=1, routed) 0.905 25.938 u_cpu/id_stage/ds_to_es_bus_r[181]_i_9_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I1 SLICE_X36Y25 LUT6 (Prop_lut6_I1_O) 0.124 26.062 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.733 26.795 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.919 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.919 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.081 28.056 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 28.056 arrival time -26.919 ------------------------------------------------------------------- slack 1.137 Slack (MET) : 1.137ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.134ns (logic 7.449ns (25.568%) route 21.685ns (74.432%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 1.102 24.909 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X36Y20 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/I5 SLICE_X36Y20 LUT6 (Prop_lut6_I5_O) 0.124 25.033 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/O net (fo=1, routed) 0.905 25.938 u_cpu/id_stage/ds_to_es_bus_r[181]_i_9_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I1 SLICE_X36Y25 LUT6 (Prop_lut6_I1_O) 0.124 26.062 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.733 26.795 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.919 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.919 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.081 28.056 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 28.056 arrival time -26.919 ------------------------------------------------------------------- slack 1.137 Slack (MET) : 1.137ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.134ns (logic 7.449ns (25.568%) route 21.685ns (74.432%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 1.102 24.909 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X36Y20 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/I5 SLICE_X36Y20 LUT6 (Prop_lut6_I5_O) 0.124 25.033 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/O net (fo=1, routed) 0.905 25.938 u_cpu/id_stage/ds_to_es_bus_r[181]_i_9_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I1 SLICE_X36Y25 LUT6 (Prop_lut6_I1_O) 0.124 26.062 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.733 26.795 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.919 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.919 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.081 28.056 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 28.056 arrival time -26.919 ------------------------------------------------------------------- slack 1.137 Slack (MET) : 1.137ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.134ns (logic 7.449ns (25.568%) route 21.685ns (74.432%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 1.102 24.909 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X36Y20 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/I5 SLICE_X36Y20 LUT6 (Prop_lut6_I5_O) 0.124 25.033 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/O net (fo=1, routed) 0.905 25.938 u_cpu/id_stage/ds_to_es_bus_r[181]_i_9_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I1 SLICE_X36Y25 LUT6 (Prop_lut6_I1_O) 0.124 26.062 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.733 26.795 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.919 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.919 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.081 28.056 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 28.056 arrival time -26.919 ------------------------------------------------------------------- slack 1.137 Slack (MET) : 1.137ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.134ns (logic 7.449ns (25.568%) route 21.685ns (74.432%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.807 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 1.102 24.909 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 SLICE_X36Y20 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/I5 SLICE_X36Y20 LUT6 (Prop_lut6_I5_O) 0.124 25.033 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_9/O net (fo=1, routed) 0.905 25.938 u_cpu/id_stage/ds_to_es_bus_r[181]_i_9_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I1 SLICE_X36Y25 LUT6 (Prop_lut6_I1_O) 0.124 26.062 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.733 26.795 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.919 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.919 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.081 28.056 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 28.056 arrival time -26.919 ------------------------------------------------------------------- slack 1.137 Slack (MET) : 1.177ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.090ns (logic 7.677ns (26.391%) route 21.413ns (73.609%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.999 24.832 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/I3 SLICE_X37Y29 LUT6 (Prop_lut6_I3_O) 0.326 25.158 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/O net (fo=1, routed) 0.808 25.966 u_cpu/id_stage/ds_to_es_bus_r[178]_i_8_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/I0 SLICE_X36Y27 LUT6 (Prop_lut6_I0_O) 0.124 26.090 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O net (fo=1, routed) 0.661 26.751 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.875 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.875 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.077 28.052 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 28.052 arrival time -26.875 ------------------------------------------------------------------- slack 1.177 Slack (MET) : 1.177ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.090ns (logic 7.677ns (26.391%) route 21.413ns (73.609%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.999 24.832 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/I3 SLICE_X37Y29 LUT6 (Prop_lut6_I3_O) 0.326 25.158 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/O net (fo=1, routed) 0.808 25.966 u_cpu/id_stage/ds_to_es_bus_r[178]_i_8_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/I0 SLICE_X36Y27 LUT6 (Prop_lut6_I0_O) 0.124 26.090 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O net (fo=1, routed) 0.661 26.751 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.875 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.875 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.077 28.052 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 28.052 arrival time -26.875 ------------------------------------------------------------------- slack 1.177 Slack (MET) : 1.177ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.090ns (logic 7.677ns (26.391%) route 21.413ns (73.609%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.999 24.832 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/I3 SLICE_X37Y29 LUT6 (Prop_lut6_I3_O) 0.326 25.158 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/O net (fo=1, routed) 0.808 25.966 u_cpu/id_stage/ds_to_es_bus_r[178]_i_8_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/I0 SLICE_X36Y27 LUT6 (Prop_lut6_I0_O) 0.124 26.090 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O net (fo=1, routed) 0.661 26.751 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.875 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.875 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.077 28.052 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 28.052 arrival time -26.875 ------------------------------------------------------------------- slack 1.177 Slack (MET) : 1.177ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.090ns (logic 7.677ns (26.391%) route 21.413ns (73.609%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.999 24.832 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/I3 SLICE_X37Y29 LUT6 (Prop_lut6_I3_O) 0.326 25.158 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/O net (fo=1, routed) 0.808 25.966 u_cpu/id_stage/ds_to_es_bus_r[178]_i_8_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/I0 SLICE_X36Y27 LUT6 (Prop_lut6_I0_O) 0.124 26.090 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O net (fo=1, routed) 0.661 26.751 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.875 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.875 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.077 28.052 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 28.052 arrival time -26.875 ------------------------------------------------------------------- slack 1.177 Slack (MET) : 1.177ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.090ns (logic 7.677ns (26.391%) route 21.413ns (73.609%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.999 24.832 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/I3 SLICE_X37Y29 LUT6 (Prop_lut6_I3_O) 0.326 25.158 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/O net (fo=1, routed) 0.808 25.966 u_cpu/id_stage/ds_to_es_bus_r[178]_i_8_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/I0 SLICE_X36Y27 LUT6 (Prop_lut6_I0_O) 0.124 26.090 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O net (fo=1, routed) 0.661 26.751 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.875 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.875 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.077 28.052 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 28.052 arrival time -26.875 ------------------------------------------------------------------- slack 1.177 Slack (MET) : 1.177ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.090ns (logic 7.677ns (26.391%) route 21.413ns (73.609%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.999 24.832 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/I3 SLICE_X37Y29 LUT6 (Prop_lut6_I3_O) 0.326 25.158 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/O net (fo=1, routed) 0.808 25.966 u_cpu/id_stage/ds_to_es_bus_r[178]_i_8_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/I0 SLICE_X36Y27 LUT6 (Prop_lut6_I0_O) 0.124 26.090 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O net (fo=1, routed) 0.661 26.751 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.875 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.875 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.077 28.052 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 28.052 arrival time -26.875 ------------------------------------------------------------------- slack 1.177 Slack (MET) : 1.177ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.090ns (logic 7.677ns (26.391%) route 21.413ns (73.609%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.999 24.832 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/I3 SLICE_X37Y29 LUT6 (Prop_lut6_I3_O) 0.326 25.158 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/O net (fo=1, routed) 0.808 25.966 u_cpu/id_stage/ds_to_es_bus_r[178]_i_8_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/I0 SLICE_X36Y27 LUT6 (Prop_lut6_I0_O) 0.124 26.090 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O net (fo=1, routed) 0.661 26.751 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.875 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.875 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.077 28.052 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 28.052 arrival time -26.875 ------------------------------------------------------------------- slack 1.177 Slack (MET) : 1.177ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.090ns (logic 7.677ns (26.391%) route 21.413ns (73.609%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.999 24.832 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/I3 SLICE_X37Y29 LUT6 (Prop_lut6_I3_O) 0.326 25.158 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/O net (fo=1, routed) 0.808 25.966 u_cpu/id_stage/ds_to_es_bus_r[178]_i_8_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/I0 SLICE_X36Y27 LUT6 (Prop_lut6_I0_O) 0.124 26.090 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O net (fo=1, routed) 0.661 26.751 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.875 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.875 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.077 28.052 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 28.052 arrival time -26.875 ------------------------------------------------------------------- slack 1.177 Slack (MET) : 1.177ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.090ns (logic 7.677ns (26.391%) route 21.413ns (73.609%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.999 24.832 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/I3 SLICE_X37Y29 LUT6 (Prop_lut6_I3_O) 0.326 25.158 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/O net (fo=1, routed) 0.808 25.966 u_cpu/id_stage/ds_to_es_bus_r[178]_i_8_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/I0 SLICE_X36Y27 LUT6 (Prop_lut6_I0_O) 0.124 26.090 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O net (fo=1, routed) 0.661 26.751 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.875 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.875 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.077 28.052 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 28.052 arrival time -26.875 ------------------------------------------------------------------- slack 1.177 Slack (MET) : 1.177ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 29.090ns (logic 7.677ns (26.391%) route 21.413ns (73.609%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.999 24.832 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/I3 SLICE_X37Y29 LUT6 (Prop_lut6_I3_O) 0.326 25.158 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_8/O net (fo=1, routed) 0.808 25.966 u_cpu/id_stage/ds_to_es_bus_r[178]_i_8_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/I0 SLICE_X36Y27 LUT6 (Prop_lut6_I0_O) 0.124 26.090 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O net (fo=1, routed) 0.661 26.751 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 SLICE_X36Y28 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/I3 SLICE_X36Y28 LUT6 (Prop_lut6_I3_O) 0.124 26.875 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.875 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X36Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.819 28.467 clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X36Y28 FDRE (Setup_fdre_C_D) 0.077 28.052 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 28.052 arrival time -26.875 ------------------------------------------------------------------- slack 1.177 Slack (MET) : 1.295ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.920ns (logic 7.677ns (26.546%) route 21.243ns (73.454%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.427 23.040 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 SLICE_X30Y20 LUT6 (Prop_lut6_I2_O) 0.124 23.164 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.340 24.504 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 SLICE_X43Y25 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 SLICE_X43Y25 LUT2 (Prop_lut2_I1_O) 0.150 24.654 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O net (fo=1, routed) 0.801 25.454 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 SLICE_X39Y25 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 SLICE_X39Y25 LUT6 (Prop_lut6_I2_O) 0.326 25.780 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.801 26.581 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 SLICE_X38Y27 LUT6 (Prop_lut6_I3_O) 0.124 26.705 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 26.705 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 28.000 arrival time -26.705 ------------------------------------------------------------------- slack 1.295 Slack (MET) : 1.295ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.920ns (logic 7.677ns (26.546%) route 21.243ns (73.454%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.427 23.040 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 SLICE_X30Y20 LUT6 (Prop_lut6_I2_O) 0.124 23.164 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.340 24.504 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 SLICE_X43Y25 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 SLICE_X43Y25 LUT2 (Prop_lut2_I1_O) 0.150 24.654 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O net (fo=1, routed) 0.801 25.454 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 SLICE_X39Y25 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 SLICE_X39Y25 LUT6 (Prop_lut6_I2_O) 0.326 25.780 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.801 26.581 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 SLICE_X38Y27 LUT6 (Prop_lut6_I3_O) 0.124 26.705 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 26.705 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 28.000 arrival time -26.705 ------------------------------------------------------------------- slack 1.295 Slack (MET) : 1.295ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.920ns (logic 7.677ns (26.546%) route 21.243ns (73.454%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.427 23.040 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 SLICE_X30Y20 LUT6 (Prop_lut6_I2_O) 0.124 23.164 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.340 24.504 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 SLICE_X43Y25 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 SLICE_X43Y25 LUT2 (Prop_lut2_I1_O) 0.150 24.654 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O net (fo=1, routed) 0.801 25.454 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 SLICE_X39Y25 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 SLICE_X39Y25 LUT6 (Prop_lut6_I2_O) 0.326 25.780 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.801 26.581 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 SLICE_X38Y27 LUT6 (Prop_lut6_I3_O) 0.124 26.705 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 26.705 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 28.000 arrival time -26.705 ------------------------------------------------------------------- slack 1.295 Slack (MET) : 1.295ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.920ns (logic 7.677ns (26.546%) route 21.243ns (73.454%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.427 23.040 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 SLICE_X30Y20 LUT6 (Prop_lut6_I2_O) 0.124 23.164 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.340 24.504 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 SLICE_X43Y25 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 SLICE_X43Y25 LUT2 (Prop_lut2_I1_O) 0.150 24.654 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O net (fo=1, routed) 0.801 25.454 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 SLICE_X39Y25 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 SLICE_X39Y25 LUT6 (Prop_lut6_I2_O) 0.326 25.780 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.801 26.581 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 SLICE_X38Y27 LUT6 (Prop_lut6_I3_O) 0.124 26.705 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 26.705 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 28.000 arrival time -26.705 ------------------------------------------------------------------- slack 1.295 Slack (MET) : 1.295ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.920ns (logic 7.677ns (26.546%) route 21.243ns (73.454%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.427 23.040 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 SLICE_X30Y20 LUT6 (Prop_lut6_I2_O) 0.124 23.164 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.340 24.504 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 SLICE_X43Y25 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 SLICE_X43Y25 LUT2 (Prop_lut2_I1_O) 0.150 24.654 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O net (fo=1, routed) 0.801 25.454 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 SLICE_X39Y25 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 SLICE_X39Y25 LUT6 (Prop_lut6_I2_O) 0.326 25.780 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.801 26.581 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 SLICE_X38Y27 LUT6 (Prop_lut6_I3_O) 0.124 26.705 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 26.705 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 28.000 arrival time -26.705 ------------------------------------------------------------------- slack 1.295 Slack (MET) : 1.295ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.920ns (logic 7.677ns (26.546%) route 21.243ns (73.454%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.427 23.040 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 SLICE_X30Y20 LUT6 (Prop_lut6_I2_O) 0.124 23.164 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.340 24.504 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 SLICE_X43Y25 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 SLICE_X43Y25 LUT2 (Prop_lut2_I1_O) 0.150 24.654 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O net (fo=1, routed) 0.801 25.454 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 SLICE_X39Y25 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 SLICE_X39Y25 LUT6 (Prop_lut6_I2_O) 0.326 25.780 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.801 26.581 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 SLICE_X38Y27 LUT6 (Prop_lut6_I3_O) 0.124 26.705 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 26.705 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 28.000 arrival time -26.705 ------------------------------------------------------------------- slack 1.295 Slack (MET) : 1.295ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.920ns (logic 7.677ns (26.546%) route 21.243ns (73.454%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.427 23.040 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 SLICE_X30Y20 LUT6 (Prop_lut6_I2_O) 0.124 23.164 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.340 24.504 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 SLICE_X43Y25 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 SLICE_X43Y25 LUT2 (Prop_lut2_I1_O) 0.150 24.654 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O net (fo=1, routed) 0.801 25.454 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 SLICE_X39Y25 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 SLICE_X39Y25 LUT6 (Prop_lut6_I2_O) 0.326 25.780 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.801 26.581 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 SLICE_X38Y27 LUT6 (Prop_lut6_I3_O) 0.124 26.705 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 26.705 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 28.000 arrival time -26.705 ------------------------------------------------------------------- slack 1.295 Slack (MET) : 1.295ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.920ns (logic 7.677ns (26.546%) route 21.243ns (73.454%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.427 23.040 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 SLICE_X30Y20 LUT6 (Prop_lut6_I2_O) 0.124 23.164 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.340 24.504 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 SLICE_X43Y25 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 SLICE_X43Y25 LUT2 (Prop_lut2_I1_O) 0.150 24.654 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O net (fo=1, routed) 0.801 25.454 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 SLICE_X39Y25 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 SLICE_X39Y25 LUT6 (Prop_lut6_I2_O) 0.326 25.780 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.801 26.581 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 SLICE_X38Y27 LUT6 (Prop_lut6_I3_O) 0.124 26.705 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 26.705 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 28.000 arrival time -26.705 ------------------------------------------------------------------- slack 1.295 Slack (MET) : 1.295ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.920ns (logic 7.677ns (26.546%) route 21.243ns (73.454%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.427 23.040 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 SLICE_X30Y20 LUT6 (Prop_lut6_I2_O) 0.124 23.164 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.340 24.504 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 SLICE_X43Y25 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 SLICE_X43Y25 LUT2 (Prop_lut2_I1_O) 0.150 24.654 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O net (fo=1, routed) 0.801 25.454 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 SLICE_X39Y25 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 SLICE_X39Y25 LUT6 (Prop_lut6_I2_O) 0.326 25.780 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.801 26.581 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 SLICE_X38Y27 LUT6 (Prop_lut6_I3_O) 0.124 26.705 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 26.705 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 28.000 arrival time -26.705 ------------------------------------------------------------------- slack 1.295 Slack (MET) : 1.295ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.920ns (logic 7.677ns (26.546%) route 21.243ns (73.454%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.427 23.040 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 SLICE_X30Y20 LUT6 (Prop_lut6_I2_O) 0.124 23.164 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O net (fo=32, routed) 1.340 24.504 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 SLICE_X43Y25 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 SLICE_X43Y25 LUT2 (Prop_lut2_I1_O) 0.150 24.654 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O net (fo=1, routed) 0.801 25.454 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 SLICE_X39Y25 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 SLICE_X39Y25 LUT6 (Prop_lut6_I2_O) 0.326 25.780 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.801 26.581 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 SLICE_X38Y27 LUT6 (Prop_lut6_I3_O) 0.124 26.705 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 26.705 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 28.000 arrival time -26.705 ------------------------------------------------------------------- slack 1.295 Slack (MET) : 1.353ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 7.677ns (26.553%) route 21.235ns (73.447%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.826 24.658 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X34Y28 f u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/I0 SLICE_X34Y28 LUT4 (Prop_lut4_I0_O) 0.326 24.984 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/O net (fo=1, routed) 0.646 25.631 u_cpu/id_stage/ds_to_es_bus_r[176]_i_8_n_0 SLICE_X34Y27 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/I3 SLICE_X34Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.755 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/O net (fo=1, routed) 0.819 26.574 u_cpu/id_stage/ds_to_es_bus_r[176]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.698 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 26.698 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.081 28.051 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 28.051 arrival time -26.698 ------------------------------------------------------------------- slack 1.353 Slack (MET) : 1.353ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 7.677ns (26.553%) route 21.235ns (73.447%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.826 24.658 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X34Y28 f u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/I0 SLICE_X34Y28 LUT4 (Prop_lut4_I0_O) 0.326 24.984 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/O net (fo=1, routed) 0.646 25.631 u_cpu/id_stage/ds_to_es_bus_r[176]_i_8_n_0 SLICE_X34Y27 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/I3 SLICE_X34Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.755 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/O net (fo=1, routed) 0.819 26.574 u_cpu/id_stage/ds_to_es_bus_r[176]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.698 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 26.698 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.081 28.051 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 28.051 arrival time -26.698 ------------------------------------------------------------------- slack 1.353 Slack (MET) : 1.353ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 7.677ns (26.553%) route 21.235ns (73.447%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.826 24.658 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X34Y28 f u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/I0 SLICE_X34Y28 LUT4 (Prop_lut4_I0_O) 0.326 24.984 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/O net (fo=1, routed) 0.646 25.631 u_cpu/id_stage/ds_to_es_bus_r[176]_i_8_n_0 SLICE_X34Y27 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/I3 SLICE_X34Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.755 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/O net (fo=1, routed) 0.819 26.574 u_cpu/id_stage/ds_to_es_bus_r[176]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.698 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 26.698 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.081 28.051 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 28.051 arrival time -26.698 ------------------------------------------------------------------- slack 1.353 Slack (MET) : 1.353ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 7.677ns (26.553%) route 21.235ns (73.447%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.826 24.658 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X34Y28 f u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/I0 SLICE_X34Y28 LUT4 (Prop_lut4_I0_O) 0.326 24.984 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/O net (fo=1, routed) 0.646 25.631 u_cpu/id_stage/ds_to_es_bus_r[176]_i_8_n_0 SLICE_X34Y27 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/I3 SLICE_X34Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.755 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/O net (fo=1, routed) 0.819 26.574 u_cpu/id_stage/ds_to_es_bus_r[176]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.698 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 26.698 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.081 28.051 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 28.051 arrival time -26.698 ------------------------------------------------------------------- slack 1.353 Slack (MET) : 1.353ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 7.677ns (26.553%) route 21.235ns (73.447%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.826 24.658 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X34Y28 f u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/I0 SLICE_X34Y28 LUT4 (Prop_lut4_I0_O) 0.326 24.984 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/O net (fo=1, routed) 0.646 25.631 u_cpu/id_stage/ds_to_es_bus_r[176]_i_8_n_0 SLICE_X34Y27 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/I3 SLICE_X34Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.755 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/O net (fo=1, routed) 0.819 26.574 u_cpu/id_stage/ds_to_es_bus_r[176]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.698 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 26.698 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.081 28.051 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 28.051 arrival time -26.698 ------------------------------------------------------------------- slack 1.353 Slack (MET) : 1.353ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 7.677ns (26.553%) route 21.235ns (73.447%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.826 24.658 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X34Y28 f u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/I0 SLICE_X34Y28 LUT4 (Prop_lut4_I0_O) 0.326 24.984 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/O net (fo=1, routed) 0.646 25.631 u_cpu/id_stage/ds_to_es_bus_r[176]_i_8_n_0 SLICE_X34Y27 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/I3 SLICE_X34Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.755 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/O net (fo=1, routed) 0.819 26.574 u_cpu/id_stage/ds_to_es_bus_r[176]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.698 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 26.698 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.081 28.051 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 28.051 arrival time -26.698 ------------------------------------------------------------------- slack 1.353 Slack (MET) : 1.353ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 7.677ns (26.553%) route 21.235ns (73.447%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.826 24.658 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X34Y28 f u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/I0 SLICE_X34Y28 LUT4 (Prop_lut4_I0_O) 0.326 24.984 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/O net (fo=1, routed) 0.646 25.631 u_cpu/id_stage/ds_to_es_bus_r[176]_i_8_n_0 SLICE_X34Y27 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/I3 SLICE_X34Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.755 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/O net (fo=1, routed) 0.819 26.574 u_cpu/id_stage/ds_to_es_bus_r[176]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.698 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 26.698 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.081 28.051 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 28.051 arrival time -26.698 ------------------------------------------------------------------- slack 1.353 Slack (MET) : 1.353ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 7.677ns (26.553%) route 21.235ns (73.447%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.826 24.658 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X34Y28 f u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/I0 SLICE_X34Y28 LUT4 (Prop_lut4_I0_O) 0.326 24.984 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/O net (fo=1, routed) 0.646 25.631 u_cpu/id_stage/ds_to_es_bus_r[176]_i_8_n_0 SLICE_X34Y27 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/I3 SLICE_X34Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.755 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/O net (fo=1, routed) 0.819 26.574 u_cpu/id_stage/ds_to_es_bus_r[176]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.698 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 26.698 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.081 28.051 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 28.051 arrival time -26.698 ------------------------------------------------------------------- slack 1.353 Slack (MET) : 1.353ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 7.677ns (26.553%) route 21.235ns (73.447%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.826 24.658 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X34Y28 f u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/I0 SLICE_X34Y28 LUT4 (Prop_lut4_I0_O) 0.326 24.984 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/O net (fo=1, routed) 0.646 25.631 u_cpu/id_stage/ds_to_es_bus_r[176]_i_8_n_0 SLICE_X34Y27 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/I3 SLICE_X34Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.755 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/O net (fo=1, routed) 0.819 26.574 u_cpu/id_stage/ds_to_es_bus_r[176]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.698 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 26.698 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.081 28.051 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 28.051 arrival time -26.698 ------------------------------------------------------------------- slack 1.353 Slack (MET) : 1.353ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 7.677ns (26.553%) route 21.235ns (73.447%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.826 24.658 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X34Y28 f u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/I0 SLICE_X34Y28 LUT4 (Prop_lut4_I0_O) 0.326 24.984 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_8/O net (fo=1, routed) 0.646 25.631 u_cpu/id_stage/ds_to_es_bus_r[176]_i_8_n_0 SLICE_X34Y27 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/I3 SLICE_X34Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.755 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_3/O net (fo=1, routed) 0.819 26.574 u_cpu/id_stage/ds_to_es_bus_r[176]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.698 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 26.698 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.081 28.051 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 28.051 arrival time -26.698 ------------------------------------------------------------------- slack 1.353 Slack (MET) : 1.368ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.849ns (logic 7.449ns (25.820%) route 21.400ns (74.179%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/I0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.412 24.851 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X40Y22 f u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/I0 SLICE_X40Y22 LUT5 (Prop_lut5_I0_O) 0.124 24.975 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O net (fo=1, routed) 0.795 25.770 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 SLICE_X37Y24 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/I0 SLICE_X37Y24 LUT5 (Prop_lut5_I0_O) 0.124 25.894 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O net (fo=1, routed) 0.617 26.511 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 SLICE_X35Y26 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/I3 SLICE_X35Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.635 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.635 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 28.003 arrival time -26.635 ------------------------------------------------------------------- slack 1.368 Slack (MET) : 1.368ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.849ns (logic 7.449ns (25.820%) route 21.400ns (74.179%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/I0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.412 24.851 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X40Y22 f u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/I0 SLICE_X40Y22 LUT5 (Prop_lut5_I0_O) 0.124 24.975 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O net (fo=1, routed) 0.795 25.770 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 SLICE_X37Y24 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/I0 SLICE_X37Y24 LUT5 (Prop_lut5_I0_O) 0.124 25.894 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O net (fo=1, routed) 0.617 26.511 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 SLICE_X35Y26 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/I3 SLICE_X35Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.635 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.635 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 28.003 arrival time -26.635 ------------------------------------------------------------------- slack 1.368 Slack (MET) : 1.368ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.849ns (logic 7.449ns (25.820%) route 21.400ns (74.179%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/I0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.412 24.851 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X40Y22 f u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/I0 SLICE_X40Y22 LUT5 (Prop_lut5_I0_O) 0.124 24.975 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O net (fo=1, routed) 0.795 25.770 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 SLICE_X37Y24 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/I0 SLICE_X37Y24 LUT5 (Prop_lut5_I0_O) 0.124 25.894 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O net (fo=1, routed) 0.617 26.511 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 SLICE_X35Y26 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/I3 SLICE_X35Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.635 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.635 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 28.003 arrival time -26.635 ------------------------------------------------------------------- slack 1.368 Slack (MET) : 1.368ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.849ns (logic 7.449ns (25.820%) route 21.400ns (74.179%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/I0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.412 24.851 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X40Y22 f u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/I0 SLICE_X40Y22 LUT5 (Prop_lut5_I0_O) 0.124 24.975 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O net (fo=1, routed) 0.795 25.770 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 SLICE_X37Y24 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/I0 SLICE_X37Y24 LUT5 (Prop_lut5_I0_O) 0.124 25.894 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O net (fo=1, routed) 0.617 26.511 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 SLICE_X35Y26 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/I3 SLICE_X35Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.635 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.635 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 28.003 arrival time -26.635 ------------------------------------------------------------------- slack 1.368 Slack (MET) : 1.368ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.849ns (logic 7.449ns (25.820%) route 21.400ns (74.179%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/I0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.412 24.851 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X40Y22 f u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/I0 SLICE_X40Y22 LUT5 (Prop_lut5_I0_O) 0.124 24.975 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O net (fo=1, routed) 0.795 25.770 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 SLICE_X37Y24 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/I0 SLICE_X37Y24 LUT5 (Prop_lut5_I0_O) 0.124 25.894 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O net (fo=1, routed) 0.617 26.511 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 SLICE_X35Y26 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/I3 SLICE_X35Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.635 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.635 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 28.003 arrival time -26.635 ------------------------------------------------------------------- slack 1.368 Slack (MET) : 1.368ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.849ns (logic 7.449ns (25.820%) route 21.400ns (74.179%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/I0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.412 24.851 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X40Y22 f u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/I0 SLICE_X40Y22 LUT5 (Prop_lut5_I0_O) 0.124 24.975 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O net (fo=1, routed) 0.795 25.770 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 SLICE_X37Y24 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/I0 SLICE_X37Y24 LUT5 (Prop_lut5_I0_O) 0.124 25.894 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O net (fo=1, routed) 0.617 26.511 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 SLICE_X35Y26 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/I3 SLICE_X35Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.635 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.635 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 28.003 arrival time -26.635 ------------------------------------------------------------------- slack 1.368 Slack (MET) : 1.368ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.849ns (logic 7.449ns (25.820%) route 21.400ns (74.179%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/I0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.412 24.851 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X40Y22 f u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/I0 SLICE_X40Y22 LUT5 (Prop_lut5_I0_O) 0.124 24.975 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O net (fo=1, routed) 0.795 25.770 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 SLICE_X37Y24 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/I0 SLICE_X37Y24 LUT5 (Prop_lut5_I0_O) 0.124 25.894 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O net (fo=1, routed) 0.617 26.511 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 SLICE_X35Y26 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/I3 SLICE_X35Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.635 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.635 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 28.003 arrival time -26.635 ------------------------------------------------------------------- slack 1.368 Slack (MET) : 1.368ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.849ns (logic 7.449ns (25.820%) route 21.400ns (74.179%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/I0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.412 24.851 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X40Y22 f u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/I0 SLICE_X40Y22 LUT5 (Prop_lut5_I0_O) 0.124 24.975 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O net (fo=1, routed) 0.795 25.770 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 SLICE_X37Y24 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/I0 SLICE_X37Y24 LUT5 (Prop_lut5_I0_O) 0.124 25.894 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O net (fo=1, routed) 0.617 26.511 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 SLICE_X35Y26 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/I3 SLICE_X35Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.635 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.635 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 28.003 arrival time -26.635 ------------------------------------------------------------------- slack 1.368 Slack (MET) : 1.368ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.849ns (logic 7.449ns (25.820%) route 21.400ns (74.179%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/I0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.412 24.851 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X40Y22 f u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/I0 SLICE_X40Y22 LUT5 (Prop_lut5_I0_O) 0.124 24.975 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O net (fo=1, routed) 0.795 25.770 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 SLICE_X37Y24 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/I0 SLICE_X37Y24 LUT5 (Prop_lut5_I0_O) 0.124 25.894 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O net (fo=1, routed) 0.617 26.511 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 SLICE_X35Y26 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/I3 SLICE_X35Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.635 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.635 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 28.003 arrival time -26.635 ------------------------------------------------------------------- slack 1.368 Slack (MET) : 1.368ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.849ns (logic 7.449ns (25.820%) route 21.400ns (74.179%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.702 23.314 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/I0 SLICE_X30Y20 LUT6 (Prop_lut6_I0_O) 0.124 23.438 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.412 24.851 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X40Y22 f u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/I0 SLICE_X40Y22 LUT5 (Prop_lut5_I0_O) 0.124 24.975 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O net (fo=1, routed) 0.795 25.770 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 SLICE_X37Y24 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/I0 SLICE_X37Y24 LUT5 (Prop_lut5_I0_O) 0.124 25.894 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O net (fo=1, routed) 0.617 26.511 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 SLICE_X35Y26 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/I3 SLICE_X35Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.635 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.635 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 28.003 arrival time -26.635 ------------------------------------------------------------------- slack 1.368 Slack (MET) : 1.427ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.841ns (logic 7.677ns (26.618%) route 21.164ns (73.382%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.868 23.481 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X31Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X31Y26 LUT5 (Prop_lut5_I2_O) 0.150 23.631 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.824 24.455 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X33Y28 f u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/I0 SLICE_X33Y28 LUT6 (Prop_lut6_I0_O) 0.326 24.781 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.845 25.625 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X33Y28 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I2 SLICE_X33Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.749 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.754 26.503 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 SLICE_X36Y27 LUT5 (Prop_lut5_I1_O) 0.124 26.627 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.627 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.817 28.465 clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y27 FDRE (Setup_fdre_C_D) 0.081 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 28.054 arrival time -26.627 ------------------------------------------------------------------- slack 1.427 Slack (MET) : 1.427ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.841ns (logic 7.677ns (26.618%) route 21.164ns (73.382%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.868 23.481 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X31Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X31Y26 LUT5 (Prop_lut5_I2_O) 0.150 23.631 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.824 24.455 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X33Y28 f u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/I0 SLICE_X33Y28 LUT6 (Prop_lut6_I0_O) 0.326 24.781 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.845 25.625 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X33Y28 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I2 SLICE_X33Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.749 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.754 26.503 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 SLICE_X36Y27 LUT5 (Prop_lut5_I1_O) 0.124 26.627 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.627 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.817 28.465 clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y27 FDRE (Setup_fdre_C_D) 0.081 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 28.054 arrival time -26.627 ------------------------------------------------------------------- slack 1.427 Slack (MET) : 1.427ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.841ns (logic 7.677ns (26.618%) route 21.164ns (73.382%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.868 23.481 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X31Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X31Y26 LUT5 (Prop_lut5_I2_O) 0.150 23.631 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.824 24.455 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X33Y28 f u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/I0 SLICE_X33Y28 LUT6 (Prop_lut6_I0_O) 0.326 24.781 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.845 25.625 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X33Y28 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I2 SLICE_X33Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.749 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.754 26.503 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 SLICE_X36Y27 LUT5 (Prop_lut5_I1_O) 0.124 26.627 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.627 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.817 28.465 clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y27 FDRE (Setup_fdre_C_D) 0.081 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 28.054 arrival time -26.627 ------------------------------------------------------------------- slack 1.427 Slack (MET) : 1.427ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.841ns (logic 7.677ns (26.618%) route 21.164ns (73.382%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.868 23.481 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X31Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X31Y26 LUT5 (Prop_lut5_I2_O) 0.150 23.631 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.824 24.455 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X33Y28 f u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/I0 SLICE_X33Y28 LUT6 (Prop_lut6_I0_O) 0.326 24.781 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.845 25.625 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X33Y28 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I2 SLICE_X33Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.749 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.754 26.503 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 SLICE_X36Y27 LUT5 (Prop_lut5_I1_O) 0.124 26.627 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.627 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.817 28.465 clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y27 FDRE (Setup_fdre_C_D) 0.081 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 28.054 arrival time -26.627 ------------------------------------------------------------------- slack 1.427 Slack (MET) : 1.427ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.841ns (logic 7.677ns (26.618%) route 21.164ns (73.382%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.868 23.481 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X31Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X31Y26 LUT5 (Prop_lut5_I2_O) 0.150 23.631 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.824 24.455 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X33Y28 f u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/I0 SLICE_X33Y28 LUT6 (Prop_lut6_I0_O) 0.326 24.781 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.845 25.625 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X33Y28 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I2 SLICE_X33Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.749 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.754 26.503 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 SLICE_X36Y27 LUT5 (Prop_lut5_I1_O) 0.124 26.627 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.627 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.817 28.465 clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y27 FDRE (Setup_fdre_C_D) 0.081 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 28.054 arrival time -26.627 ------------------------------------------------------------------- slack 1.427 Slack (MET) : 1.427ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.841ns (logic 7.677ns (26.618%) route 21.164ns (73.382%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.868 23.481 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X31Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X31Y26 LUT5 (Prop_lut5_I2_O) 0.150 23.631 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.824 24.455 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X33Y28 f u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/I0 SLICE_X33Y28 LUT6 (Prop_lut6_I0_O) 0.326 24.781 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.845 25.625 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X33Y28 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I2 SLICE_X33Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.749 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.754 26.503 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 SLICE_X36Y27 LUT5 (Prop_lut5_I1_O) 0.124 26.627 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.627 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.817 28.465 clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y27 FDRE (Setup_fdre_C_D) 0.081 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 28.054 arrival time -26.627 ------------------------------------------------------------------- slack 1.427 Slack (MET) : 1.427ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.841ns (logic 7.677ns (26.618%) route 21.164ns (73.382%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.868 23.481 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X31Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X31Y26 LUT5 (Prop_lut5_I2_O) 0.150 23.631 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.824 24.455 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X33Y28 f u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/I0 SLICE_X33Y28 LUT6 (Prop_lut6_I0_O) 0.326 24.781 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.845 25.625 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X33Y28 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I2 SLICE_X33Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.749 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.754 26.503 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 SLICE_X36Y27 LUT5 (Prop_lut5_I1_O) 0.124 26.627 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.627 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.817 28.465 clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y27 FDRE (Setup_fdre_C_D) 0.081 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 28.054 arrival time -26.627 ------------------------------------------------------------------- slack 1.427 Slack (MET) : 1.427ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.841ns (logic 7.677ns (26.618%) route 21.164ns (73.382%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.868 23.481 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X31Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X31Y26 LUT5 (Prop_lut5_I2_O) 0.150 23.631 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.824 24.455 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X33Y28 f u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/I0 SLICE_X33Y28 LUT6 (Prop_lut6_I0_O) 0.326 24.781 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.845 25.625 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X33Y28 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I2 SLICE_X33Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.749 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.754 26.503 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 SLICE_X36Y27 LUT5 (Prop_lut5_I1_O) 0.124 26.627 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.627 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.817 28.465 clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y27 FDRE (Setup_fdre_C_D) 0.081 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 28.054 arrival time -26.627 ------------------------------------------------------------------- slack 1.427 Slack (MET) : 1.427ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.841ns (logic 7.677ns (26.618%) route 21.164ns (73.382%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.868 23.481 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X31Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X31Y26 LUT5 (Prop_lut5_I2_O) 0.150 23.631 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.824 24.455 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X33Y28 f u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/I0 SLICE_X33Y28 LUT6 (Prop_lut6_I0_O) 0.326 24.781 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.845 25.625 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X33Y28 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I2 SLICE_X33Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.749 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.754 26.503 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 SLICE_X36Y27 LUT5 (Prop_lut5_I1_O) 0.124 26.627 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.627 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.817 28.465 clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y27 FDRE (Setup_fdre_C_D) 0.081 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 28.054 arrival time -26.627 ------------------------------------------------------------------- slack 1.427 Slack (MET) : 1.427ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.841ns (logic 7.677ns (26.618%) route 21.164ns (73.382%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.868 23.481 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X31Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X31Y26 LUT5 (Prop_lut5_I2_O) 0.150 23.631 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.824 24.455 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X33Y28 f u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/I0 SLICE_X33Y28 LUT6 (Prop_lut6_I0_O) 0.326 24.781 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.845 25.625 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X33Y28 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I2 SLICE_X33Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.749 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.754 26.503 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X36Y27 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 SLICE_X36Y27 LUT5 (Prop_lut5_I1_O) 0.124 26.627 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.627 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X36Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.817 28.465 clock pessimism -0.418 28.047 clock uncertainty -0.074 27.973 SLICE_X36Y27 FDRE (Setup_fdre_C_D) 0.081 28.054 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 28.054 arrival time -26.627 ------------------------------------------------------------------- slack 1.427 Slack (MET) : 1.449ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.813ns (logic 7.677ns (26.645%) route 21.136ns (73.355%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.933 24.766 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y27 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/I0 SLICE_X37Y27 LUT6 (Prop_lut6_I0_O) 0.326 25.092 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O net (fo=1, routed) 0.616 25.708 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 SLICE_X37Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/I0 SLICE_X37Y25 LUT5 (Prop_lut5_I0_O) 0.124 25.832 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O net (fo=1, routed) 0.642 26.474 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.598 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 26.598 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.077 28.047 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 28.047 arrival time -26.598 ------------------------------------------------------------------- slack 1.449 Slack (MET) : 1.449ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.813ns (logic 7.677ns (26.645%) route 21.136ns (73.355%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.933 24.766 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y27 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/I0 SLICE_X37Y27 LUT6 (Prop_lut6_I0_O) 0.326 25.092 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O net (fo=1, routed) 0.616 25.708 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 SLICE_X37Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/I0 SLICE_X37Y25 LUT5 (Prop_lut5_I0_O) 0.124 25.832 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O net (fo=1, routed) 0.642 26.474 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.598 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 26.598 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.077 28.047 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 28.047 arrival time -26.598 ------------------------------------------------------------------- slack 1.449 Slack (MET) : 1.449ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.813ns (logic 7.677ns (26.645%) route 21.136ns (73.355%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.933 24.766 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y27 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/I0 SLICE_X37Y27 LUT6 (Prop_lut6_I0_O) 0.326 25.092 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O net (fo=1, routed) 0.616 25.708 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 SLICE_X37Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/I0 SLICE_X37Y25 LUT5 (Prop_lut5_I0_O) 0.124 25.832 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O net (fo=1, routed) 0.642 26.474 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.598 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 26.598 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.077 28.047 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 28.047 arrival time -26.598 ------------------------------------------------------------------- slack 1.449 Slack (MET) : 1.449ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.813ns (logic 7.677ns (26.645%) route 21.136ns (73.355%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.933 24.766 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y27 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/I0 SLICE_X37Y27 LUT6 (Prop_lut6_I0_O) 0.326 25.092 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O net (fo=1, routed) 0.616 25.708 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 SLICE_X37Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/I0 SLICE_X37Y25 LUT5 (Prop_lut5_I0_O) 0.124 25.832 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O net (fo=1, routed) 0.642 26.474 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.598 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 26.598 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.077 28.047 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 28.047 arrival time -26.598 ------------------------------------------------------------------- slack 1.449 Slack (MET) : 1.449ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.813ns (logic 7.677ns (26.645%) route 21.136ns (73.355%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.933 24.766 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y27 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/I0 SLICE_X37Y27 LUT6 (Prop_lut6_I0_O) 0.326 25.092 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O net (fo=1, routed) 0.616 25.708 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 SLICE_X37Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/I0 SLICE_X37Y25 LUT5 (Prop_lut5_I0_O) 0.124 25.832 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O net (fo=1, routed) 0.642 26.474 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.598 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 26.598 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.077 28.047 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 28.047 arrival time -26.598 ------------------------------------------------------------------- slack 1.449 Slack (MET) : 1.449ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.813ns (logic 7.677ns (26.645%) route 21.136ns (73.355%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.933 24.766 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y27 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/I0 SLICE_X37Y27 LUT6 (Prop_lut6_I0_O) 0.326 25.092 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O net (fo=1, routed) 0.616 25.708 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 SLICE_X37Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/I0 SLICE_X37Y25 LUT5 (Prop_lut5_I0_O) 0.124 25.832 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O net (fo=1, routed) 0.642 26.474 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.598 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 26.598 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.077 28.047 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 28.047 arrival time -26.598 ------------------------------------------------------------------- slack 1.449 Slack (MET) : 1.449ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.813ns (logic 7.677ns (26.645%) route 21.136ns (73.355%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.933 24.766 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y27 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/I0 SLICE_X37Y27 LUT6 (Prop_lut6_I0_O) 0.326 25.092 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O net (fo=1, routed) 0.616 25.708 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 SLICE_X37Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/I0 SLICE_X37Y25 LUT5 (Prop_lut5_I0_O) 0.124 25.832 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O net (fo=1, routed) 0.642 26.474 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.598 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 26.598 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.077 28.047 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 28.047 arrival time -26.598 ------------------------------------------------------------------- slack 1.449 Slack (MET) : 1.449ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.813ns (logic 7.677ns (26.645%) route 21.136ns (73.355%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.933 24.766 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y27 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/I0 SLICE_X37Y27 LUT6 (Prop_lut6_I0_O) 0.326 25.092 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O net (fo=1, routed) 0.616 25.708 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 SLICE_X37Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/I0 SLICE_X37Y25 LUT5 (Prop_lut5_I0_O) 0.124 25.832 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O net (fo=1, routed) 0.642 26.474 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.598 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 26.598 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.077 28.047 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 28.047 arrival time -26.598 ------------------------------------------------------------------- slack 1.449 Slack (MET) : 1.449ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.813ns (logic 7.677ns (26.645%) route 21.136ns (73.355%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.933 24.766 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y27 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/I0 SLICE_X37Y27 LUT6 (Prop_lut6_I0_O) 0.326 25.092 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O net (fo=1, routed) 0.616 25.708 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 SLICE_X37Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/I0 SLICE_X37Y25 LUT5 (Prop_lut5_I0_O) 0.124 25.832 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O net (fo=1, routed) 0.642 26.474 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.598 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 26.598 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.077 28.047 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 28.047 arrival time -26.598 ------------------------------------------------------------------- slack 1.449 Slack (MET) : 1.449ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.813ns (logic 7.677ns (26.645%) route 21.136ns (73.355%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.861ns = ( 28.462 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.933 24.766 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y27 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/I0 SLICE_X37Y27 LUT6 (Prop_lut6_I0_O) 0.326 25.092 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O net (fo=1, routed) 0.616 25.708 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 SLICE_X37Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/I0 SLICE_X37Y25 LUT5 (Prop_lut5_I0_O) 0.124 25.832 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O net (fo=1, routed) 0.642 26.474 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 SLICE_X36Y25 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/I2 SLICE_X36Y25 LUT6 (Prop_lut6_I2_O) 0.124 26.598 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 26.598 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X36Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.814 28.462 clock pessimism -0.418 28.044 clock uncertainty -0.074 27.970 SLICE_X36Y25 FDRE (Setup_fdre_C_D) 0.077 28.047 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 28.047 arrival time -26.598 ------------------------------------------------------------------- slack 1.449 Slack (MET) : 1.471ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.743ns (logic 7.677ns (26.709%) route 21.066ns (73.291%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.700 24.533 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y28 f u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/I2 SLICE_X37Y28 LUT4 (Prop_lut4_I2_O) 0.326 24.859 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/O net (fo=1, routed) 0.634 25.494 u_cpu/id_stage/ds_to_es_bus_r[187]_i_12_n_0 SLICE_X37Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/I3 SLICE_X37Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.618 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O net (fo=1, routed) 0.787 26.405 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/I4 SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 26.529 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.529 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 28.000 arrival time -26.529 ------------------------------------------------------------------- slack 1.471 Slack (MET) : 1.471ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.743ns (logic 7.677ns (26.709%) route 21.066ns (73.291%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.700 24.533 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y28 f u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/I2 SLICE_X37Y28 LUT4 (Prop_lut4_I2_O) 0.326 24.859 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/O net (fo=1, routed) 0.634 25.494 u_cpu/id_stage/ds_to_es_bus_r[187]_i_12_n_0 SLICE_X37Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/I3 SLICE_X37Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.618 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O net (fo=1, routed) 0.787 26.405 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/I4 SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 26.529 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.529 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 28.000 arrival time -26.529 ------------------------------------------------------------------- slack 1.471 Slack (MET) : 1.471ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.743ns (logic 7.677ns (26.709%) route 21.066ns (73.291%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.700 24.533 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y28 f u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/I2 SLICE_X37Y28 LUT4 (Prop_lut4_I2_O) 0.326 24.859 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/O net (fo=1, routed) 0.634 25.494 u_cpu/id_stage/ds_to_es_bus_r[187]_i_12_n_0 SLICE_X37Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/I3 SLICE_X37Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.618 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O net (fo=1, routed) 0.787 26.405 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/I4 SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 26.529 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.529 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 28.000 arrival time -26.529 ------------------------------------------------------------------- slack 1.471 Slack (MET) : 1.471ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.743ns (logic 7.677ns (26.709%) route 21.066ns (73.291%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.700 24.533 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y28 f u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/I2 SLICE_X37Y28 LUT4 (Prop_lut4_I2_O) 0.326 24.859 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/O net (fo=1, routed) 0.634 25.494 u_cpu/id_stage/ds_to_es_bus_r[187]_i_12_n_0 SLICE_X37Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/I3 SLICE_X37Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.618 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O net (fo=1, routed) 0.787 26.405 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/I4 SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 26.529 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.529 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 28.000 arrival time -26.529 ------------------------------------------------------------------- slack 1.471 Slack (MET) : 1.471ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.743ns (logic 7.677ns (26.709%) route 21.066ns (73.291%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.700 24.533 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y28 f u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/I2 SLICE_X37Y28 LUT4 (Prop_lut4_I2_O) 0.326 24.859 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/O net (fo=1, routed) 0.634 25.494 u_cpu/id_stage/ds_to_es_bus_r[187]_i_12_n_0 SLICE_X37Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/I3 SLICE_X37Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.618 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O net (fo=1, routed) 0.787 26.405 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/I4 SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 26.529 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.529 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 28.000 arrival time -26.529 ------------------------------------------------------------------- slack 1.471 Slack (MET) : 1.471ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.743ns (logic 7.677ns (26.709%) route 21.066ns (73.291%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.700 24.533 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y28 f u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/I2 SLICE_X37Y28 LUT4 (Prop_lut4_I2_O) 0.326 24.859 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/O net (fo=1, routed) 0.634 25.494 u_cpu/id_stage/ds_to_es_bus_r[187]_i_12_n_0 SLICE_X37Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/I3 SLICE_X37Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.618 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O net (fo=1, routed) 0.787 26.405 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/I4 SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 26.529 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.529 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 28.000 arrival time -26.529 ------------------------------------------------------------------- slack 1.471 Slack (MET) : 1.471ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.743ns (logic 7.677ns (26.709%) route 21.066ns (73.291%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.700 24.533 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y28 f u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/I2 SLICE_X37Y28 LUT4 (Prop_lut4_I2_O) 0.326 24.859 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/O net (fo=1, routed) 0.634 25.494 u_cpu/id_stage/ds_to_es_bus_r[187]_i_12_n_0 SLICE_X37Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/I3 SLICE_X37Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.618 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O net (fo=1, routed) 0.787 26.405 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/I4 SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 26.529 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.529 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 28.000 arrival time -26.529 ------------------------------------------------------------------- slack 1.471 Slack (MET) : 1.471ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.743ns (logic 7.677ns (26.709%) route 21.066ns (73.291%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.700 24.533 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y28 f u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/I2 SLICE_X37Y28 LUT4 (Prop_lut4_I2_O) 0.326 24.859 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/O net (fo=1, routed) 0.634 25.494 u_cpu/id_stage/ds_to_es_bus_r[187]_i_12_n_0 SLICE_X37Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/I3 SLICE_X37Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.618 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O net (fo=1, routed) 0.787 26.405 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/I4 SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 26.529 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.529 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 28.000 arrival time -26.529 ------------------------------------------------------------------- slack 1.471 Slack (MET) : 1.471ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.743ns (logic 7.677ns (26.709%) route 21.066ns (73.291%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.700 24.533 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y28 f u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/I2 SLICE_X37Y28 LUT4 (Prop_lut4_I2_O) 0.326 24.859 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/O net (fo=1, routed) 0.634 25.494 u_cpu/id_stage/ds_to_es_bus_r[187]_i_12_n_0 SLICE_X37Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/I3 SLICE_X37Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.618 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O net (fo=1, routed) 0.787 26.405 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/I4 SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 26.529 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.529 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 28.000 arrival time -26.529 ------------------------------------------------------------------- slack 1.471 Slack (MET) : 1.471ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.743ns (logic 7.677ns (26.709%) route 21.066ns (73.291%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=6 LUT5=7 LUT6=11 MUXF7=1 MUXF8=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 1.070 23.683 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X32Y26 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X32Y26 LUT5 (Prop_lut5_I4_O) 0.150 23.833 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.700 24.533 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_3 SLICE_X37Y28 f u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/I2 SLICE_X37Y28 LUT4 (Prop_lut4_I2_O) 0.326 24.859 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_12/O net (fo=1, routed) 0.634 25.494 u_cpu/id_stage/ds_to_es_bus_r[187]_i_12_n_0 SLICE_X37Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/I3 SLICE_X37Y27 LUT4 (Prop_lut4_I3_O) 0.124 25.618 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O net (fo=1, routed) 0.787 26.405 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 SLICE_X38Y27 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/I4 SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 26.529 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.529 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.813 28.461 clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 28.000 arrival time -26.529 ------------------------------------------------------------------- slack 1.471 Slack (MET) : 1.527ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.688ns (logic 7.449ns (25.965%) route 21.239ns (74.035%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.430 23.043 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/I3 SLICE_X30Y20 LUT6 (Prop_lut6_I3_O) 0.124 23.167 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.573 24.740 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X43Y25 f u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/I2 SLICE_X43Y25 LUT4 (Prop_lut4_I2_O) 0.124 24.864 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O net (fo=1, routed) 0.723 25.588 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 SLICE_X39Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/I1 SLICE_X39Y25 LUT6 (Prop_lut6_I1_O) 0.124 25.712 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 0.638 26.350 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X34Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/I4 SLICE_X34Y25 LUT6 (Prop_lut6_I4_O) 0.124 26.474 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.474 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.816 28.464 clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.029 28.001 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 28.001 arrival time -26.474 ------------------------------------------------------------------- slack 1.527 Slack (MET) : 1.527ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.688ns (logic 7.449ns (25.965%) route 21.239ns (74.035%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.430 23.043 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/I3 SLICE_X30Y20 LUT6 (Prop_lut6_I3_O) 0.124 23.167 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.573 24.740 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X43Y25 f u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/I2 SLICE_X43Y25 LUT4 (Prop_lut4_I2_O) 0.124 24.864 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O net (fo=1, routed) 0.723 25.588 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 SLICE_X39Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/I1 SLICE_X39Y25 LUT6 (Prop_lut6_I1_O) 0.124 25.712 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 0.638 26.350 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X34Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/I4 SLICE_X34Y25 LUT6 (Prop_lut6_I4_O) 0.124 26.474 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.474 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.816 28.464 clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.029 28.001 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 28.001 arrival time -26.474 ------------------------------------------------------------------- slack 1.527 Slack (MET) : 1.527ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.688ns (logic 7.449ns (25.965%) route 21.239ns (74.035%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.430 23.043 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/I3 SLICE_X30Y20 LUT6 (Prop_lut6_I3_O) 0.124 23.167 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.573 24.740 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X43Y25 f u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/I2 SLICE_X43Y25 LUT4 (Prop_lut4_I2_O) 0.124 24.864 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O net (fo=1, routed) 0.723 25.588 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 SLICE_X39Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/I1 SLICE_X39Y25 LUT6 (Prop_lut6_I1_O) 0.124 25.712 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 0.638 26.350 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X34Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/I4 SLICE_X34Y25 LUT6 (Prop_lut6_I4_O) 0.124 26.474 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.474 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.816 28.464 clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.029 28.001 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 28.001 arrival time -26.474 ------------------------------------------------------------------- slack 1.527 Slack (MET) : 1.527ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.688ns (logic 7.449ns (25.965%) route 21.239ns (74.035%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.430 23.043 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/I3 SLICE_X30Y20 LUT6 (Prop_lut6_I3_O) 0.124 23.167 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.573 24.740 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X43Y25 f u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/I2 SLICE_X43Y25 LUT4 (Prop_lut4_I2_O) 0.124 24.864 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O net (fo=1, routed) 0.723 25.588 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 SLICE_X39Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/I1 SLICE_X39Y25 LUT6 (Prop_lut6_I1_O) 0.124 25.712 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 0.638 26.350 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X34Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/I4 SLICE_X34Y25 LUT6 (Prop_lut6_I4_O) 0.124 26.474 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.474 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.816 28.464 clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.029 28.001 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 28.001 arrival time -26.474 ------------------------------------------------------------------- slack 1.527 Slack (MET) : 1.527ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.688ns (logic 7.449ns (25.965%) route 21.239ns (74.035%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.430 23.043 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/I3 SLICE_X30Y20 LUT6 (Prop_lut6_I3_O) 0.124 23.167 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.573 24.740 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X43Y25 f u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/I2 SLICE_X43Y25 LUT4 (Prop_lut4_I2_O) 0.124 24.864 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O net (fo=1, routed) 0.723 25.588 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 SLICE_X39Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/I1 SLICE_X39Y25 LUT6 (Prop_lut6_I1_O) 0.124 25.712 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 0.638 26.350 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X34Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/I4 SLICE_X34Y25 LUT6 (Prop_lut6_I4_O) 0.124 26.474 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.474 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.816 28.464 clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.029 28.001 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 28.001 arrival time -26.474 ------------------------------------------------------------------- slack 1.527 Slack (MET) : 1.527ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.688ns (logic 7.449ns (25.965%) route 21.239ns (74.035%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.430 23.043 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/I3 SLICE_X30Y20 LUT6 (Prop_lut6_I3_O) 0.124 23.167 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.573 24.740 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X43Y25 f u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/I2 SLICE_X43Y25 LUT4 (Prop_lut4_I2_O) 0.124 24.864 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O net (fo=1, routed) 0.723 25.588 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 SLICE_X39Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/I1 SLICE_X39Y25 LUT6 (Prop_lut6_I1_O) 0.124 25.712 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 0.638 26.350 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X34Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/I4 SLICE_X34Y25 LUT6 (Prop_lut6_I4_O) 0.124 26.474 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.474 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.816 28.464 clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.029 28.001 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 28.001 arrival time -26.474 ------------------------------------------------------------------- slack 1.527 Slack (MET) : 1.527ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.688ns (logic 7.449ns (25.965%) route 21.239ns (74.035%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.430 23.043 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/I3 SLICE_X30Y20 LUT6 (Prop_lut6_I3_O) 0.124 23.167 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.573 24.740 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X43Y25 f u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/I2 SLICE_X43Y25 LUT4 (Prop_lut4_I2_O) 0.124 24.864 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O net (fo=1, routed) 0.723 25.588 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 SLICE_X39Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/I1 SLICE_X39Y25 LUT6 (Prop_lut6_I1_O) 0.124 25.712 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 0.638 26.350 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X34Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/I4 SLICE_X34Y25 LUT6 (Prop_lut6_I4_O) 0.124 26.474 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.474 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.816 28.464 clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.029 28.001 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 28.001 arrival time -26.474 ------------------------------------------------------------------- slack 1.527 Slack (MET) : 1.527ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.688ns (logic 7.449ns (25.965%) route 21.239ns (74.035%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.430 23.043 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/I3 SLICE_X30Y20 LUT6 (Prop_lut6_I3_O) 0.124 23.167 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.573 24.740 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X43Y25 f u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/I2 SLICE_X43Y25 LUT4 (Prop_lut4_I2_O) 0.124 24.864 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O net (fo=1, routed) 0.723 25.588 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 SLICE_X39Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/I1 SLICE_X39Y25 LUT6 (Prop_lut6_I1_O) 0.124 25.712 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 0.638 26.350 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X34Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/I4 SLICE_X34Y25 LUT6 (Prop_lut6_I4_O) 0.124 26.474 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.474 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.816 28.464 clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.029 28.001 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 28.001 arrival time -26.474 ------------------------------------------------------------------- slack 1.527 Slack (MET) : 1.527ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.688ns (logic 7.449ns (25.965%) route 21.239ns (74.035%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.430 23.043 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/I3 SLICE_X30Y20 LUT6 (Prop_lut6_I3_O) 0.124 23.167 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.573 24.740 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X43Y25 f u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/I2 SLICE_X43Y25 LUT4 (Prop_lut4_I2_O) 0.124 24.864 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O net (fo=1, routed) 0.723 25.588 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 SLICE_X39Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/I1 SLICE_X39Y25 LUT6 (Prop_lut6_I1_O) 0.124 25.712 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 0.638 26.350 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X34Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/I4 SLICE_X34Y25 LUT6 (Prop_lut6_I4_O) 0.124 26.474 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.474 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.816 28.464 clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.029 28.001 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 28.001 arrival time -26.474 ------------------------------------------------------------------- slack 1.527 Slack (MET) : 1.527ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.688ns (logic 7.449ns (25.965%) route 21.239ns (74.035%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.062ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.430 23.043 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/I3 SLICE_X30Y20 LUT6 (Prop_lut6_I3_O) 0.124 23.167 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O net (fo=32, routed) 1.573 24.740 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 SLICE_X43Y25 f u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/I2 SLICE_X43Y25 LUT4 (Prop_lut4_I2_O) 0.124 24.864 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O net (fo=1, routed) 0.723 25.588 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 SLICE_X39Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/I1 SLICE_X39Y25 LUT6 (Prop_lut6_I1_O) 0.124 25.712 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 0.638 26.350 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X34Y25 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/I4 SLICE_X34Y25 LUT6 (Prop_lut6_I4_O) 0.124 26.474 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.474 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X34Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.816 28.464 clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X34Y25 FDRE (Setup_fdre_C_D) 0.029 28.001 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 28.001 arrival time -26.474 ------------------------------------------------------------------- slack 1.527 Slack (MET) : 1.551ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.666ns (logic 7.449ns (25.985%) route 21.217ns (74.015%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/I2 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.092 24.400 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_0 SLICE_X38Y25 f u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/I1 SLICE_X38Y25 LUT2 (Prop_lut2_I1_O) 0.124 24.524 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/O net (fo=1, routed) 0.984 25.508 u_cpu/u_csr/ds_to_es_bus_r[165]_i_13_n_0 SLICE_X35Y26 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/I5 SLICE_X35Y26 LUT6 (Prop_lut6_I5_O) 0.124 25.632 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.695 26.328 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X34Y26 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/I3 SLICE_X34Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.452 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.452 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 28.003 arrival time -26.452 ------------------------------------------------------------------- slack 1.551 Slack (MET) : 1.551ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.666ns (logic 7.449ns (25.985%) route 21.217ns (74.015%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/I2 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.092 24.400 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_0 SLICE_X38Y25 f u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/I1 SLICE_X38Y25 LUT2 (Prop_lut2_I1_O) 0.124 24.524 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/O net (fo=1, routed) 0.984 25.508 u_cpu/u_csr/ds_to_es_bus_r[165]_i_13_n_0 SLICE_X35Y26 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/I5 SLICE_X35Y26 LUT6 (Prop_lut6_I5_O) 0.124 25.632 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.695 26.328 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X34Y26 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/I3 SLICE_X34Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.452 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.452 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 28.003 arrival time -26.452 ------------------------------------------------------------------- slack 1.551 Slack (MET) : 1.551ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.666ns (logic 7.449ns (25.985%) route 21.217ns (74.015%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/I2 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.092 24.400 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_0 SLICE_X38Y25 f u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/I1 SLICE_X38Y25 LUT2 (Prop_lut2_I1_O) 0.124 24.524 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/O net (fo=1, routed) 0.984 25.508 u_cpu/u_csr/ds_to_es_bus_r[165]_i_13_n_0 SLICE_X35Y26 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/I5 SLICE_X35Y26 LUT6 (Prop_lut6_I5_O) 0.124 25.632 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.695 26.328 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X34Y26 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/I3 SLICE_X34Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.452 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.452 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 28.003 arrival time -26.452 ------------------------------------------------------------------- slack 1.551 Slack (MET) : 1.551ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.666ns (logic 7.449ns (25.985%) route 21.217ns (74.015%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/I2 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.092 24.400 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_0 SLICE_X38Y25 f u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/I1 SLICE_X38Y25 LUT2 (Prop_lut2_I1_O) 0.124 24.524 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/O net (fo=1, routed) 0.984 25.508 u_cpu/u_csr/ds_to_es_bus_r[165]_i_13_n_0 SLICE_X35Y26 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/I5 SLICE_X35Y26 LUT6 (Prop_lut6_I5_O) 0.124 25.632 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.695 26.328 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X34Y26 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/I3 SLICE_X34Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.452 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.452 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 28.003 arrival time -26.452 ------------------------------------------------------------------- slack 1.551 Slack (MET) : 1.551ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.666ns (logic 7.449ns (25.985%) route 21.217ns (74.015%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/I2 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.092 24.400 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_0 SLICE_X38Y25 f u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/I1 SLICE_X38Y25 LUT2 (Prop_lut2_I1_O) 0.124 24.524 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/O net (fo=1, routed) 0.984 25.508 u_cpu/u_csr/ds_to_es_bus_r[165]_i_13_n_0 SLICE_X35Y26 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/I5 SLICE_X35Y26 LUT6 (Prop_lut6_I5_O) 0.124 25.632 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.695 26.328 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X34Y26 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/I3 SLICE_X34Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.452 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.452 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 28.003 arrival time -26.452 ------------------------------------------------------------------- slack 1.551 Slack (MET) : 1.551ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.666ns (logic 7.449ns (25.985%) route 21.217ns (74.015%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/I2 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.092 24.400 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_0 SLICE_X38Y25 f u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/I1 SLICE_X38Y25 LUT2 (Prop_lut2_I1_O) 0.124 24.524 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/O net (fo=1, routed) 0.984 25.508 u_cpu/u_csr/ds_to_es_bus_r[165]_i_13_n_0 SLICE_X35Y26 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/I5 SLICE_X35Y26 LUT6 (Prop_lut6_I5_O) 0.124 25.632 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.695 26.328 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X34Y26 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/I3 SLICE_X34Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.452 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.452 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 28.003 arrival time -26.452 ------------------------------------------------------------------- slack 1.551 Slack (MET) : 1.551ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.666ns (logic 7.449ns (25.985%) route 21.217ns (74.015%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/I2 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.092 24.400 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_0 SLICE_X38Y25 f u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/I1 SLICE_X38Y25 LUT2 (Prop_lut2_I1_O) 0.124 24.524 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/O net (fo=1, routed) 0.984 25.508 u_cpu/u_csr/ds_to_es_bus_r[165]_i_13_n_0 SLICE_X35Y26 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/I5 SLICE_X35Y26 LUT6 (Prop_lut6_I5_O) 0.124 25.632 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.695 26.328 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X34Y26 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/I3 SLICE_X34Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.452 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.452 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 28.003 arrival time -26.452 ------------------------------------------------------------------- slack 1.551 Slack (MET) : 1.551ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.666ns (logic 7.449ns (25.985%) route 21.217ns (74.015%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/I2 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.092 24.400 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_0 SLICE_X38Y25 f u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/I1 SLICE_X38Y25 LUT2 (Prop_lut2_I1_O) 0.124 24.524 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/O net (fo=1, routed) 0.984 25.508 u_cpu/u_csr/ds_to_es_bus_r[165]_i_13_n_0 SLICE_X35Y26 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/I5 SLICE_X35Y26 LUT6 (Prop_lut6_I5_O) 0.124 25.632 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.695 26.328 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X34Y26 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/I3 SLICE_X34Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.452 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.452 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 28.003 arrival time -26.452 ------------------------------------------------------------------- slack 1.551 Slack (MET) : 1.551ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.666ns (logic 7.449ns (25.985%) route 21.217ns (74.015%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/I2 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.092 24.400 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_0 SLICE_X38Y25 f u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/I1 SLICE_X38Y25 LUT2 (Prop_lut2_I1_O) 0.124 24.524 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/O net (fo=1, routed) 0.984 25.508 u_cpu/u_csr/ds_to_es_bus_r[165]_i_13_n_0 SLICE_X35Y26 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/I5 SLICE_X35Y26 LUT6 (Prop_lut6_I5_O) 0.124 25.632 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.695 26.328 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X34Y26 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/I3 SLICE_X34Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.452 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.452 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 28.003 arrival time -26.452 ------------------------------------------------------------------- slack 1.551 Slack (MET) : 1.551ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.666ns (logic 7.449ns (25.985%) route 21.217ns (74.015%)) Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=4 LUT5=6 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.215ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 4.061 -2.215 SLICE_X20Y38 FDRE 0.000 -2.215 r u_cpu/addr_trans/data_vaddr_buffer_reg[27]/C SLICE_X20Y38 FDRE (Prop_fdre_C_Q) 0.518 -1.697 f u_cpu/addr_trans/data_vaddr_buffer_reg[27]/Q net (fo=65, routed) 1.432 -0.264 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[15] SLICE_X25Y32 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/I3 SLICE_X25Y32 LUT6 (Prop_lut6_I3_O) 0.124 -0.140 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126/O net (fo=1, routed) 0.000 -0.140 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_126_n_0 SLICE_X25Y32 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/S[0] SLICE_X25Y32 CARRY4 (Prop_carry4_S[0]_CO[2]) 0.536 0.396 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36/CO[2] net (fo=1, routed) 1.267 1.663 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_36_n_1 SLICE_X21Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I1 SLICE_X21Y44 LUT6 (Prop_lut6_I1_O) 0.313 1.976 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O net (fo=3, routed) 0.819 2.795 u_cpu/addr_trans/tlb_entry/match1[30] SLICE_X21Y43 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 SLICE_X21Y43 LUT4 (Prop_lut4_I3_O) 0.124 2.919 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 1.007 3.925 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X18Y42 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X18Y42 LUT5 (Prop_lut5_I0_O) 0.124 4.049 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.868 4.917 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X14Y37 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X14Y37 LUT6 (Prop_lut6_I0_O) 0.124 5.041 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 0.921 5.962 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X12Y34 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/S SLICE_X12Y34 MUXF7 (Prop_muxf7_S_O) 0.292 6.254 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0/O net (fo=1, routed) 0.000 6.254 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_66__0_n_0 SLICE_X12Y34 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I1 SLICE_X12Y34 MUXF8 (Prop_muxf8_I1_O) 0.088 6.342 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, routed) 0.891 7.233 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 SLICE_X12Y31 LUT5 (Prop_lut5_I0_O) 0.319 7.552 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, routed) 0.378 7.931 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 SLICE_X12Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 SLICE_X12Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.055 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.418 8.473 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X14Y31 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 SLICE_X14Y31 LUT6 (Prop_lut6_I5_O) 0.124 8.597 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 1.249 9.846 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X19Y23 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/I3 SLICE_X19Y23 LUT6 (Prop_lut6_I3_O) 0.124 9.970 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[2]_i_1__0/O net (fo=6, routed) 0.808 10.778 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[14] SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/I4 SLICE_X20Y21 LUT6 (Prop_lut6_I4_O) 0.124 10.902 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14/O net (fo=1, routed) 0.000 10.902 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_14_n_0 SLICE_X20Y21 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[0] SLICE_X20Y21 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 11.415 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.415 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X20Y22 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X20Y22 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 11.644 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.002 12.646 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X12Y21 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X12Y21 LUT3 (Prop_lut3_I0_O) 0.336 12.982 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.145 14.127 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X9Y24 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/I5 SLICE_X9Y24 LUT6 (Prop_lut6_I5_O) 0.328 14.455 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, routed) 0.719 15.173 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] SLICE_X9Y25 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I1 SLICE_X9Y25 LUT6 (Prop_lut6_I1_O) 0.124 15.297 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, routed) 0.532 15.829 u_cpu/mem_stage/p_5_in6_in[0] SLICE_X8Y25 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/I0 SLICE_X8Y25 LUT4 (Prop_lut4_I0_O) 0.116 15.945 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, routed) 0.611 16.556 u_cpu/u_div/ms_to_ws_bus_r_reg[40] SLICE_X6Y26 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/I4 SLICE_X6Y26 LUT5 (Prop_lut5_I4_O) 0.328 16.884 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, routed) 0.754 17.638 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] SLICE_X11Y23 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/I2 SLICE_X11Y23 LUT4 (Prop_lut4_I2_O) 0.124 17.762 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, routed) 0.816 18.579 u_cpu/id_stage/ms_to_ds_forward_bus[8] SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/I2 SLICE_X18Y20 LUT5 (Prop_lut5_I2_O) 0.124 18.703 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, routed) 0.000 18.703 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 SLICE_X18Y20 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[1] SLICE_X18Y20 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 19.236 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.236 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X18Y21 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X18Y21 CARRY4 (Prop_carry4_CI_O[2]) 0.239 19.475 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[2] net (fo=1, routed) 0.638 20.112 u_cpu/id_stage/rd_csr_addr0[13] SLICE_X19Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I2 SLICE_X19Y20 LUT5 (Prop_lut5_I2_O) 0.327 20.439 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.597 21.036 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X21Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X21Y20 LUT5 (Prop_lut5_I1_O) 0.326 21.362 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.680 22.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X24Y20 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X24Y20 LUT4 (Prop_lut4_I3_O) 0.124 22.166 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.323 22.489 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X26Y20 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X26Y20 LUT6 (Prop_lut6_I5_O) 0.124 22.613 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.571 23.184 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X30Y21 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/I2 SLICE_X30Y21 LUT6 (Prop_lut6_I2_O) 0.124 23.308 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.092 24.400 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_0 SLICE_X38Y25 f u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/I1 SLICE_X38Y25 LUT2 (Prop_lut2_I1_O) 0.124 24.524 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_13/O net (fo=1, routed) 0.984 25.508 u_cpu/u_csr/ds_to_es_bus_r[165]_i_13_n_0 SLICE_X35Y26 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/I5 SLICE_X35Y26 LUT6 (Prop_lut6_I5_O) 0.124 25.632 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.695 26.328 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X34Y26 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/I3 SLICE_X34Y26 LUT6 (Prop_lut6_I3_O) 0.124 26.452 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.452 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X34Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r clock source latency -5.674 24.648 propagated clock network latency 3.818 28.466 clock pessimism -0.418 28.048 clock uncertainty -0.074 27.974 SLICE_X34Y26 FDRE (Setup_fdre_C_D) 0.029 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 28.003 arrival time -26.452 ------------------------------------------------------------------- slack 1.551 Slack (MET) : 5.353ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.257ns (logic 0.642ns (4.503%) route 13.615ns (95.497%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.087 11.761 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X122Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.763 18.088 clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X122Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[5] ------------------------------------------------------------------- required time 17.114 arrival time -11.761 ------------------------------------------------------------------- slack 5.353 Slack (MET) : 5.353ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.257ns (logic 0.642ns (4.503%) route 13.615ns (95.497%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.087 11.761 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X122Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.763 18.088 clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X122Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[6] ------------------------------------------------------------------- required time 17.114 arrival time -11.761 ------------------------------------------------------------------- slack 5.353 Slack (MET) : 5.353ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.257ns (logic 0.642ns (4.503%) route 13.615ns (95.497%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.087 11.761 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X122Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.763 18.088 clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X122Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[7] ------------------------------------------------------------------- required time 17.114 arrival time -11.761 ------------------------------------------------------------------- slack 5.353 Slack (MET) : 5.365ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.245ns (logic 0.642ns (4.507%) route 13.603ns (95.493%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.075 11.749 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X121Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.763 18.088 clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X121Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[0] ------------------------------------------------------------------- required time 17.114 arrival time -11.749 ------------------------------------------------------------------- slack 5.365 Slack (MET) : 5.365ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.245ns (logic 0.642ns (4.507%) route 13.603ns (95.493%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.075 11.749 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X121Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.763 18.088 clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X121Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8] ------------------------------------------------------------------- required time 17.114 arrival time -11.749 ------------------------------------------------------------------- slack 5.365 Slack (MET) : 5.365ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.245ns (logic 0.642ns (4.507%) route 13.603ns (95.493%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.075 11.749 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X121Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.763 18.088 clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X121Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9] ------------------------------------------------------------------- required time 17.114 arrival time -11.749 ------------------------------------------------------------------- slack 5.365 Slack (MET) : 5.365ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.245ns (logic 0.642ns (4.507%) route 13.603ns (95.493%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 10.075 11.749 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X121Y7 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.763 18.088 clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X121Y7 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg ------------------------------------------------------------------- required time 17.114 arrival time -11.749 ------------------------------------------------------------------- slack 5.365 Slack (MET) : 5.494ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.116ns (logic 0.642ns (4.548%) route 13.474ns (95.452%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.946 11.621 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X122Y8 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.763 18.088 clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X122Y8 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2] ------------------------------------------------------------------- required time 17.114 arrival time -11.621 ------------------------------------------------------------------- slack 5.494 Slack (MET) : 5.494ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.116ns (logic 0.642ns (4.548%) route 13.474ns (95.452%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.946 11.621 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X122Y8 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.763 18.088 clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X122Y8 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3] ------------------------------------------------------------------- required time 17.114 arrival time -11.621 ------------------------------------------------------------------- slack 5.494 Slack (MET) : 5.494ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.116ns (logic 0.642ns (4.548%) route 13.474ns (95.452%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.946 11.621 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X122Y8 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.763 18.088 clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X122Y8 FDCE (Recov_fdce_C_CLR) -0.405 17.114 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4] ------------------------------------------------------------------- required time 17.114 arrival time -11.621 ------------------------------------------------------------------- slack 5.494 Slack (MET) : 5.592ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 14.104ns (logic 0.642ns (4.552%) route 13.462ns (95.448%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.912ns = ( 18.088 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.934 11.609 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X120Y8 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.763 18.088 clock pessimism -0.498 17.590 clock uncertainty -0.071 17.519 SLICE_X120Y8 FDCE (Recov_fdce_C_CLR) -0.319 17.200 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1] ------------------------------------------------------------------- required time 17.200 arrival time -11.609 ------------------------------------------------------------------- slack 5.592 Slack (MET) : 6.161ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.434ns (logic 0.642ns (4.779%) route 12.792ns (95.221%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.265 10.939 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X118Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.748 18.073 clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X118Y23 FDCE (Recov_fdce_C_CLR) -0.405 17.099 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[6] ------------------------------------------------------------------- required time 17.099 arrival time -10.939 ------------------------------------------------------------------- slack 6.161 Slack (MET) : 6.161ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.434ns (logic 0.642ns (4.779%) route 12.792ns (95.221%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.265 10.939 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X118Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.748 18.073 clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X118Y23 FDCE (Recov_fdce_C_CLR) -0.405 17.099 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[7] ------------------------------------------------------------------- required time 17.099 arrival time -10.939 ------------------------------------------------------------------- slack 6.161 Slack (MET) : 6.161ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.434ns (logic 0.642ns (4.779%) route 12.792ns (95.221%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 9.265 10.939 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X118Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.748 18.073 clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X118Y23 FDCE (Recov_fdce_C_CLR) -0.405 17.099 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[8] ------------------------------------------------------------------- required time 17.099 arrival time -10.939 ------------------------------------------------------------------- slack 6.161 Slack (MET) : 6.495ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X117Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.748 18.073 clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X117Y23 FDCE (Recov_fdce_C_CLR) -0.405 17.099 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[5] ------------------------------------------------------------------- required time 17.099 arrival time -10.604 ------------------------------------------------------------------- slack 6.495 Slack (MET) : 6.495ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X117Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.748 18.073 clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X117Y23 FDCE (Recov_fdce_C_CLR) -0.405 17.099 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[9] ------------------------------------------------------------------- required time 17.099 arrival time -10.604 ------------------------------------------------------------------- slack 6.495 Slack (MET) : 6.495ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_sp_en_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X117Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_sp_en_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.748 18.073 clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X117Y23 FDCE (Recov_fdce_C_CLR) -0.405 17.099 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_sp_en_reg ------------------------------------------------------------------- required time 17.099 arrival time -10.604 ------------------------------------------------------------------- slack 6.495 Slack (MET) : 6.539ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.748 18.073 clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X116Y23 FDCE (Recov_fdce_C_CLR) -0.361 17.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[1] ------------------------------------------------------------------- required time 17.143 arrival time -10.604 ------------------------------------------------------------------- slack 6.539 Slack (MET) : 6.539ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.748 18.073 clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X116Y23 FDCE (Recov_fdce_C_CLR) -0.361 17.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[3] ------------------------------------------------------------------- required time 17.143 arrival time -10.604 ------------------------------------------------------------------- slack 6.539 Slack (MET) : 6.581ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.748 18.073 clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X116Y23 FDCE (Recov_fdce_C_CLR) -0.319 17.185 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[2] ------------------------------------------------------------------- required time 17.185 arrival time -10.604 ------------------------------------------------------------------- slack 6.581 Slack (MET) : 6.581ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 13.100ns (logic 0.642ns (4.901%) route 12.458ns (95.099%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.930 10.604 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y23 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.748 18.073 clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X116Y23 FDCE (Recov_fdce_C_CLR) -0.319 17.185 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[4] ------------------------------------------------------------------- required time 17.185 arrival time -10.604 ------------------------------------------------------------------- slack 6.581 Slack (MET) : 6.685ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.908ns (logic 0.642ns (4.974%) route 12.266ns (95.026%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.069ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns = ( 18.071 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.739 10.413 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X117Y25 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.746 18.071 clock pessimism -0.498 17.573 clock uncertainty -0.071 17.502 SLICE_X117Y25 FDCE (Recov_fdce_C_CLR) -0.405 17.097 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[7] ------------------------------------------------------------------- required time 17.097 arrival time -10.413 ------------------------------------------------------------------- slack 6.685 Slack (MET) : 6.685ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.908ns (logic 0.642ns (4.974%) route 12.266ns (95.026%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.069ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns = ( 18.071 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.739 10.413 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X117Y25 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.746 18.071 clock pessimism -0.498 17.573 clock uncertainty -0.071 17.502 SLICE_X117Y25 FDCE (Recov_fdce_C_CLR) -0.405 17.097 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[8] ------------------------------------------------------------------- required time 17.097 arrival time -10.413 ------------------------------------------------------------------- slack 6.685 Slack (MET) : 6.685ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.908ns (logic 0.642ns (4.974%) route 12.266ns (95.026%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.069ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns = ( 18.071 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.739 10.413 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X117Y25 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.746 18.071 clock pessimism -0.498 17.573 clock uncertainty -0.071 17.502 SLICE_X117Y25 FDCE (Recov_fdce_C_CLR) -0.405 17.097 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[9] ------------------------------------------------------------------- required time 17.097 arrival time -10.413 ------------------------------------------------------------------- slack 6.685 Slack (MET) : 6.771ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.908ns (logic 0.642ns (4.974%) route 12.266ns (95.026%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.069ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns = ( 18.071 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.739 10.413 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y25 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.746 18.071 clock pessimism -0.498 17.573 clock uncertainty -0.071 17.502 SLICE_X116Y25 FDCE (Recov_fdce_C_CLR) -0.319 17.183 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[6] ------------------------------------------------------------------- required time 17.183 arrival time -10.413 ------------------------------------------------------------------- slack 6.771 Slack (MET) : 6.831ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.850ns (logic 0.642ns (4.996%) route 12.208ns (95.004%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.680 10.354 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y26 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.748 18.073 clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X116Y26 FDCE (Recov_fdce_C_CLR) -0.319 17.185 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[4] ------------------------------------------------------------------- required time 17.185 arrival time -10.354 ------------------------------------------------------------------- slack 6.831 Slack (MET) : 6.831ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.850ns (logic 0.642ns (4.996%) route 12.208ns (95.004%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns = ( 18.073 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.680 10.354 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y26 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.748 18.073 clock pessimism -0.498 17.575 clock uncertainty -0.071 17.504 SLICE_X116Y26 FDCE (Recov_fdce_C_CLR) -0.319 17.185 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[5] ------------------------------------------------------------------- required time 17.185 arrival time -10.354 ------------------------------------------------------------------- slack 6.831 Slack (MET) : 6.839ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_do_en_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.803ns (logic 0.642ns (5.014%) route 12.161ns (94.986%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.074ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.924ns = ( 18.076 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.633 10.308 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y21 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_do_en_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.751 18.076 clock pessimism -0.498 17.578 clock uncertainty -0.071 17.507 SLICE_X116Y21 FDCE (Recov_fdce_C_CLR) -0.361 17.146 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_do_en_reg ------------------------------------------------------------------- required time 17.146 arrival time -10.308 ------------------------------------------------------------------- slack 6.839 Slack (MET) : 6.873ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[20]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.789ns (logic 0.642ns (5.020%) route 12.147ns (94.980%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns = ( 18.068 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.619 10.293 u_axi_ram/u_axi_sram_sp/prst SLICE_X0Y63 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.742 18.068 clock pessimism -0.426 17.641 clock uncertainty -0.071 17.571 SLICE_X0Y63 FDCE (Recov_fdce_C_CLR) -0.405 17.166 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[20] ------------------------------------------------------------------- required time 17.166 arrival time -10.293 ------------------------------------------------------------------- slack 6.873 Slack (MET) : 6.877ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[17]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.784ns (logic 0.642ns (5.022%) route 12.142ns (94.978%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns = ( 18.068 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.614 10.289 u_axi_ram/u_axi_sram_sp/prst SLICE_X1Y63 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.742 18.068 clock pessimism -0.426 17.641 clock uncertainty -0.071 17.571 SLICE_X1Y63 FDCE (Recov_fdce_C_CLR) -0.405 17.166 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[17] ------------------------------------------------------------------- required time 17.166 arrival time -10.289 ------------------------------------------------------------------- slack 6.877 Slack (MET) : 6.881ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.803ns (logic 0.642ns (5.014%) route 12.161ns (94.986%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.074ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.924ns = ( 18.076 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.633 10.308 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y21 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.751 18.076 clock pessimism -0.498 17.578 clock uncertainty -0.071 17.507 SLICE_X116Y21 FDCE (Recov_fdce_C_CLR) -0.319 17.188 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_count_reg[0] ------------------------------------------------------------------- required time 17.188 arrival time -10.308 ------------------------------------------------------------------- slack 6.881 Slack (MET) : 7.079ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.561ns (logic 0.642ns (5.111%) route 11.919ns (94.889%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.072ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.926ns = ( 18.074 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.392 10.066 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y27 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.749 18.074 clock pessimism -0.498 17.576 clock uncertainty -0.071 17.505 SLICE_X116Y27 FDCE (Recov_fdce_C_CLR) -0.361 17.144 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[1] ------------------------------------------------------------------- required time 17.144 arrival time -10.066 ------------------------------------------------------------------- slack 7.079 Slack (MET) : 7.079ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.561ns (logic 0.642ns (5.111%) route 11.919ns (94.889%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.072ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.926ns = ( 18.074 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.392 10.066 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y27 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.749 18.074 clock pessimism -0.498 17.576 clock uncertainty -0.071 17.505 SLICE_X116Y27 FDCE (Recov_fdce_C_CLR) -0.361 17.144 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[3] ------------------------------------------------------------------- required time 17.144 arrival time -10.066 ------------------------------------------------------------------- slack 7.079 Slack (MET) : 7.121ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.561ns (logic 0.642ns (5.111%) route 11.919ns (94.889%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.072ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.926ns = ( 18.074 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.392 10.066 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y27 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.749 18.074 clock pessimism -0.498 17.576 clock uncertainty -0.071 17.505 SLICE_X116Y27 FDCE (Recov_fdce_C_CLR) -0.319 17.186 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[0] ------------------------------------------------------------------- required time 17.186 arrival time -10.066 ------------------------------------------------------------------- slack 7.121 Slack (MET) : 7.121ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.561ns (logic 0.642ns (5.111%) route 11.919ns (94.889%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.072ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.926ns = ( 18.074 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.392 10.066 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/prst SLICE_X116Y27 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.749 18.074 clock pessimism -0.498 17.576 clock uncertainty -0.071 17.505 SLICE_X116Y27 FDCE (Recov_fdce_C_CLR) -0.319 17.186 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/di_count_reg[2] ------------------------------------------------------------------- required time 17.186 arrival time -10.066 ------------------------------------------------------------------- slack 7.121 Slack (MET) : 7.212ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.449ns (logic 0.642ns (5.157%) route 11.807ns (94.843%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.932ns = ( 18.068 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.279 9.954 u_axi_ram/u_axi_sram_sp/prst SLICE_X3Y64 FDCE f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.742 18.068 clock pessimism -0.426 17.641 clock uncertainty -0.071 17.571 SLICE_X3Y64 FDCE (Recov_fdce_C_CLR) -0.405 17.166 u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[5] ------------------------------------------------------------------- required time 17.166 arrival time -9.953 ------------------------------------------------------------------- slack 7.212 Slack (MET) : 7.487ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.173ns (logic 0.642ns (5.274%) route 11.531ns (94.726%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 18.067 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 8.003 9.678 u_axi_ram/u_axi_sram_sp/prst SLICE_X0Y65 FDCE f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.741 18.067 clock pessimism -0.426 17.640 clock uncertainty -0.071 17.570 SLICE_X0Y65 FDCE (Recov_fdce_C_CLR) -0.405 17.165 u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4] ------------------------------------------------------------------- required time 17.165 arrival time -9.678 ------------------------------------------------------------------- slack 7.487 Slack (MET) : 7.492ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.169ns (logic 0.642ns (5.276%) route 11.527ns (94.724%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 18.067 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.999 9.673 u_axi_ram/u_axi_sram_sp/prst SLICE_X1Y65 FDCE f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.741 18.067 clock pessimism -0.426 17.640 clock uncertainty -0.071 17.570 SLICE_X1Y65 FDCE (Recov_fdce_C_CLR) -0.405 17.165 u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[6] ------------------------------------------------------------------- required time 17.165 arrival time -9.673 ------------------------------------------------------------------- slack 7.492 Slack (MET) : 7.492ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.169ns (logic 0.642ns (5.276%) route 11.527ns (94.724%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.933ns = ( 18.067 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.999 9.673 u_axi_ram/u_axi_sram_sp/prst SLICE_X1Y65 FDCE f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.741 18.067 clock pessimism -0.426 17.640 clock uncertainty -0.071 17.570 SLICE_X1Y65 FDCE (Recov_fdce_C_CLR) -0.405 17.165 u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[7] ------------------------------------------------------------------- required time 17.165 arrival time -9.673 ------------------------------------------------------------------- slack 7.492 Slack (MET) : 7.555ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.945ns (logic 0.642ns (5.375%) route 11.303ns (94.625%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.775 9.449 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X80Y92 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.537 17.863 clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X80Y92 FDCE (Recov_fdce_C_CLR) -0.361 17.005 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[1] ------------------------------------------------------------------- required time 17.005 arrival time -9.449 ------------------------------------------------------------------- slack 7.555 Slack (MET) : 7.555ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.945ns (logic 0.642ns (5.375%) route 11.303ns (94.625%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.775 9.449 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X80Y92 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.537 17.863 clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X80Y92 FDCE (Recov_fdce_C_CLR) -0.361 17.005 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[3] ------------------------------------------------------------------- required time 17.005 arrival time -9.449 ------------------------------------------------------------------- slack 7.555 Slack (MET) : 7.566ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[13]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.087ns (logic 0.642ns (5.312%) route 11.445ns (94.688%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.128ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.941ns = ( 18.059 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.917 9.591 u_axi_ram/u_axi_sram_sp/prst SLICE_X5Y71 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.733 18.059 clock pessimism -0.426 17.632 clock uncertainty -0.071 17.562 SLICE_X5Y71 FDCE (Recov_fdce_C_CLR) -0.405 17.157 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[13] ------------------------------------------------------------------- required time 17.157 arrival time -9.591 ------------------------------------------------------------------- slack 7.566 Slack (MET) : 7.566ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[16]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.087ns (logic 0.642ns (5.312%) route 11.445ns (94.688%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.128ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.941ns = ( 18.059 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.917 9.591 u_axi_ram/u_axi_sram_sp/prst SLICE_X5Y71 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.733 18.059 clock pessimism -0.426 17.632 clock uncertainty -0.071 17.562 SLICE_X5Y71 FDCE (Recov_fdce_C_CLR) -0.405 17.157 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[16] ------------------------------------------------------------------- required time 17.157 arrival time -9.591 ------------------------------------------------------------------- slack 7.566 Slack (MET) : 7.566ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.087ns (logic 0.642ns (5.311%) route 11.445ns (94.689%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.129ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.940ns = ( 18.060 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.918 9.592 u_axi_ram/u_axi_sram_sp/prst SLICE_X5Y69 FDCE f u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.734 18.060 clock pessimism -0.426 17.633 clock uncertainty -0.071 17.563 SLICE_X5Y69 FDCE (Recov_fdce_C_CLR) -0.405 17.158 u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[7] ------------------------------------------------------------------- required time 17.158 arrival time -9.592 ------------------------------------------------------------------- slack 7.566 Slack (MET) : 7.597ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.945ns (logic 0.642ns (5.375%) route 11.303ns (94.625%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.775 9.449 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X80Y92 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.537 17.863 clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X80Y92 FDCE (Recov_fdce_C_CLR) -0.319 17.047 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[0] ------------------------------------------------------------------- required time 17.047 arrival time -9.449 ------------------------------------------------------------------- slack 7.597 Slack (MET) : 7.597ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.945ns (logic 0.642ns (5.375%) route 11.303ns (94.625%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.775 9.449 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X80Y92 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.537 17.863 clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X80Y92 FDCE (Recov_fdce_C_CLR) -0.319 17.047 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[2] ------------------------------------------------------------------- required time 17.047 arrival time -9.449 ------------------------------------------------------------------- slack 7.597 Slack (MET) : 7.597ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.945ns (logic 0.642ns (5.375%) route 11.303ns (94.625%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.775 9.449 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X80Y92 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.537 17.863 clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X80Y92 FDCE (Recov_fdce_C_CLR) -0.319 17.047 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[4] ------------------------------------------------------------------- required time 17.047 arrival time -9.449 ------------------------------------------------------------------- slack 7.597 Slack (MET) : 7.636ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.821ns (logic 0.642ns (5.431%) route 11.179ns (94.569%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.651 9.325 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X81Y91 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.537 17.863 clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X81Y91 FDCE (Recov_fdce_C_CLR) -0.405 16.961 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[6] ------------------------------------------------------------------- required time 16.961 arrival time -9.325 ------------------------------------------------------------------- slack 7.636 Slack (MET) : 7.636ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.821ns (logic 0.642ns (5.431%) route 11.179ns (94.569%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.651 9.325 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X81Y91 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.537 17.863 clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X81Y91 FDCE (Recov_fdce_C_CLR) -0.405 16.961 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[7] ------------------------------------------------------------------- required time 16.961 arrival time -9.325 ------------------------------------------------------------------- slack 7.636 Slack (MET) : 7.636ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.821ns (logic 0.642ns (5.431%) route 11.179ns (94.569%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.651 9.325 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X81Y91 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.537 17.863 clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X81Y91 FDCE (Recov_fdce_C_CLR) -0.405 16.961 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[8] ------------------------------------------------------------------- required time 16.961 arrival time -9.325 ------------------------------------------------------------------- slack 7.636 Slack (MET) : 7.636ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.821ns (logic 0.642ns (5.431%) route 11.179ns (94.569%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.651 9.325 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X81Y91 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.537 17.863 clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X81Y91 FDCE (Recov_fdce_C_CLR) -0.405 16.961 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[9] ------------------------------------------------------------------- required time 16.961 arrival time -9.325 ------------------------------------------------------------------- slack 7.636 Slack (MET) : 7.671ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_do_en_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.936ns (logic 0.642ns (5.379%) route 11.294ns (94.621%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.083ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.915ns = ( 18.085 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.766 9.440 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/prst SLICE_X114Y41 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_do_en_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.760 18.085 clock pessimism -0.498 17.587 clock uncertainty -0.071 17.516 SLICE_X114Y41 FDCE (Recov_fdce_C_CLR) -0.405 17.111 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_do_en_reg ------------------------------------------------------------------- required time 17.111 arrival time -9.440 ------------------------------------------------------------------- slack 7.671 Slack (MET) : 7.671ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/mu_do_en_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.936ns (logic 0.642ns (5.379%) route 11.294ns (94.621%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.083ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.915ns = ( 18.085 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.766 9.440 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/prst SLICE_X114Y41 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/mu_do_en_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.760 18.085 clock pessimism -0.498 17.587 clock uncertainty -0.071 17.516 SLICE_X114Y41 FDCE (Recov_fdce_C_CLR) -0.405 17.111 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/mu_do_en_reg ------------------------------------------------------------------- required time 17.111 arrival time -9.440 ------------------------------------------------------------------- slack 7.671 Slack (MET) : 7.722ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.821ns (logic 0.642ns (5.431%) route 11.179ns (94.569%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.137ns = ( 17.863 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.651 9.325 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X80Y91 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.537 17.863 clock pessimism -0.426 17.436 clock uncertainty -0.071 17.366 SLICE_X80Y91 FDCE (Recov_fdce_C_CLR) -0.319 17.047 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/di_count_reg[5] ------------------------------------------------------------------- required time 17.047 arrival time -9.325 ------------------------------------------------------------------- slack 7.722 Slack (MET) : 7.899ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.765ns (logic 0.642ns (5.457%) route 11.123ns (94.543%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns = ( 18.071 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.595 9.270 u_confreg/u_digitaltube_controller/prst SLICE_X1Y59 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.745 18.071 clock pessimism -0.426 17.644 clock uncertainty -0.071 17.574 SLICE_X1Y59 FDCE (Recov_fdce_C_CLR) -0.405 17.169 u_confreg/u_digitaltube_controller/dpy1_reg_reg[2] ------------------------------------------------------------------- required time 17.169 arrival time -9.270 ------------------------------------------------------------------- slack 7.899 Slack (MET) : 7.899ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.765ns (logic 0.642ns (5.457%) route 11.123ns (94.543%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns = ( 18.071 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.595 9.270 u_confreg/u_digitaltube_controller/prst SLICE_X1Y59 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.745 18.071 clock pessimism -0.426 17.644 clock uncertainty -0.071 17.574 SLICE_X1Y59 FDCE (Recov_fdce_C_CLR) -0.405 17.169 u_confreg/u_digitaltube_controller/dpy1_reg_reg[4] ------------------------------------------------------------------- required time 17.169 arrival time -9.270 ------------------------------------------------------------------- slack 7.899 Slack (MET) : 7.899ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.765ns (logic 0.642ns (5.457%) route 11.123ns (94.543%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.929ns = ( 18.071 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.595 9.270 u_confreg/u_digitaltube_controller/prst SLICE_X1Y59 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.745 18.071 clock pessimism -0.426 17.644 clock uncertainty -0.071 17.574 SLICE_X1Y59 FDCE (Recov_fdce_C_CLR) -0.405 17.169 u_confreg/u_digitaltube_controller/dpy1_reg_reg[6] ------------------------------------------------------------------- required time 17.169 arrival time -9.270 ------------------------------------------------------------------- slack 7.899 Slack (MET) : 7.944ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.508ns (logic 0.642ns (5.579%) route 10.866ns (94.421%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.073ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.142ns = ( 17.858 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.338 9.012 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X81Y65 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.532 17.858 clock pessimism -0.426 17.431 clock uncertainty -0.071 17.361 SLICE_X81Y65 FDCE (Recov_fdce_C_CLR) -0.405 16.956 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7] ------------------------------------------------------------------- required time 16.956 arrival time -9.012 ------------------------------------------------------------------- slack 7.944 Slack (MET) : 7.944ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.508ns (logic 0.642ns (5.579%) route 10.866ns (94.421%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.073ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.142ns = ( 17.858 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.338 9.012 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X81Y65 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.532 17.858 clock pessimism -0.426 17.431 clock uncertainty -0.071 17.361 SLICE_X81Y65 FDCE (Recov_fdce_C_CLR) -0.405 16.956 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8] ------------------------------------------------------------------- required time 16.956 arrival time -9.012 ------------------------------------------------------------------- slack 7.944 Slack (MET) : 7.944ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.508ns (logic 0.642ns (5.579%) route 10.866ns (94.421%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.073ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.142ns = ( 17.858 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.338 9.012 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X81Y65 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.532 17.858 clock pessimism -0.426 17.431 clock uncertainty -0.071 17.361 SLICE_X81Y65 FDCE (Recov_fdce_C_CLR) -0.405 16.956 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9] ------------------------------------------------------------------- required time 16.956 arrival time -9.012 ------------------------------------------------------------------- slack 7.944 Slack (MET) : 8.184ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[19]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.480ns (logic 0.642ns (5.593%) route 10.838ns (94.407%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.930ns = ( 18.070 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.310 8.984 u_axi_ram/u_axi_sram_sp/prst SLICE_X3Y61 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.744 18.070 clock pessimism -0.426 17.643 clock uncertainty -0.071 17.573 SLICE_X3Y61 FDCE (Recov_fdce_C_CLR) -0.405 17.168 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[19] ------------------------------------------------------------------- required time 17.168 arrival time -8.984 ------------------------------------------------------------------- slack 8.184 Slack (MET) : 8.184ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.480ns (logic 0.642ns (5.593%) route 10.838ns (94.407%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.930ns = ( 18.070 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.310 8.984 u_axi_ram/u_axi_sram_sp/prst SLICE_X3Y61 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.744 18.070 clock pessimism -0.426 17.643 clock uncertainty -0.071 17.573 SLICE_X3Y61 FDCE (Recov_fdce_C_CLR) -0.405 17.168 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[6] ------------------------------------------------------------------- required time 17.168 arrival time -8.984 ------------------------------------------------------------------- slack 8.184 Slack (MET) : 8.207ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.451ns (logic 0.642ns (5.607%) route 10.809ns (94.393%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.936ns = ( 18.064 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.281 8.955 u_confreg/u_int_ctrl/prst SLICE_X5Y66 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.738 18.064 clock pessimism -0.426 17.637 clock uncertainty -0.071 17.567 SLICE_X5Y66 FDCE (Recov_fdce_C_CLR) -0.405 17.162 u_confreg/u_int_ctrl/int_in_sync_d1_reg[2] ------------------------------------------------------------------- required time 17.162 arrival time -8.955 ------------------------------------------------------------------- slack 8.207 Slack (MET) : 8.207ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[18]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.455ns (logic 0.642ns (5.604%) route 10.813ns (94.396%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns = ( 18.069 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.286 8.960 u_axi_ram/u_axi_sram_sp/prst SLICE_X0Y62 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.743 18.069 clock pessimism -0.426 17.642 clock uncertainty -0.071 17.572 SLICE_X0Y62 FDCE (Recov_fdce_C_CLR) -0.405 17.167 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[18] ------------------------------------------------------------------- required time 17.167 arrival time -8.960 ------------------------------------------------------------------- slack 8.207 Slack (MET) : 8.227ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.522ns (logic 0.642ns (5.572%) route 10.880ns (94.428%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns = ( 18.069 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.352 9.026 u_axi_ram/u_axi_sram_sp/prst SLICE_X2Y62 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.743 18.069 clock pessimism -0.426 17.642 clock uncertainty -0.071 17.572 SLICE_X2Y62 FDCE (Recov_fdce_C_CLR) -0.319 17.253 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[3] ------------------------------------------------------------------- required time 17.253 arrival time -9.026 ------------------------------------------------------------------- slack 8.227 Slack (MET) : 8.227ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.522ns (logic 0.642ns (5.572%) route 10.880ns (94.428%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns = ( 18.069 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 7.352 9.026 u_axi_ram/u_axi_sram_sp/prst SLICE_X2Y62 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.743 18.069 clock pessimism -0.426 17.642 clock uncertainty -0.071 17.572 SLICE_X2Y62 FDCE (Recov_fdce_C_CLR) -0.319 17.253 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[5] ------------------------------------------------------------------- required time 17.253 arrival time -9.026 ------------------------------------------------------------------- slack 8.227 Slack (MET) : 8.375ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.088ns (logic 0.642ns (5.790%) route 10.446ns (94.210%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.130ns = ( 17.870 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.919 8.593 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X75Y86 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.544 17.870 clock pessimism -0.426 17.443 clock uncertainty -0.071 17.373 SLICE_X75Y86 FDCE (Recov_fdce_C_CLR) -0.405 16.968 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[7] ------------------------------------------------------------------- required time 16.968 arrival time -8.593 ------------------------------------------------------------------- slack 8.375 Slack (MET) : 8.375ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.088ns (logic 0.642ns (5.790%) route 10.446ns (94.210%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.130ns = ( 17.870 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.919 8.593 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X75Y86 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.544 17.870 clock pessimism -0.426 17.443 clock uncertainty -0.071 17.373 SLICE_X75Y86 FDCE (Recov_fdce_C_CLR) -0.405 16.968 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[8] ------------------------------------------------------------------- required time 16.968 arrival time -8.593 ------------------------------------------------------------------- slack 8.375 Slack (MET) : 8.375ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.088ns (logic 0.642ns (5.790%) route 10.446ns (94.210%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.130ns = ( 17.870 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.919 8.593 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X75Y86 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.544 17.870 clock pessimism -0.426 17.443 clock uncertainty -0.071 17.373 SLICE_X75Y86 FDCE (Recov_fdce_C_CLR) -0.405 16.968 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[9] ------------------------------------------------------------------- required time 16.968 arrival time -8.593 ------------------------------------------------------------------- slack 8.375 Slack (MET) : 8.517ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.948ns (logic 0.642ns (5.864%) route 10.306ns (94.136%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.129ns = ( 17.871 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.778 8.452 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X75Y87 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.545 17.871 clock pessimism -0.426 17.444 clock uncertainty -0.071 17.374 SLICE_X75Y87 FDCE (Recov_fdce_C_CLR) -0.405 16.969 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[5] ------------------------------------------------------------------- required time 16.969 arrival time -8.452 ------------------------------------------------------------------- slack 8.517 Slack (MET) : 8.517ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.948ns (logic 0.642ns (5.864%) route 10.306ns (94.136%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.129ns = ( 17.871 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.778 8.452 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X75Y87 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.545 17.871 clock pessimism -0.426 17.444 clock uncertainty -0.071 17.374 SLICE_X75Y87 FDCE (Recov_fdce_C_CLR) -0.405 16.969 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[6] ------------------------------------------------------------------- required time 16.969 arrival time -8.452 ------------------------------------------------------------------- slack 8.517 Slack (MET) : 8.519ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.948ns (logic 0.642ns (5.864%) route 10.306ns (94.136%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.778 8.452 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X75Y89 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.547 17.873 clock pessimism -0.426 17.446 clock uncertainty -0.071 17.376 SLICE_X75Y89 FDCE (Recov_fdce_C_CLR) -0.405 16.971 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[0] ------------------------------------------------------------------- required time 16.971 arrival time -8.452 ------------------------------------------------------------------- slack 8.519 Slack (MET) : 8.519ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.948ns (logic 0.642ns (5.864%) route 10.306ns (94.136%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.778 8.452 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X75Y89 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.547 17.873 clock pessimism -0.426 17.446 clock uncertainty -0.071 17.376 SLICE_X75Y89 FDCE (Recov_fdce_C_CLR) -0.405 16.971 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[1] ------------------------------------------------------------------- required time 16.971 arrival time -8.452 ------------------------------------------------------------------- slack 8.519 Slack (MET) : 8.519ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.948ns (logic 0.642ns (5.864%) route 10.306ns (94.136%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.778 8.452 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X75Y89 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.547 17.873 clock pessimism -0.426 17.446 clock uncertainty -0.071 17.376 SLICE_X75Y89 FDCE (Recov_fdce_C_CLR) -0.405 16.971 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[2] ------------------------------------------------------------------- required time 16.971 arrival time -8.452 ------------------------------------------------------------------- slack 8.519 Slack (MET) : 8.519ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.948ns (logic 0.642ns (5.864%) route 10.306ns (94.136%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.778 8.452 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X75Y89 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.547 17.873 clock pessimism -0.426 17.446 clock uncertainty -0.071 17.376 SLICE_X75Y89 FDCE (Recov_fdce_C_CLR) -0.405 16.971 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[3] ------------------------------------------------------------------- required time 16.971 arrival time -8.452 ------------------------------------------------------------------- slack 8.519 Slack (MET) : 8.519ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.948ns (logic 0.642ns (5.864%) route 10.306ns (94.136%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.778 8.452 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X75Y89 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.547 17.873 clock pessimism -0.426 17.446 clock uncertainty -0.071 17.376 SLICE_X75Y89 FDCE (Recov_fdce_C_CLR) -0.405 16.971 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[4] ------------------------------------------------------------------- required time 16.971 arrival time -8.452 ------------------------------------------------------------------- slack 8.519 Slack (MET) : 8.519ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_en_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.948ns (logic 0.642ns (5.864%) route 10.306ns (94.136%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.778 8.452 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/prst SLICE_X75Y89 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_en_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.547 17.873 clock pessimism -0.426 17.446 clock uncertainty -0.071 17.376 SLICE_X75Y89 FDCE (Recov_fdce_C_CLR) -0.405 16.971 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_en_reg ------------------------------------------------------------------- required time 16.971 arrival time -8.452 ------------------------------------------------------------------- slack 8.519 Slack (MET) : 8.522ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 10.488ns (logic 0.642ns (6.121%) route 9.846ns (93.879%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns = ( 37.717 - 40.000 ) Source Clock Delay (SCD): -2.496ns = ( 17.504 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -6.275 13.725 propagated clock network latency 3.780 17.504 SLICE_X56Y97 FDCE 0.000 17.504 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 18.022 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 21.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 21.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.318 27.992 pll_clk.u_rst_mlkem/prst SLICE_X67Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.392 37.717 clock pessimism -0.601 37.116 clock uncertainty -0.197 36.920 SLICE_X67Y102 FDCE (Recov_fdce_C_CLR) -0.405 36.515 pll_clk.u_rst_mlkem/delay_reg[0] ------------------------------------------------------------------- required time 36.515 arrival time -27.992 ------------------------------------------------------------------- slack 8.522 Slack (MET) : 8.522ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) Data Path Delay: 10.488ns (logic 0.642ns (6.121%) route 9.846ns (93.879%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns = ( 37.717 - 40.000 ) Source Clock Delay (SCD): -2.496ns = ( 17.504 - 20.000 ) Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -6.275 13.725 propagated clock network latency 3.780 17.504 SLICE_X56Y97 FDCE 0.000 17.504 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 18.022 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 21.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 21.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.318 27.992 pll_clk.u_rst_mlkem/prst SLICE_X67Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.392 37.717 clock pessimism -0.601 37.116 clock uncertainty -0.197 36.920 SLICE_X67Y102 FDCE (Recov_fdce_C_CLR) -0.405 36.515 pll_clk.u_rst_mlkem/delay_reg[1] ------------------------------------------------------------------- required time 36.515 arrival time -27.992 ------------------------------------------------------------------- slack 8.522 Slack (MET) : 8.539ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/sys_timer_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.087ns (logic 0.642ns (5.790%) route 10.445ns (94.210%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.917 8.592 u_confreg/prst SLICE_X8Y62 FDCE f u_confreg/sys_timer_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.663 17.989 clock pessimism -0.426 17.562 clock uncertainty -0.071 17.492 SLICE_X8Y62 FDCE (Recov_fdce_C_CLR) -0.361 17.131 u_confreg/sys_timer_reg[1] ------------------------------------------------------------------- required time 17.131 arrival time -8.592 ------------------------------------------------------------------- slack 8.539 Slack (MET) : 8.539ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/sys_timer_reg[8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.087ns (logic 0.642ns (5.790%) route 10.445ns (94.210%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.917 8.592 u_confreg/prst SLICE_X8Y62 FDCE f u_confreg/sys_timer_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.663 17.989 clock pessimism -0.426 17.562 clock uncertainty -0.071 17.492 SLICE_X8Y62 FDCE (Recov_fdce_C_CLR) -0.361 17.131 u_confreg/sys_timer_reg[8] ------------------------------------------------------------------- required time 17.131 arrival time -8.592 ------------------------------------------------------------------- slack 8.539 Slack (MET) : 8.539ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/timer_int_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.087ns (logic 0.642ns (5.790%) route 10.445ns (94.210%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.917 8.592 u_confreg/prst SLICE_X8Y62 FDCE f u_confreg/timer_int_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.663 17.989 clock pessimism -0.426 17.562 clock uncertainty -0.071 17.492 SLICE_X8Y62 FDCE (Recov_fdce_C_CLR) -0.361 17.131 u_confreg/timer_int_reg ------------------------------------------------------------------- required time 17.131 arrival time -8.592 ------------------------------------------------------------------- slack 8.539 Slack (MET) : 8.553ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/_zz_cmdAllowedStart_reg/PRE (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.071ns (logic 0.642ns (5.799%) route 10.429ns (94.201%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.901 8.575 u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/prst SLICE_X18Y66 FDPE f u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/_zz_cmdAllowedStart_reg/PRE ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.660 17.986 clock pessimism -0.426 17.559 clock uncertainty -0.071 17.489 SLICE_X18Y66 FDPE (Recov_fdpe_C_PRE) -0.361 17.128 u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/_zz_cmdAllowedStart_reg ------------------------------------------------------------------- required time 17.128 arrival time -8.575 ------------------------------------------------------------------- slack 8.553 Slack (MET) : 8.553ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/pendingDataCounter_value_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.071ns (logic 0.642ns (5.799%) route 10.429ns (94.201%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.901 8.575 u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/prst SLICE_X18Y66 FDCE f u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/pendingDataCounter_value_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.660 17.986 clock pessimism -0.426 17.559 clock uncertainty -0.071 17.489 SLICE_X18Y66 FDCE (Recov_fdce_C_CLR) -0.361 17.128 u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/pendingDataCounter_value_reg[1] ------------------------------------------------------------------- required time 17.128 arrival time -8.575 ------------------------------------------------------------------- slack 8.553 Slack (MET) : 8.581ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/sys_timer_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.087ns (logic 0.642ns (5.790%) route 10.445ns (94.210%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.917 8.592 u_confreg/prst SLICE_X8Y62 FDCE f u_confreg/sys_timer_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.663 17.989 clock pessimism -0.426 17.562 clock uncertainty -0.071 17.492 SLICE_X8Y62 FDCE (Recov_fdce_C_CLR) -0.319 17.173 u_confreg/sys_timer_reg[0] ------------------------------------------------------------------- required time 17.173 arrival time -8.592 ------------------------------------------------------------------- slack 8.581 Slack (MET) : 8.581ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/sys_timer_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.087ns (logic 0.642ns (5.790%) route 10.445ns (94.210%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.917 8.592 u_confreg/prst SLICE_X8Y62 FDCE f u_confreg/sys_timer_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.663 17.989 clock pessimism -0.426 17.562 clock uncertainty -0.071 17.492 SLICE_X8Y62 FDCE (Recov_fdce_C_CLR) -0.319 17.173 u_confreg/sys_timer_reg[5] ------------------------------------------------------------------- required time 17.173 arrival time -8.592 ------------------------------------------------------------------- slack 8.581 Slack (MET) : 8.581ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/sys_timer_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.087ns (logic 0.642ns (5.790%) route 10.445ns (94.210%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.917 8.592 u_confreg/prst SLICE_X8Y62 FDCE f u_confreg/sys_timer_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.663 17.989 clock pessimism -0.426 17.562 clock uncertainty -0.071 17.492 SLICE_X8Y62 FDCE (Recov_fdce_C_CLR) -0.319 17.173 u_confreg/sys_timer_reg[7] ------------------------------------------------------------------- required time 17.173 arrival time -8.592 ------------------------------------------------------------------- slack 8.581 Slack (MET) : 8.595ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/pendingDataCounter_value_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.071ns (logic 0.642ns (5.799%) route 10.429ns (94.201%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.901 8.575 u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/prst SLICE_X18Y66 FDCE f u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/pendingDataCounter_value_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.660 17.986 clock pessimism -0.426 17.559 clock uncertainty -0.071 17.489 SLICE_X18Y66 FDCE (Recov_fdce_C_CLR) -0.319 17.170 u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/pendingDataCounter_value_reg[0] ------------------------------------------------------------------- required time 17.170 arrival time -8.575 ------------------------------------------------------------------- slack 8.595 Slack (MET) : 8.595ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/pendingDataCounter_value_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.071ns (logic 0.642ns (5.799%) route 10.429ns (94.201%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.901 8.575 u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/prst SLICE_X18Y66 FDCE f u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/pendingDataCounter_value_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.660 17.986 clock pessimism -0.426 17.559 clock uncertainty -0.071 17.489 SLICE_X18Y66 FDCE (Recov_fdce_C_CLR) -0.319 17.170 u_AxiCrossbar_2x8/axiIn_0_writeOnly_decoder/pendingDataCounter_value_reg[2] ------------------------------------------------------------------- required time 17.170 arrival time -8.575 ------------------------------------------------------------------- slack 8.595 Slack (MET) : 8.624ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/sys_timer_reg[25]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.955ns (logic 0.642ns (5.860%) route 10.313ns (94.140%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.785 8.459 u_confreg/prst SLICE_X11Y67 FDCE f u_confreg/sys_timer_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.660 17.986 clock pessimism -0.426 17.559 clock uncertainty -0.071 17.489 SLICE_X11Y67 FDCE (Recov_fdce_C_CLR) -0.405 17.084 u_confreg/sys_timer_reg[25] ------------------------------------------------------------------- required time 17.084 arrival time -8.459 ------------------------------------------------------------------- slack 8.624 Slack (MET) : 8.624ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/sys_timer_reg[26]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.955ns (logic 0.642ns (5.860%) route 10.313ns (94.140%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.785 8.459 u_confreg/prst SLICE_X11Y67 FDCE f u_confreg/sys_timer_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.660 17.986 clock pessimism -0.426 17.559 clock uncertainty -0.071 17.489 SLICE_X11Y67 FDCE (Recov_fdce_C_CLR) -0.405 17.084 u_confreg/sys_timer_reg[26] ------------------------------------------------------------------- required time 17.084 arrival time -8.459 ------------------------------------------------------------------- slack 8.624 Slack (MET) : 8.624ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/sys_timer_reg[30]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.955ns (logic 0.642ns (5.860%) route 10.313ns (94.140%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.785 8.459 u_confreg/prst SLICE_X11Y67 FDCE f u_confreg/sys_timer_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.660 17.986 clock pessimism -0.426 17.559 clock uncertainty -0.071 17.489 SLICE_X11Y67 FDCE (Recov_fdce_C_CLR) -0.405 17.084 u_confreg/sys_timer_reg[30] ------------------------------------------------------------------- required time 17.084 arrival time -8.459 ------------------------------------------------------------------- slack 8.624 Slack (MET) : 8.661ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/req_addr_q_reg[10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.998ns (logic 0.642ns (5.837%) route 10.356ns (94.163%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns = ( 18.066 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.829 8.503 u_axi_ram/u_axi_sram_sp/prst SLICE_X7Y64 FDCE f u_axi_ram/u_axi_sram_sp/req_addr_q_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.740 18.066 clock pessimism -0.426 17.639 clock uncertainty -0.071 17.569 SLICE_X7Y64 FDCE (Recov_fdce_C_CLR) -0.405 17.164 u_axi_ram/u_axi_sram_sp/req_addr_q_reg[10] ------------------------------------------------------------------- required time 17.164 arrival time -8.503 ------------------------------------------------------------------- slack 8.661 Slack (MET) : 8.743ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.922ns (logic 0.642ns (5.878%) route 10.280ns (94.122%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.752 8.427 u_axi_ram/u_axi_sram_sp/prst SLICE_X20Y65 FDCE f u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.660 17.986 clock pessimism -0.426 17.559 clock uncertainty -0.071 17.489 SLICE_X20Y65 FDCE (Recov_fdce_C_CLR) -0.319 17.170 u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[1] ------------------------------------------------------------------- required time 17.170 arrival time -8.427 ------------------------------------------------------------------- slack 8.743 Slack (MET) : 8.743ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.919ns (logic 0.642ns (5.880%) route 10.277ns (94.120%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns = ( 18.069 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.749 8.423 u_confreg/u_int_ctrl/prst SLICE_X7Y60 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.743 18.069 clock pessimism -0.426 17.642 clock uncertainty -0.071 17.572 SLICE_X7Y60 FDCE (Recov_fdce_C_CLR) -0.405 17.167 u_confreg/u_int_ctrl/edge_int_state_reg[3] ------------------------------------------------------------------- required time 17.167 arrival time -8.423 ------------------------------------------------------------------- slack 8.743 Slack (MET) : 8.743ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.919ns (logic 0.642ns (5.880%) route 10.277ns (94.120%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns = ( 18.069 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.749 8.423 u_confreg/u_int_ctrl/prst SLICE_X7Y60 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.743 18.069 clock pessimism -0.426 17.642 clock uncertainty -0.071 17.572 SLICE_X7Y60 FDCE (Recov_fdce_C_CLR) -0.405 17.167 u_confreg/u_int_ctrl/int_in_sync_d2_reg[3] ------------------------------------------------------------------- required time 17.167 arrival time -8.423 ------------------------------------------------------------------- slack 8.743 Slack (MET) : 8.743ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.919ns (logic 0.642ns (5.880%) route 10.277ns (94.120%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns = ( 18.069 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.749 8.423 u_confreg/u_int_ctrl/prst SLICE_X7Y60 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.743 18.069 clock pessimism -0.426 17.642 clock uncertainty -0.071 17.572 SLICE_X7Y60 FDCE (Recov_fdce_C_CLR) -0.405 17.167 u_confreg/u_int_ctrl/int_in_sync_d3_reg[3] ------------------------------------------------------------------- required time 17.167 arrival time -8.423 ------------------------------------------------------------------- slack 8.743 Slack (MET) : 8.747ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[17]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.998ns (logic 0.642ns (5.837%) route 10.356ns (94.163%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.934ns = ( 18.066 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.829 8.503 u_axi_ram/u_axi_sram_sp/prst SLICE_X6Y64 FDCE f u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.740 18.066 clock pessimism -0.426 17.639 clock uncertainty -0.071 17.569 SLICE_X6Y64 FDCE (Recov_fdce_C_CLR) -0.319 17.250 u_axi_ram/u_axi_sram_sp/ax_req_q_addr_reg[17] ------------------------------------------------------------------- required time 17.250 arrival time -8.503 ------------------------------------------------------------------- slack 8.747 Slack (MET) : 8.777ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_AxiCrossbar_2x8/toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_rValid_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.800ns (logic 0.642ns (5.944%) route 10.158ns (94.056%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.016ns = ( 17.984 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.630 8.305 u_AxiCrossbar_2x8/prst SLICE_X11Y68 FDCE f u_AxiCrossbar_2x8/toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.658 17.984 clock pessimism -0.426 17.557 clock uncertainty -0.071 17.487 SLICE_X11Y68 FDCE (Recov_fdce_C_CLR) -0.405 17.082 u_AxiCrossbar_2x8/toplevel_axiIn_0_writeOnly_decoder_io_outputs_0_aw_rValid_reg ------------------------------------------------------------------- required time 17.082 arrival time -8.305 ------------------------------------------------------------------- slack 8.777 Slack (MET) : 8.777ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[27]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.800ns (logic 0.642ns (5.944%) route 10.158ns (94.056%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.016ns = ( 17.984 - 20.000 ) Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.780 -2.496 SLICE_X56Y97 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.518 -1.978 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 3.528 1.550 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.124 1.674 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 6.630 8.305 u_confreg/u_int_ctrl/prst SLICE_X11Y68 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency 3.658 17.984 clock pessimism -0.426 17.557 clock uncertainty -0.071 17.487 SLICE_X11Y68 FDCE (Recov_fdce_C_CLR) -0.405 17.082 u_confreg/u_int_ctrl/edge_int_state_reg[27] ------------------------------------------------------------------- required time 17.082 arrival time -8.305 ------------------------------------------------------------------- slack 8.777 Slack (MET) : 12.906ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.488ns (logic 1.164ns (4.394%) route 25.324ns (95.606%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400] ------------------------------------------------------------------- required time 36.872 arrival time -23.966 ------------------------------------------------------------------- slack 12.906 Slack (MET) : 12.906ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.488ns (logic 1.164ns (4.394%) route 25.324ns (95.606%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400] ------------------------------------------------------------------- required time 36.872 arrival time -23.966 ------------------------------------------------------------------- slack 12.906 Slack (MET) : 12.906ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.488ns (logic 1.164ns (4.394%) route 25.324ns (95.606%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592] ------------------------------------------------------------------- required time 36.872 arrival time -23.966 ------------------------------------------------------------------- slack 12.906 Slack (MET) : 12.906ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.488ns (logic 1.164ns (4.394%) route 25.324ns (95.606%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592] ------------------------------------------------------------------- required time 36.872 arrival time -23.966 ------------------------------------------------------------------- slack 12.906 Slack (MET) : 12.985ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.751ns (logic 1.556ns (5.817%) route 25.195ns (94.183%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.245 21.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X123Y140 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[602]_i_3/I3 SLICE_X123Y140 LUT4 (Prop_lut4_I3_O) 0.118 21.502 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[602]_i_3/O net (fo=1, routed) 1.525 23.027 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[602] SLICE_X132Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[602]_i_2/I0 SLICE_X132Y158 LUT6 (Prop_lut6_I0_O) 0.326 23.353 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[602]_i_2/O net (fo=1, routed) 0.757 24.111 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[341] SLICE_X134Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[602]_i_1/I1 SLICE_X134Y155 LUT3 (Prop_lut3_I1_O) 0.118 24.229 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[602]_i_1/O net (fo=1, routed) 0.000 24.229 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[602] SLICE_X134Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X134Y155 FDCE (Setup_fdce_C_D) 0.075 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602] ------------------------------------------------------------------- required time 37.213 arrival time -24.229 ------------------------------------------------------------------- slack 12.985 Slack (MET) : 12.985ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.751ns (logic 1.556ns (5.817%) route 25.195ns (94.183%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.245 21.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X123Y140 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[602]_i_3/I3 SLICE_X123Y140 LUT4 (Prop_lut4_I3_O) 0.118 21.502 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[602]_i_3/O net (fo=1, routed) 1.525 23.027 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[602] SLICE_X132Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[602]_i_2/I0 SLICE_X132Y158 LUT6 (Prop_lut6_I0_O) 0.326 23.353 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[602]_i_2/O net (fo=1, routed) 0.757 24.111 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[341] SLICE_X134Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[602]_i_1/I1 SLICE_X134Y155 LUT3 (Prop_lut3_I1_O) 0.118 24.229 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[602]_i_1/O net (fo=1, routed) 0.000 24.229 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[602] SLICE_X134Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X134Y155 FDCE (Setup_fdce_C_D) 0.075 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[602] ------------------------------------------------------------------- required time 37.213 arrival time -24.229 ------------------------------------------------------------------- slack 12.985 Slack (MET) : 12.994ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.404ns (logic 1.164ns (4.408%) route 25.240ns (95.592%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.279 23.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X153Y128 FDCE (Setup_fdce_C_CE) -0.413 36.875 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527] ------------------------------------------------------------------- required time 36.875 arrival time -23.881 ------------------------------------------------------------------- slack 12.994 Slack (MET) : 12.994ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.404ns (logic 1.164ns (4.408%) route 25.240ns (95.592%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.279 23.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X153Y128 FDCE (Setup_fdce_C_CE) -0.413 36.875 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527] ------------------------------------------------------------------- required time 36.875 arrival time -23.881 ------------------------------------------------------------------- slack 12.994 Slack (MET) : 13.047ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.784ns (logic 1.624ns (6.063%) route 25.160ns (93.937%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.255ns = ( 37.745 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.176 20.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X119Y148 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[795]_i_3/I3 SLICE_X119Y148 LUT4 (Prop_lut4_I3_O) 0.152 20.467 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[795]_i_3/O net (fo=1, routed) 1.499 21.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[795] SLICE_X120Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[795]_i_2/I0 SLICE_X120Y158 LUT6 (Prop_lut6_I0_O) 0.326 22.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[795]_i_2/O net (fo=1, routed) 1.818 24.110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[534] SLICE_X131Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[795]_i_1/I1 SLICE_X131Y145 LUT3 (Prop_lut3_I1_O) 0.152 24.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[795]_i_1/O net (fo=1, routed) 0.000 24.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[795] SLICE_X131Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.420 37.745 clock pessimism -0.435 37.310 clock uncertainty -0.077 37.234 SLICE_X131Y145 FDCE (Setup_fdce_C_D) 0.075 37.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795] ------------------------------------------------------------------- required time 37.309 arrival time -24.262 ------------------------------------------------------------------- slack 13.047 Slack (MET) : 13.047ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.784ns (logic 1.624ns (6.063%) route 25.160ns (93.937%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.255ns = ( 37.745 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.176 20.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X119Y148 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[795]_i_3/I3 SLICE_X119Y148 LUT4 (Prop_lut4_I3_O) 0.152 20.467 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[795]_i_3/O net (fo=1, routed) 1.499 21.966 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[795] SLICE_X120Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[795]_i_2/I0 SLICE_X120Y158 LUT6 (Prop_lut6_I0_O) 0.326 22.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[795]_i_2/O net (fo=1, routed) 1.818 24.110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[534] SLICE_X131Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[795]_i_1/I1 SLICE_X131Y145 LUT3 (Prop_lut3_I1_O) 0.152 24.262 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[795]_i_1/O net (fo=1, routed) 0.000 24.262 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[795] SLICE_X131Y145 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.420 37.745 clock pessimism -0.435 37.310 clock uncertainty -0.077 37.234 SLICE_X131Y145 FDCE (Setup_fdce_C_D) 0.075 37.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[795] ------------------------------------------------------------------- required time 37.309 arrival time -24.262 ------------------------------------------------------------------- slack 13.047 Slack (MET) : 13.154ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.538ns (logic 1.562ns (5.886%) route 24.976ns (94.114%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.901 21.041 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X130Y146 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[629]_i_3/I3 SLICE_X130Y146 LUT4 (Prop_lut4_I3_O) 0.118 21.159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[629]_i_3/O net (fo=1, routed) 1.198 22.357 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[629] SLICE_X134Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[629]_i_2/I0 SLICE_X134Y157 LUT6 (Prop_lut6_I0_O) 0.326 22.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[629]_i_2/O net (fo=1, routed) 1.209 23.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[368] SLICE_X134Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[629]_i_1/I1 SLICE_X134Y155 LUT3 (Prop_lut3_I1_O) 0.124 24.016 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[629]_i_1/O net (fo=1, routed) 0.000 24.016 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[629] SLICE_X134Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X134Y155 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629] ------------------------------------------------------------------- required time 37.169 arrival time -24.016 ------------------------------------------------------------------- slack 13.154 Slack (MET) : 13.154ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.538ns (logic 1.562ns (5.886%) route 24.976ns (94.114%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.901 21.041 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X130Y146 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[629]_i_3/I3 SLICE_X130Y146 LUT4 (Prop_lut4_I3_O) 0.118 21.159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[629]_i_3/O net (fo=1, routed) 1.198 22.357 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[629] SLICE_X134Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[629]_i_2/I0 SLICE_X134Y157 LUT6 (Prop_lut6_I0_O) 0.326 22.683 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[629]_i_2/O net (fo=1, routed) 1.209 23.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[368] SLICE_X134Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[629]_i_1/I1 SLICE_X134Y155 LUT3 (Prop_lut3_I1_O) 0.124 24.016 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[629]_i_1/O net (fo=1, routed) 0.000 24.016 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[629] SLICE_X134Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X134Y155 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[629] ------------------------------------------------------------------- required time 37.169 arrival time -24.016 ------------------------------------------------------------------- slack 13.154 Slack (MET) : 13.175ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.605ns (logic 1.612ns (6.059%) route 24.993ns (93.941%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.271ns = ( 37.729 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.059 21.198 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X136Y146 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[731]_i_3/I3 SLICE_X136Y146 LUT4 (Prop_lut4_I3_O) 0.117 21.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[731]_i_3/O net (fo=1, routed) 1.245 22.560 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[731] SLICE_X138Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[731]_i_2/I0 SLICE_X138Y157 LUT6 (Prop_lut6_I0_O) 0.348 22.908 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[731]_i_2/O net (fo=1, routed) 1.021 23.930 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[470] SLICE_X132Y150 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[731]_i_1/I1 SLICE_X132Y150 LUT3 (Prop_lut3_I1_O) 0.153 24.083 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[731]_i_1/O net (fo=1, routed) 0.000 24.083 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[731] SLICE_X132Y150 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.404 37.729 clock pessimism -0.514 37.216 clock uncertainty -0.077 37.139 SLICE_X132Y150 FDCE (Setup_fdce_C_D) 0.118 37.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731] ------------------------------------------------------------------- required time 37.257 arrival time -24.083 ------------------------------------------------------------------- slack 13.175 Slack (MET) : 13.175ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.605ns (logic 1.612ns (6.059%) route 24.993ns (93.941%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.271ns = ( 37.729 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.059 21.198 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X136Y146 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[731]_i_3/I3 SLICE_X136Y146 LUT4 (Prop_lut4_I3_O) 0.117 21.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[731]_i_3/O net (fo=1, routed) 1.245 22.560 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[731] SLICE_X138Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[731]_i_2/I0 SLICE_X138Y157 LUT6 (Prop_lut6_I0_O) 0.348 22.908 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[731]_i_2/O net (fo=1, routed) 1.021 23.930 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[470] SLICE_X132Y150 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[731]_i_1/I1 SLICE_X132Y150 LUT3 (Prop_lut3_I1_O) 0.153 24.083 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[731]_i_1/O net (fo=1, routed) 0.000 24.083 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[731] SLICE_X132Y150 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.404 37.729 clock pessimism -0.514 37.216 clock uncertainty -0.077 37.139 SLICE_X132Y150 FDCE (Setup_fdce_C_D) 0.118 37.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[731] ------------------------------------------------------------------- required time 37.257 arrival time -24.083 ------------------------------------------------------------------- slack 13.175 Slack (MET) : 13.189ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.205ns (logic 1.392ns (5.312%) route 24.813ns (94.688%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.682 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400] ------------------------------------------------------------------- required time 36.872 arrival time -23.682 ------------------------------------------------------------------- slack 13.189 Slack (MET) : 13.189ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.205ns (logic 1.392ns (5.312%) route 24.813ns (94.688%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.682 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1400] ------------------------------------------------------------------- required time 36.872 arrival time -23.682 ------------------------------------------------------------------- slack 13.189 Slack (MET) : 13.189ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.205ns (logic 1.392ns (5.312%) route 24.813ns (94.688%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.682 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592] ------------------------------------------------------------------- required time 36.872 arrival time -23.682 ------------------------------------------------------------------- slack 13.189 Slack (MET) : 13.189ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.205ns (logic 1.392ns (5.312%) route 24.813ns (94.688%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.364 23.682 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y126 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X153Y126 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1592] ------------------------------------------------------------------- required time 36.872 arrival time -23.682 ------------------------------------------------------------------- slack 13.189 Slack (MET) : 13.193ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.240ns (logic 1.164ns (4.436%) route 25.076ns (95.564%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402] ------------------------------------------------------------------- required time 36.911 arrival time -23.717 ------------------------------------------------------------------- slack 13.193 Slack (MET) : 13.193ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.240ns (logic 1.164ns (4.436%) route 25.076ns (95.564%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402] ------------------------------------------------------------------- required time 36.911 arrival time -23.717 ------------------------------------------------------------------- slack 13.193 Slack (MET) : 13.193ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.240ns (logic 1.164ns (4.436%) route 25.076ns (95.564%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466] ------------------------------------------------------------------- required time 36.911 arrival time -23.717 ------------------------------------------------------------------- slack 13.193 Slack (MET) : 13.193ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.240ns (logic 1.164ns (4.436%) route 25.076ns (95.564%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466] ------------------------------------------------------------------- required time 36.911 arrival time -23.717 ------------------------------------------------------------------- slack 13.193 Slack (MET) : 13.240ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.153ns (logic 1.164ns (4.451%) route 24.989ns (95.549%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.028 23.630 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X151Y124 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X151Y124 FDCE (Setup_fdce_C_CE) -0.413 36.870 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383] ------------------------------------------------------------------- required time 36.870 arrival time -23.630 ------------------------------------------------------------------- slack 13.240 Slack (MET) : 13.240ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.153ns (logic 1.164ns (4.451%) route 24.989ns (95.549%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.028 23.630 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X151Y124 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X151Y124 FDCE (Setup_fdce_C_CE) -0.413 36.870 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383] ------------------------------------------------------------------- required time 36.870 arrival time -23.630 ------------------------------------------------------------------- slack 13.240 Slack (MET) : 13.246ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.531ns (logic 1.366ns (5.149%) route 25.165ns (94.851%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.264ns = ( 37.736 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.901 21.041 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X130Y146 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[296]_i_3/I3 SLICE_X130Y146 LUT4 (Prop_lut4_I3_O) 0.124 21.165 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[296]_i_3/O net (fo=1, routed) 1.879 23.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[296] SLICE_X123Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[296]_i_2/I0 SLICE_X123Y131 LUT6 (Prop_lut6_I0_O) 0.124 23.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[296]_i_2/O net (fo=1, routed) 0.717 23.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[35] SLICE_X123Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[296]_i_1/I1 SLICE_X123Y133 LUT3 (Prop_lut3_I1_O) 0.124 24.008 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[296]_i_1/O net (fo=1, routed) 0.000 24.008 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[296] SLICE_X123Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.411 37.736 clock pessimism -0.435 37.301 clock uncertainty -0.077 37.225 SLICE_X123Y133 FDCE (Setup_fdce_C_D) 0.029 37.254 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296] ------------------------------------------------------------------- required time 37.254 arrival time -24.008 ------------------------------------------------------------------- slack 13.246 Slack (MET) : 13.246ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.531ns (logic 1.366ns (5.149%) route 25.165ns (94.851%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.264ns = ( 37.736 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.901 21.041 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X130Y146 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[296]_i_3/I3 SLICE_X130Y146 LUT4 (Prop_lut4_I3_O) 0.124 21.165 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[296]_i_3/O net (fo=1, routed) 1.879 23.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[296] SLICE_X123Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[296]_i_2/I0 SLICE_X123Y131 LUT6 (Prop_lut6_I0_O) 0.124 23.167 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[296]_i_2/O net (fo=1, routed) 0.717 23.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[35] SLICE_X123Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[296]_i_1/I1 SLICE_X123Y133 LUT3 (Prop_lut3_I1_O) 0.124 24.008 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[296]_i_1/O net (fo=1, routed) 0.000 24.008 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[296] SLICE_X123Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.411 37.736 clock pessimism -0.435 37.301 clock uncertainty -0.077 37.225 SLICE_X123Y133 FDCE (Setup_fdce_C_D) 0.029 37.254 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[296] ------------------------------------------------------------------- required time 37.254 arrival time -24.008 ------------------------------------------------------------------- slack 13.246 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.480 37.805 clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.480 37.805 clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[142] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.480 37.805 clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.480 37.805 clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[144] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.480 37.805 clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.267ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.136ns (logic 0.761ns (2.912%) route 25.375ns (97.088%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.336 23.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X141Y111 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.480 37.805 clock pessimism -0.435 37.370 clock uncertainty -0.077 37.294 SLICE_X141Y111 FDCE (Setup_fdce_C_CE) -0.413 36.881 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[173] ------------------------------------------------------------------- required time 36.881 arrival time -23.614 ------------------------------------------------------------------- slack 13.267 Slack (MET) : 13.277ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.120ns (logic 1.392ns (5.329%) route 24.728ns (94.671%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.279 23.598 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X153Y128 FDCE (Setup_fdce_C_CE) -0.413 36.875 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527] ------------------------------------------------------------------- required time 36.875 arrival time -23.598 ------------------------------------------------------------------- slack 13.277 Slack (MET) : 13.277ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.120ns (logic 1.392ns (5.329%) route 24.728ns (94.671%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.279 23.598 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X153Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X153Y128 FDCE (Setup_fdce_C_CE) -0.413 36.875 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1527] ------------------------------------------------------------------- required time 36.875 arrival time -23.598 ------------------------------------------------------------------- slack 13.277 Slack (MET) : 13.292ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.141ns (logic 1.164ns (4.453%) route 24.977ns (95.547%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.016 23.618 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X146Y128 FDCE (Setup_fdce_C_CE) -0.377 36.910 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472] ------------------------------------------------------------------- required time 36.910 arrival time -23.618 ------------------------------------------------------------------- slack 13.292 Slack (MET) : 13.292ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.141ns (logic 1.164ns (4.453%) route 24.977ns (95.547%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.016 23.618 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X146Y128 FDCE (Setup_fdce_C_CE) -0.377 36.910 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1472] ------------------------------------------------------------------- required time 36.910 arrival time -23.618 ------------------------------------------------------------------- slack 13.292 Slack (MET) : 13.292ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.141ns (logic 1.164ns (4.453%) route 24.977ns (95.547%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.016 23.618 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X146Y128 FDCE (Setup_fdce_C_CE) -0.377 36.910 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478] ------------------------------------------------------------------- required time 36.910 arrival time -23.618 ------------------------------------------------------------------- slack 13.292 Slack (MET) : 13.292ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.141ns (logic 1.164ns (4.453%) route 24.977ns (95.547%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.016 23.618 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X146Y128 FDCE (Setup_fdce_C_CE) -0.377 36.910 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1478] ------------------------------------------------------------------- required time 36.910 arrival time -23.618 ------------------------------------------------------------------- slack 13.292 Slack (MET) : 13.301ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.131ns (logic 1.164ns (4.455%) route 24.967ns (95.545%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.203ns = ( 37.797 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.006 23.608 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X152Y127 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.472 37.797 clock pessimism -0.435 37.362 clock uncertainty -0.077 37.286 SLICE_X152Y127 FDCE (Setup_fdce_C_CE) -0.377 36.909 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384] ------------------------------------------------------------------- required time 36.909 arrival time -23.608 ------------------------------------------------------------------- slack 13.301 Slack (MET) : 13.301ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.131ns (logic 1.164ns (4.455%) route 24.967ns (95.545%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.203ns = ( 37.797 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.006 23.608 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X152Y127 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.472 37.797 clock pessimism -0.435 37.362 clock uncertainty -0.077 37.286 SLICE_X152Y127 FDCE (Setup_fdce_C_CE) -0.377 36.909 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1384] ------------------------------------------------------------------- required time 36.909 arrival time -23.608 ------------------------------------------------------------------- slack 13.301 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[628] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[631] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[725] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.310ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.146ns (logic 0.766ns (2.930%) route 25.380ns (97.070%)) Logic Levels: 2 (LUT3=1 LUT4=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.272ns = ( 37.728 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/I2 SLICE_X53Y138 LUT4 (Prop_lut4_I2_O) 0.124 11.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1/O net (fo=1600, routed) 12.340 23.623 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 SLICE_X138Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.403 37.728 clock pessimism -0.514 37.215 clock uncertainty -0.077 37.138 SLICE_X138Y158 FDCE (Setup_fdce_C_CE) -0.205 36.933 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[728] ------------------------------------------------------------------- required time 36.933 arrival time -23.623 ------------------------------------------------------------------- slack 13.310 Slack (MET) : 13.317ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.018ns (logic 1.164ns (4.474%) route 24.854ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.263ns = ( 37.737 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.894 23.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X133Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.412 37.737 clock pessimism -0.435 37.302 clock uncertainty -0.077 37.226 SLICE_X133Y117 FDCE (Setup_fdce_C_CE) -0.413 36.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568] ------------------------------------------------------------------- required time 36.813 arrival time -23.495 ------------------------------------------------------------------- slack 13.317 Slack (MET) : 13.317ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.018ns (logic 1.164ns (4.474%) route 24.854ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.263ns = ( 37.737 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.894 23.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X133Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.412 37.737 clock pessimism -0.435 37.302 clock uncertainty -0.077 37.226 SLICE_X133Y117 FDCE (Setup_fdce_C_CE) -0.413 36.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1568] ------------------------------------------------------------------- required time 36.813 arrival time -23.495 ------------------------------------------------------------------- slack 13.317 Slack (MET) : 13.317ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.018ns (logic 1.164ns (4.474%) route 24.854ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.263ns = ( 37.737 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.894 23.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X133Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.412 37.737 clock pessimism -0.435 37.302 clock uncertainty -0.077 37.226 SLICE_X133Y117 FDCE (Setup_fdce_C_CE) -0.413 36.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574] ------------------------------------------------------------------- required time 36.813 arrival time -23.495 ------------------------------------------------------------------- slack 13.317 Slack (MET) : 13.317ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.018ns (logic 1.164ns (4.474%) route 24.854ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.263ns = ( 37.737 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.894 23.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X133Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.412 37.737 clock pessimism -0.435 37.302 clock uncertainty -0.077 37.226 SLICE_X133Y117 FDCE (Setup_fdce_C_CE) -0.413 36.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1574] ------------------------------------------------------------------- required time 36.813 arrival time -23.495 ------------------------------------------------------------------- slack 13.317 Slack (MET) : 13.319ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.482ns (logic 1.594ns (6.019%) route 24.888ns (93.981%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.209ns = ( 37.791 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.909 21.049 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X125Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[675]_i_3/I3 SLICE_X125Y147 LUT4 (Prop_lut4_I3_O) 0.150 21.199 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[675]_i_3/O net (fo=1, routed) 1.702 22.901 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[675] SLICE_X141Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[675]_i_2/I0 SLICE_X141Y156 LUT6 (Prop_lut6_I0_O) 0.326 23.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[675]_i_2/O net (fo=1, routed) 0.609 23.835 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[414] SLICE_X142Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[675]_i_1/I1 SLICE_X142Y156 LUT3 (Prop_lut3_I1_O) 0.124 23.959 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[675]_i_1/O net (fo=1, routed) 0.000 23.959 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[675] SLICE_X142Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.466 37.791 clock pessimism -0.514 37.278 clock uncertainty -0.077 37.201 SLICE_X142Y156 FDCE (Setup_fdce_C_D) 0.077 37.278 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675] ------------------------------------------------------------------- required time 37.278 arrival time -23.959 ------------------------------------------------------------------- slack 13.319 Slack (MET) : 13.319ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.482ns (logic 1.594ns (6.019%) route 24.888ns (93.981%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.209ns = ( 37.791 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 9.909 21.049 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X125Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[675]_i_3/I3 SLICE_X125Y147 LUT4 (Prop_lut4_I3_O) 0.150 21.199 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[675]_i_3/O net (fo=1, routed) 1.702 22.901 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[675] SLICE_X141Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[675]_i_2/I0 SLICE_X141Y156 LUT6 (Prop_lut6_I0_O) 0.326 23.227 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[675]_i_2/O net (fo=1, routed) 0.609 23.835 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[414] SLICE_X142Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[675]_i_1/I1 SLICE_X142Y156 LUT3 (Prop_lut3_I1_O) 0.124 23.959 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[675]_i_1/O net (fo=1, routed) 0.000 23.959 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[675] SLICE_X142Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.466 37.791 clock pessimism -0.514 37.278 clock uncertainty -0.077 37.201 SLICE_X142Y156 FDCE (Setup_fdce_C_D) 0.077 37.278 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[675] ------------------------------------------------------------------- required time 37.278 arrival time -23.959 ------------------------------------------------------------------- slack 13.319 Slack (MET) : 13.335ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.094ns (logic 1.164ns (4.461%) route 24.930ns (95.539%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.970 23.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y126 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347] ------------------------------------------------------------------- required time 36.907 arrival time -23.572 ------------------------------------------------------------------- slack 13.335 Slack (MET) : 13.335ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.094ns (logic 1.164ns (4.461%) route 24.930ns (95.539%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.970 23.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y126 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y126 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1347] ------------------------------------------------------------------- required time 36.907 arrival time -23.572 ------------------------------------------------------------------- slack 13.335 Slack (MET) : 13.375ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.019ns (logic 1.164ns (4.474%) route 24.855ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.895 23.497 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X143Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X143Y128 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336] ------------------------------------------------------------------- required time 36.872 arrival time -23.497 ------------------------------------------------------------------- slack 13.375 Slack (MET) : 13.375ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.019ns (logic 1.164ns (4.474%) route 24.855ns (95.526%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.204ns = ( 37.796 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.895 23.497 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X143Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.796 clock pessimism -0.435 37.361 clock uncertainty -0.077 37.285 SLICE_X143Y128 FDCE (Setup_fdce_C_CE) -0.413 36.872 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1336] ------------------------------------------------------------------- required time 36.872 arrival time -23.497 ------------------------------------------------------------------- slack 13.375 Slack (MET) : 13.383ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.512ns (logic 1.562ns (5.892%) route 24.950ns (94.108%)) Logic Levels: 5 (LUT3=1 LUT4=1 LUT5=1 LUT6=2) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.193ns = ( 37.807 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.287 21.427 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X132Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1112]_i_4/I3 SLICE_X132Y142 LUT4 (Prop_lut4_I3_O) 0.116 21.543 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1112]_i_4/O net (fo=1, routed) 0.954 22.497 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[1112] SLICE_X138Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[1112]_i_3/I0 SLICE_X138Y142 LUT6 (Prop_lut6_I0_O) 0.328 22.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[1112]_i_3/O net (fo=1, routed) 1.041 23.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[851] SLICE_X142Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1112]_i_1/I3 SLICE_X142Y142 LUT5 (Prop_lut5_I3_O) 0.124 23.990 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1112]_i_1/O net (fo=1, routed) 0.000 23.990 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[1112] SLICE_X142Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.482 37.807 clock pessimism -0.435 37.372 clock uncertainty -0.077 37.296 SLICE_X142Y142 FDCE (Setup_fdce_C_D) 0.077 37.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112] ------------------------------------------------------------------- required time 37.373 arrival time -23.990 ------------------------------------------------------------------- slack 13.383 Slack (MET) : 13.383ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.512ns (logic 1.562ns (5.892%) route 24.950ns (94.108%)) Logic Levels: 5 (LUT3=1 LUT4=1 LUT5=1 LUT6=2) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.193ns = ( 37.807 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 10.287 21.427 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X132Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1112]_i_4/I3 SLICE_X132Y142 LUT4 (Prop_lut4_I3_O) 0.116 21.543 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1112]_i_4/O net (fo=1, routed) 0.954 22.497 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[1112] SLICE_X138Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[1112]_i_3/I0 SLICE_X138Y142 LUT6 (Prop_lut6_I0_O) 0.328 22.825 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[1112]_i_3/O net (fo=1, routed) 1.041 23.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[851] SLICE_X142Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1112]_i_1/I3 SLICE_X142Y142 LUT5 (Prop_lut5_I3_O) 0.124 23.990 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1112]_i_1/O net (fo=1, routed) 0.000 23.990 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[1112] SLICE_X142Y142 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.482 37.807 clock pessimism -0.435 37.372 clock uncertainty -0.077 37.296 SLICE_X142Y142 FDCE (Setup_fdce_C_D) 0.077 37.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1112] ------------------------------------------------------------------- required time 37.373 arrival time -23.990 ------------------------------------------------------------------- slack 13.383 Slack (MET) : 13.417ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.979ns (logic 1.164ns (4.481%) route 24.815ns (95.519%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.855 23.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X145Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X145Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414] ------------------------------------------------------------------- required time 36.874 arrival time -23.456 ------------------------------------------------------------------- slack 13.417 Slack (MET) : 13.417ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.979ns (logic 1.164ns (4.481%) route 24.815ns (95.519%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.855 23.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X145Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X145Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1414] ------------------------------------------------------------------- required time 36.874 arrival time -23.456 ------------------------------------------------------------------- slack 13.417 Slack (MET) : 13.417ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.979ns (logic 1.164ns (4.481%) route 24.815ns (95.519%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.855 23.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X145Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X145Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576] ------------------------------------------------------------------- required time 36.874 arrival time -23.456 ------------------------------------------------------------------- slack 13.417 Slack (MET) : 13.417ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.979ns (logic 1.164ns (4.481%) route 24.815ns (95.519%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.855 23.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X145Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X145Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1576] ------------------------------------------------------------------- required time 36.874 arrival time -23.456 ------------------------------------------------------------------- slack 13.417 Slack (MET) : 13.419ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.010ns (logic 1.164ns (4.475%) route 24.846ns (95.525%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.885 23.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X148Y124 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X148Y124 FDCE (Setup_fdce_C_CE) -0.377 36.906 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513] ------------------------------------------------------------------- required time 36.906 arrival time -23.487 ------------------------------------------------------------------- slack 13.419 Slack (MET) : 13.419ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.010ns (logic 1.164ns (4.475%) route 24.846ns (95.525%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.885 23.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X148Y124 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X148Y124 FDCE (Setup_fdce_C_CE) -0.377 36.906 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1513] ------------------------------------------------------------------- required time 36.906 arrival time -23.487 ------------------------------------------------------------------- slack 13.419 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1287] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1415] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1543] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.426ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.004ns (logic 1.164ns (4.476%) route 24.840ns (95.524%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 37.795 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.879 23.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X146Y123 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.470 37.795 clock pessimism -0.435 37.360 clock uncertainty -0.077 37.284 SLICE_X146Y123 FDCE (Setup_fdce_C_CE) -0.377 36.907 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1572] ------------------------------------------------------------------- required time 36.907 arrival time -23.481 ------------------------------------------------------------------- slack 13.426 Slack (MET) : 13.444ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.985ns (logic 1.164ns (4.480%) route 24.821ns (95.520%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.860 23.462 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X140Y127 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X140Y127 FDCE (Setup_fdce_C_CE) -0.377 36.906 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439] ------------------------------------------------------------------- required time 36.906 arrival time -23.462 ------------------------------------------------------------------- slack 13.444 Slack (MET) : 13.444ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.985ns (logic 1.164ns (4.480%) route 24.821ns (95.520%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.860 23.462 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X140Y127 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X140Y127 FDCE (Setup_fdce_C_CE) -0.377 36.906 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1439] ------------------------------------------------------------------- required time 36.906 arrival time -23.462 ------------------------------------------------------------------- slack 13.444 Slack (MET) : 13.445ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.951ns (logic 1.164ns (4.485%) route 24.787ns (95.515%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.827 23.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X147Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X147Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416] ------------------------------------------------------------------- required time 36.874 arrival time -23.429 ------------------------------------------------------------------- slack 13.445 Slack (MET) : 13.445ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.951ns (logic 1.164ns (4.485%) route 24.787ns (95.515%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.827 23.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X147Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X147Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1416] ------------------------------------------------------------------- required time 36.874 arrival time -23.429 ------------------------------------------------------------------- slack 13.445 Slack (MET) : 13.445ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.951ns (logic 1.164ns (4.485%) route 24.787ns (95.515%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.827 23.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X147Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X147Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480] ------------------------------------------------------------------- required time 36.874 arrival time -23.429 ------------------------------------------------------------------- slack 13.445 Slack (MET) : 13.445ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.951ns (logic 1.164ns (4.485%) route 24.787ns (95.515%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.202ns = ( 37.798 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.827 23.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X147Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.473 37.798 clock pessimism -0.435 37.363 clock uncertainty -0.077 37.287 SLICE_X147Y128 FDCE (Setup_fdce_C_CE) -0.413 36.874 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1480] ------------------------------------------------------------------- required time 36.874 arrival time -23.429 ------------------------------------------------------------------- slack 13.445 Slack (MET) : 13.477ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.957ns (logic 1.392ns (5.363%) route 24.565ns (94.637%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.434 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402] ------------------------------------------------------------------- required time 36.911 arrival time -23.434 ------------------------------------------------------------------- slack 13.477 Slack (MET) : 13.477ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.957ns (logic 1.392ns (5.363%) route 24.565ns (94.637%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.434 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1402] ------------------------------------------------------------------- required time 36.911 arrival time -23.434 ------------------------------------------------------------------- slack 13.477 Slack (MET) : 13.477ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.957ns (logic 1.392ns (5.363%) route 24.565ns (94.637%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.434 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466] ------------------------------------------------------------------- required time 36.911 arrival time -23.434 ------------------------------------------------------------------- slack 13.477 Slack (MET) : 13.477ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.957ns (logic 1.392ns (5.363%) route 24.565ns (94.637%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.115 23.434 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X150Y128 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X150Y128 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1466] ------------------------------------------------------------------- required time 36.911 arrival time -23.434 ------------------------------------------------------------------- slack 13.477 Slack (MET) : 13.504ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.930ns (logic 1.164ns (4.489%) route 24.766ns (95.511%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.805 23.407 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X144Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X144Y129 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418] ------------------------------------------------------------------- required time 36.911 arrival time -23.407 ------------------------------------------------------------------- slack 13.504 Slack (MET) : 13.504ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.930ns (logic 1.164ns (4.489%) route 24.766ns (95.511%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.201ns = ( 37.799 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.805 23.407 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X144Y129 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.474 37.799 clock pessimism -0.435 37.364 clock uncertainty -0.077 37.288 SLICE_X144Y129 FDCE (Setup_fdce_C_CE) -0.377 36.911 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1418] ------------------------------------------------------------------- required time 36.911 arrival time -23.407 ------------------------------------------------------------------- slack 13.504 Slack (MET) : 13.523ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.869ns (logic 1.392ns (5.381%) route 24.477ns (94.619%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.028 23.347 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X151Y124 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X151Y124 FDCE (Setup_fdce_C_CE) -0.413 36.870 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383] ------------------------------------------------------------------- required time 36.870 arrival time -23.347 ------------------------------------------------------------------- slack 13.523 Slack (MET) : 13.523ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.869ns (logic 1.392ns (5.381%) route 24.477ns (94.619%)) Logic Levels: 5 (LUT3=2 LUT6=3) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.206ns = ( 37.794 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 0.830 11.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X60Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/I1 SLICE_X60Y151 LUT6 (Prop_lut6_I1_O) 0.124 12.094 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O net (fo=1, routed) 1.395 13.489 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I0 SLICE_X60Y139 LUT6 (Prop_lut6_I0_O) 0.124 13.613 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.319 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 8.028 23.347 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X151Y124 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.469 37.794 clock pessimism -0.435 37.359 clock uncertainty -0.077 37.283 SLICE_X151Y124 FDCE (Setup_fdce_C_CE) -0.413 36.870 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1383] ------------------------------------------------------------------- required time 36.870 arrival time -23.347 ------------------------------------------------------------------- slack 13.523 Slack (MET) : 13.528ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.208ns (logic 1.620ns (6.181%) route 24.588ns (93.819%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.271ns = ( 37.729 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 8.784 19.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X105Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[598]_i_3/I3 SLICE_X105Y139 LUT4 (Prop_lut4_I3_O) 0.150 20.074 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[598]_i_3/O net (fo=1, routed) 1.791 21.864 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[598] SLICE_X115Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[598]_i_2/I0 SLICE_X115Y158 LUT6 (Prop_lut6_I0_O) 0.326 22.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[598]_i_2/O net (fo=1, routed) 1.346 23.536 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[337] SLICE_X133Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[598]_i_1/I1 SLICE_X133Y151 LUT3 (Prop_lut3_I1_O) 0.150 23.686 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[598]_i_1/O net (fo=1, routed) 0.000 23.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[598] SLICE_X133Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.404 37.729 clock pessimism -0.514 37.216 clock uncertainty -0.077 37.139 SLICE_X133Y151 FDCE (Setup_fdce_C_D) 0.075 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598] ------------------------------------------------------------------- required time 37.214 arrival time -23.686 ------------------------------------------------------------------- slack 13.528 Slack (MET) : 13.528ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 26.208ns (logic 1.620ns (6.181%) route 24.588ns (93.819%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.271ns = ( 37.729 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 10.212 8.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/I1 SLICE_X78Y138 LUT3 (Prop_lut3_I1_O) 0.150 8.358 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O net (fo=1608, routed) 2.456 10.813 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] SLICE_X60Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/I2 SLICE_X60Y152 LUT6 (Prop_lut6_I2_O) 0.326 11.139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[260]_i_7/O net (fo=1601, routed) 8.784 19.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_next[0] SLICE_X105Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[598]_i_3/I3 SLICE_X105Y139 LUT4 (Prop_lut4_I3_O) 0.150 20.074 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[598]_i_3/O net (fo=1, routed) 1.791 21.864 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r_reg[598] SLICE_X115Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[598]_i_2/I0 SLICE_X115Y158 LUT6 (Prop_lut6_I0_O) 0.326 22.190 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/state_r[598]_i_2/O net (fo=1, routed) 1.346 23.536 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[337] SLICE_X133Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[598]_i_1/I1 SLICE_X133Y151 LUT3 (Prop_lut3_I1_O) 0.150 23.686 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[598]_i_1/O net (fo=1, routed) 0.000 23.686 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[598] SLICE_X133Y151 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.404 37.729 clock pessimism -0.514 37.216 clock uncertainty -0.077 37.139 SLICE_X133Y151 FDCE (Setup_fdce_C_D) 0.075 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[598] ------------------------------------------------------------------- required time 37.214 arrival time -23.686 ------------------------------------------------------------------- slack 13.528 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[206] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[246] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[53] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.893ns (logic 0.761ns (2.939%) route 25.132ns (97.061%)) Logic Levels: 2 (LUT2=1 LUT3=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.197ns = ( 37.803 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 1.943 11.159 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X53Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/I1 SLICE_X53Y138 LUT2 (Prop_lut2_I1_O) 0.119 11.278 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[511]_i_1/O net (fo=512, routed) 12.092 23.370 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 SLICE_X140Y113 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.477 37.803 clock pessimism -0.435 37.368 clock uncertainty -0.077 37.292 SLICE_X140Y113 FDCE (Setup_fdce_C_CE) -0.377 36.915 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[57] ------------------------------------------------------------------- required time 36.915 arrival time -23.370 ------------------------------------------------------------------- slack 13.544 Slack (MET) : 13.566ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.763ns (logic 1.164ns (4.518%) route 24.599ns (95.482%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.181ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.269ns = ( 37.731 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.639 23.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X138Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.406 37.731 clock pessimism -0.435 37.296 clock uncertainty -0.077 37.220 SLICE_X138Y126 FDCE (Setup_fdce_C_CE) -0.413 36.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413] ------------------------------------------------------------------- required time 36.807 arrival time -23.240 ------------------------------------------------------------------- slack 13.566 Slack (MET) : 13.566ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413]/CE (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 25.763ns (logic 1.164ns (4.518%) route 24.599ns (95.482%)) Logic Levels: 5 (LUT3=2 LUT4=1 LUT6=2) Clock Path Skew: -0.181ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.269ns = ( 37.731 - 40.000 ) Source Clock Delay (SCD): -2.523ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.753 -2.523 SLICE_X158Y129 FDCE 0.000 -2.523 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/C SLICE_X158Y129 FDCE (Prop_fdce_C_Q) 0.518 -2.005 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg/Q net (fo=1611, routed) 11.097 9.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 SLICE_X78Y139 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/I1 SLICE_X78Y139 LUT3 (Prop_lut3_I1_O) 0.124 9.216 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/FSM_onehot_mb_state[2]_i_4/O net (fo=9, routed) 2.458 11.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/kc_valid_o_sha3 SLICE_X47Y138 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/I1 SLICE_X47Y138 LUT6 (Prop_lut6_I1_O) 0.124 11.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9/O net (fo=1, routed) 0.946 12.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_9_n_0 SLICE_X51Y138 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/I3 SLICE_X51Y138 LUT4 (Prop_lut4_I3_O) 0.124 12.868 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/cnt_r[4]_i_7/O net (fo=1, routed) 0.904 13.772 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r_reg[1599]_2 SLICE_X60Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/I5 SLICE_X60Y139 LUT6 (Prop_lut6_I5_O) 0.124 13.896 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O net (fo=2, routed) 1.556 15.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux SLICE_X78Y139 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/I2 SLICE_X78Y139 LUT3 (Prop_lut3_I2_O) 0.150 15.602 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O net (fo=1601, routed) 7.639 23.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 SLICE_X138Y126 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413]/CE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 40.000 40.000 r clock source latency -5.674 34.326 propagated clock network latency 3.406 37.731 clock pessimism -0.435 37.296 clock uncertainty -0.077 37.220 SLICE_X138Y126 FDCE (Setup_fdce_C_CE) -0.413 36.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1413] ------------------------------------------------------------------- required time 36.807 arrival time -23.240 ------------------------------------------------------------------- slack 13.566