Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 | Date : Wed Jul 15 05:09:25 2026 | Host : Roc_Wang running 64-bit major release (build 9200) | Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 20 -input_pins -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/timing_summary_full.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 38 input ports with no input delay specified. (HIGH) UART_RX UART_TX dip_sw[0] dip_sw[10] dip_sw[11] dip_sw[12] dip_sw[13] dip_sw[14] dip_sw[15] dip_sw[16] dip_sw[17] dip_sw[18] dip_sw[19] dip_sw[1] dip_sw[20] dip_sw[21] dip_sw[22] dip_sw[23] dip_sw[24] dip_sw[25] dip_sw[26] dip_sw[27] dip_sw[28] dip_sw[29] dip_sw[2] dip_sw[30] dip_sw[31] dip_sw[3] dip_sw[4] dip_sw[5] dip_sw[6] dip_sw[7] dip_sw[8] dip_sw[9] touch_btn[0] touch_btn[1] touch_btn[2] touch_btn[3] There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 40 ports with no output delay specified. (HIGH) UART_RX UART_TX dpy0[0] dpy0[1] dpy0[2] dpy0[3] dpy0[4] dpy0[5] dpy0[6] dpy0[7] dpy1[0] dpy1[1] dpy1[2] dpy1[3] dpy1[4] dpy1[5] dpy1[6] dpy1[7] leds[0] leds[10] leds[11] leds[12] leds[13] leds[14] leds[15] leds[1] leds[2] leds[3] leds[4] leds[5] leds[6] leds[7] leds[8] leds[9] video_de video_hsync video_red[0] video_red[1] video_red[2] video_vsync There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.070 0.000 0 88843 0.024 0.000 0 88843 5.250 0.000 0 33736 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk {0.000 10.000} 20.000 50.000 clkfbout_clk_pll {0.000 10.000} 20.000 50.000 cpu_clk {0.000 15.000} 30.000 33.333 mlkem_clk {0.000 6.500} 13.000 76.923 sys_clk {0.000 10.000} 20.000 50.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk 7.000 0.000 0 1 clkfbout_clk_pll 17.845 0.000 0 3 cpu_clk 0.737 0.000 0 17197 0.040 0.000 0 17197 13.750 0.000 0 6486 mlkem_clk 0.070 0.000 0 31646 0.057 0.000 0 31646 5.250 0.000 0 17274 sys_clk 0.125 0.000 0 22307 0.024 0.000 0 22307 8.750 0.000 0 9972 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** cpu_clk cpu_clk 26.018 0.000 0 67 0.681 0.000 0 67 **async_default** mlkem_clk mlkem_clk 3.826 0.000 0 16740 0.658 0.000 0 16740 **async_default** sys_clk sys_clk 6.335 0.000 0 886 0.573 0.000 0 886 ------------------------------------------------------------------------------------------------ | User Ignored Path Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) sys_clk cpu_clk (none) sys_clk mlkem_clk (none) cpu_clk sys_clk (none) mlkem_clk sys_clk ------------------------------------------------------------------------------------------------ | Unconstrained Path Table | ------------------------ ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) clkfbout_clk_pll (none) sys_clk (none) sys_clk ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk To Clock: clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { clk } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_pll To Clock: clkfbout_clk_pll Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_pll Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y19 pll_clk.u_clk_pll/inst/clkf_buf/I Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: cpu_clk To Clock: cpu_clk Setup : 0 Failing Endpoints, Worst Slack 0.737ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.040ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 13.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.737ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 29.089ns (logic 8.012ns (27.543%) route 21.077ns (72.457%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.677 24.234 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X117Y153 f u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/I2 SLICE_X117Y153 LUT6 (Prop_lut6_I2_O) 0.332 24.566 r u_cpu/u_csr/ds_to_es_bus_r[189]_i_15/O net (fo=1, routed) 0.909 25.475 u_cpu/id_stage/ds_to_es_bus_r_reg[189]_2 SLICE_X113Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/I3 SLICE_X113Y158 LUT4 (Prop_lut4_I3_O) 0.124 25.599 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_5/O net (fo=1, routed) 0.715 26.314 u_cpu/id_stage/ds_to_es_bus_r[189]_i_5_n_0 SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/I4 SLICE_X112Y158 LUT6 (Prop_lut6_I4_O) 0.124 26.438 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O net (fo=1, routed) 0.000 26.438 u_cpu/exe_stage/ds_to_es_bus[139] SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.079 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] ------------------------------------------------------------------- required time 27.175 arrival time -26.438 ------------------------------------------------------------------- slack 0.737 Slack (MET) : 0.754ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 29.021ns (logic 8.005ns (27.583%) route 21.016ns (72.417%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.702 24.253 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 SLICE_X115Y154 f u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/I0 SLICE_X115Y154 LUT5 (Prop_lut5_I0_O) 0.326 24.579 r u_cpu/u_csr/ds_to_es_bus_r[193]_i_9/O net (fo=1, routed) 0.421 25.000 u_cpu/id_stage/ds_to_es_bus_r_reg[193]_6 SLICE_X114Y152 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/I3 SLICE_X114Y152 LUT6 (Prop_lut6_I3_O) 0.124 25.124 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_2/O net (fo=1, routed) 1.122 26.246 u_cpu/id_stage/ds_to_es_bus_r[193]_i_2_n_0 SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/I1 SLICE_X110Y160 LUT6 (Prop_lut6_I1_O) 0.124 26.370 r u_cpu/id_stage/ds_to_es_bus_r[193]_i_1/O net (fo=1, routed) 0.000 26.370 u_cpu/exe_stage/ds_to_es_bus[143] SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[193]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[193] ------------------------------------------------------------------- required time 27.124 arrival time -26.370 ------------------------------------------------------------------- slack 0.754 Slack (MET) : 0.793ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 29.035ns (logic 7.809ns (26.895%) route 21.226ns (73.105%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O net (fo=32, routed) 0.967 24.378 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 SLICE_X111Y155 f u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/I2 SLICE_X111Y155 LUT4 (Prop_lut4_I2_O) 0.124 24.502 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_11/O net (fo=1, routed) 0.819 25.321 u_cpu/id_stage/ds_to_es_bus_r[186]_i_11_n_0 SLICE_X116Y155 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/I3 SLICE_X116Y155 LUT4 (Prop_lut4_I3_O) 0.124 25.445 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_4/O net (fo=1, routed) 0.815 26.260 u_cpu/id_stage/ds_to_es_bus_r[186]_i_4_n_0 SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/I3 SLICE_X112Y158 LUT6 (Prop_lut6_I3_O) 0.124 26.384 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O net (fo=1, routed) 0.000 26.384 u_cpu/exe_stage/ds_to_es_bus[136] SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.081 27.177 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] ------------------------------------------------------------------- required time 27.177 arrival time -26.384 ------------------------------------------------------------------- slack 0.793 Slack (MET) : 0.803ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.973ns (logic 8.037ns (27.740%) route 20.936ns (72.260%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 SLICE_X114Y152 f u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/I2 SLICE_X114Y152 LUT4 (Prop_lut4_I2_O) 0.150 25.267 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O net (fo=1, routed) 0.729 25.996 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 SLICE_X110Y152 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/I1 SLICE_X110Y152 LUT6 (Prop_lut6_I1_O) 0.326 26.322 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O net (fo=1, routed) 0.000 26.322 u_cpu/exe_stage/ds_to_es_bus[118] SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X110Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X110Y152 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] ------------------------------------------------------------------- required time 27.125 arrival time -26.322 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.804ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 29.019ns (logic 8.012ns (27.609%) route 21.007ns (72.391%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.713 24.270 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_2 SLICE_X115Y155 f u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/I0 SLICE_X115Y155 LUT6 (Prop_lut6_I0_O) 0.332 24.602 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O net (fo=1, routed) 0.848 25.450 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 SLICE_X104Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/I0 SLICE_X104Y156 LUT6 (Prop_lut6_I0_O) 0.124 25.574 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.671 26.245 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X108Y156 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/I3 SLICE_X108Y156 LUT6 (Prop_lut6_I3_O) 0.124 26.369 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 26.369 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X108Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X108Y156 FDRE (Setup_fdre_C_D) 0.077 27.172 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 27.172 arrival time -26.369 ------------------------------------------------------------------- slack 0.804 Slack (MET) : 0.863ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.961ns (logic 7.809ns (26.964%) route 21.152ns (73.036%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O net (fo=32, routed) 0.987 24.398 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_0 SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/I2 SLICE_X117Y153 LUT4 (Prop_lut4_I2_O) 0.124 24.522 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_7/O net (fo=1, routed) 0.718 25.239 u_cpu/id_stage/ds_to_es_bus_r[185]_i_7_n_0 SLICE_X117Y156 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/I2 SLICE_X117Y156 LUT4 (Prop_lut4_I2_O) 0.124 25.363 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_3/O net (fo=1, routed) 0.823 26.187 u_cpu/id_stage/ds_to_es_bus_r[185]_i_3_n_0 SLICE_X112Y158 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/I2 SLICE_X112Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.311 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O net (fo=1, routed) 0.000 26.311 u_cpu/exe_stage/ds_to_es_bus[135] SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X112Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X112Y158 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] ------------------------------------------------------------------- required time 27.173 arrival time -26.311 ------------------------------------------------------------------- slack 0.863 Slack (MET) : 0.865ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.912ns (logic 8.037ns (27.799%) route 20.875ns (72.201%)) Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O net (fo=32, routed) 1.058 24.188 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 SLICE_X103Y151 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 SLICE_X103Y151 LUT2 (Prop_lut2_I1_O) 0.150 24.338 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O net (fo=1, routed) 1.172 25.510 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 SLICE_X105Y151 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 SLICE_X105Y151 LUT6 (Prop_lut6_I4_O) 0.326 25.836 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O net (fo=1, routed) 0.301 26.137 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 SLICE_X105Y150 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 SLICE_X105Y150 LUT6 (Prop_lut6_I3_O) 0.124 26.261 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O net (fo=1, routed) 0.000 26.261 u_cpu/exe_stage/ds_to_es_bus[114] SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X105Y150 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] ------------------------------------------------------------------- required time 27.126 arrival time -26.261 ------------------------------------------------------------------- slack 0.865 Slack (MET) : 0.867ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.906ns (logic 7.809ns (27.015%) route 21.097ns (72.985%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O net (fo=15, routed) 0.796 25.105 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 SLICE_X116Y153 f u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/I5 SLICE_X116Y153 LUT6 (Prop_lut6_I5_O) 0.124 25.229 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.902 26.131 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X110Y160 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/I1 SLICE_X110Y160 LUT5 (Prop_lut5_I1_O) 0.124 26.255 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 26.255 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk SLICE_X110Y160 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X110Y160 FDRE (Setup_fdre_C_D) 0.029 27.122 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 27.122 arrival time -26.255 ------------------------------------------------------------------- slack 0.867 Slack (MET) : 0.894ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.883ns (logic 8.039ns (27.833%) route 20.844ns (72.167%)) Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 0.878 25.101 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 SLICE_X109Y152 f u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/I1 SLICE_X109Y152 LUT2 (Prop_lut2_I1_O) 0.152 25.253 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O net (fo=1, routed) 0.654 25.907 u_cpu/id_stage/ds_to_es_bus_r_reg[171] SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/I2 SLICE_X109Y151 LUT6 (Prop_lut6_I2_O) 0.326 26.233 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O net (fo=1, routed) 0.000 26.233 u_cpu/exe_stage/ds_to_es_bus[121] SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.031 27.127 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] ------------------------------------------------------------------- required time 27.127 arrival time -26.233 ------------------------------------------------------------------- slack 0.894 Slack (MET) : 0.921ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.855ns (logic 8.026ns (27.815%) route 20.829ns (72.185%)) Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.661 23.820 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X111Y153 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/I0 SLICE_X111Y153 LUT6 (Prop_lut6_I0_O) 0.124 23.944 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O net (fo=22, routed) 0.870 24.814 u_cpu/u_csr/ds_to_es_bus_r_reg[172] SLICE_X112Y150 f u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/I1 SLICE_X112Y150 LUT2 (Prop_lut2_I1_O) 0.117 24.931 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O net (fo=1, routed) 0.925 25.856 u_cpu/id_stage/ds_to_es_bus_r_reg[172] SLICE_X105Y154 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/I2 SLICE_X105Y154 LUT6 (Prop_lut6_I2_O) 0.348 26.204 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O net (fo=1, routed) 0.000 26.204 u_cpu/exe_stage/ds_to_es_bus[122] SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk SLICE_X105Y154 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/C clock pessimism -0.514 27.208 clock uncertainty -0.113 27.094 SLICE_X105Y154 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] ------------------------------------------------------------------- required time 27.125 arrival time -26.204 ------------------------------------------------------------------- slack 0.921 Slack (MET) : 0.943ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.831ns (logic 8.005ns (27.765%) route 20.826ns (72.235%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=9 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.866 24.418 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2_0 SLICE_X115Y152 f u_cpu/u_csr/ds_to_es_bus_r[192]_i_9/I0 SLICE_X115Y152 LUT5 (Prop_lut5_I0_O) 0.326 24.744 r u_cpu/u_csr/ds_to_es_bus_r[192]_i_9/O net (fo=1, routed) 0.415 25.158 u_cpu/id_stage/ds_to_es_bus_r_reg[192] SLICE_X111Y152 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_3/I3 SLICE_X111Y152 LUT4 (Prop_lut4_I3_O) 0.124 25.282 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_3/O net (fo=1, routed) 0.775 26.057 u_cpu/id_stage/ds_to_es_bus_r[192]_i_3_n_0 SLICE_X110Y159 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_1/I2 SLICE_X110Y159 LUT6 (Prop_lut6_I2_O) 0.124 26.181 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_1/O net (fo=1, routed) 0.000 26.181 u_cpu/exe_stage/ds_to_es_bus[142] SLICE_X110Y159 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.720 u_cpu/exe_stage/cpu_clk SLICE_X110Y159 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/C clock pessimism -0.514 27.207 clock uncertainty -0.113 27.093 SLICE_X110Y159 FDRE (Setup_fdre_C_D) 0.031 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[192] ------------------------------------------------------------------- required time 27.124 arrival time -26.181 ------------------------------------------------------------------- slack 0.943 Slack (MET) : 0.964ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.862ns (logic 7.809ns (27.057%) route 21.053ns (72.943%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.275ns = ( 27.725 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.492 23.006 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y154 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 SLICE_X101Y154 LUT6 (Prop_lut6_I4_O) 0.124 23.130 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O net (fo=32, routed) 1.058 24.188 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_4 SLICE_X103Y151 f u_cpu/id_stage/ds_to_es_bus_r[163]_i_7/I2 SLICE_X103Y151 LUT4 (Prop_lut4_I2_O) 0.124 24.312 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_7/O net (fo=1, routed) 0.590 24.902 u_cpu/id_stage/ds_to_es_bus_r[163]_i_7_n_0 SLICE_X102Y150 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_3/I4 SLICE_X102Y150 LUT5 (Prop_lut5_I4_O) 0.124 25.026 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_3/O net (fo=1, routed) 1.061 26.087 u_cpu/id_stage/ds_to_es_bus_r[163]_i_3_n_0 SLICE_X112Y150 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_1/I2 SLICE_X112Y150 LUT6 (Prop_lut6_I2_O) 0.124 26.211 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_1/O net (fo=1, routed) 0.000 26.211 u_cpu/exe_stage/ds_to_es_bus[113] SLICE_X112Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.554 27.725 u_cpu/exe_stage/cpu_clk SLICE_X112Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/C clock pessimism -0.514 27.212 clock uncertainty -0.113 27.098 SLICE_X112Y150 FDRE (Setup_fdre_C_D) 0.077 27.175 u_cpu/exe_stage/ds_to_es_bus_r_reg[163] ------------------------------------------------------------------- required time 27.175 arrival time -26.211 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.965ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.812ns (logic 8.005ns (27.784%) route 20.807ns (72.216%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=4 LUT5=8 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/I4 SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.118 23.551 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_25/O net (fo=19, routed) 0.702 24.253 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 SLICE_X114Y154 f u_cpu/id_stage/ds_to_es_bus_r[175]_i_7/I0 SLICE_X114Y154 LUT4 (Prop_lut4_I0_O) 0.326 24.579 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_7/O net (fo=1, routed) 0.772 25.352 u_cpu/id_stage/ds_to_es_bus_r[175]_i_7_n_0 SLICE_X112Y154 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_3/I2 SLICE_X112Y154 LUT4 (Prop_lut4_I2_O) 0.124 25.476 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_3/O net (fo=1, routed) 0.561 26.037 u_cpu/id_stage/ds_to_es_bus_r[175]_i_3_n_0 SLICE_X111Y153 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/I2 SLICE_X111Y153 LUT6 (Prop_lut6_I2_O) 0.124 26.161 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O net (fo=1, routed) 0.000 26.161 u_cpu/exe_stage/ds_to_es_bus[125] SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X111Y153 FDRE (Setup_fdre_C_D) 0.031 27.126 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] ------------------------------------------------------------------- required time 27.126 arrival time -26.161 ------------------------------------------------------------------- slack 0.965 Slack (MET) : 1.001ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.774ns (logic 7.809ns (27.139%) route 20.965ns (72.861%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O net (fo=15, routed) 0.935 25.244 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 SLICE_X117Y151 f u_cpu/id_stage/ds_to_es_bus_r[178]_i_2/I0 SLICE_X117Y151 LUT6 (Prop_lut6_I0_O) 0.124 25.368 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_2/O net (fo=1, routed) 0.631 26.000 u_cpu/id_stage/ds_to_es_bus_r[178]_i_2_n_0 SLICE_X110Y156 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/I1 SLICE_X110Y156 LUT6 (Prop_lut6_I1_O) 0.124 26.124 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O net (fo=1, routed) 0.000 26.124 u_cpu/exe_stage/ds_to_es_bus[128] SLICE_X110Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X110Y156 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X110Y156 FDRE (Setup_fdre_C_D) 0.029 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] ------------------------------------------------------------------- required time 27.124 arrival time -26.124 ------------------------------------------------------------------- slack 1.001 Slack (MET) : 1.021ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.754ns (logic 7.809ns (27.158%) route 20.945ns (72.842%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 27.722 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.940 24.099 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X110Y153 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/I0 SLICE_X110Y153 LUT6 (Prop_lut6_I0_O) 0.124 24.223 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 0.894 25.117 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 SLICE_X112Y150 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_2/I2 SLICE_X112Y150 LUT4 (Prop_lut4_I2_O) 0.124 25.241 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_2/O net (fo=1, routed) 0.738 25.979 u_cpu/id_stage/ds_to_es_bus_r[170]_i_2_n_0 SLICE_X111Y153 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I1 SLICE_X111Y153 LUT6 (Prop_lut6_I1_O) 0.124 26.103 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O net (fo=1, routed) 0.000 26.103 u_cpu/exe_stage/ds_to_es_bus[120] SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.551 27.722 u_cpu/exe_stage/cpu_clk SLICE_X111Y153 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/C clock pessimism -0.514 27.209 clock uncertainty -0.113 27.095 SLICE_X111Y153 FDRE (Setup_fdre_C_D) 0.029 27.124 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] ------------------------------------------------------------------- required time 27.124 arrival time -26.103 ------------------------------------------------------------------- slack 1.021 Slack (MET) : 1.037ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.784ns (logic 8.012ns (27.834%) route 20.772ns (72.165%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.761 24.317 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X112Y155 f u_cpu/u_csr/ds_to_es_bus_r[182]_i_8/I0 SLICE_X112Y155 LUT5 (Prop_lut5_I0_O) 0.332 24.649 r u_cpu/u_csr/ds_to_es_bus_r[182]_i_8/O net (fo=1, routed) 0.667 25.316 u_cpu/id_stage/ds_to_es_bus_r_reg[182] SLICE_X112Y154 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_2/I1 SLICE_X112Y154 LUT6 (Prop_lut6_I1_O) 0.124 25.440 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_2/O net (fo=1, routed) 0.569 26.010 u_cpu/id_stage/ds_to_es_bus_r[182]_i_2_n_0 SLICE_X108Y157 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_1/I1 SLICE_X108Y157 LUT6 (Prop_lut6_I1_O) 0.124 26.134 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_1/O net (fo=1, routed) 0.000 26.134 u_cpu/exe_stage/ds_to_es_bus[132] SLICE_X108Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk SLICE_X108Y157 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/C clock pessimism -0.514 27.208 clock uncertainty -0.113 27.094 SLICE_X108Y157 FDRE (Setup_fdre_C_D) 0.077 27.171 u_cpu/exe_stage/ds_to_es_bus_r_reg[182] ------------------------------------------------------------------- required time 27.171 arrival time -26.134 ------------------------------------------------------------------- slack 1.037 Slack (MET) : 1.065ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.709ns (logic 7.809ns (27.200%) route 20.900ns (72.800%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.521 23.035 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X101Y153 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/I2 SLICE_X101Y153 LUT6 (Prop_lut6_I2_O) 0.124 23.159 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.026 24.185 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X115Y152 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/I0 SLICE_X115Y152 LUT6 (Prop_lut6_I0_O) 0.124 24.309 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O net (fo=15, routed) 0.884 25.193 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 SLICE_X117Y153 f u_cpu/id_stage/ds_to_es_bus_r[187]_i_3/I3 SLICE_X117Y153 LUT6 (Prop_lut6_I3_O) 0.124 25.317 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_3/O net (fo=1, routed) 0.617 25.935 u_cpu/id_stage/ds_to_es_bus_r[187]_i_3_n_0 SLICE_X111Y158 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/I2 SLICE_X111Y158 LUT6 (Prop_lut6_I2_O) 0.124 26.059 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 26.059 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X111Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk SLICE_X111Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/C clock pessimism -0.514 27.208 clock uncertainty -0.113 27.094 SLICE_X111Y158 FDRE (Setup_fdre_C_D) 0.029 27.123 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 27.123 arrival time -26.059 ------------------------------------------------------------------- slack 1.065 Slack (MET) : 1.081ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.695ns (logic 8.005ns (27.897%) route 20.690ns (72.103%)) Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.920 23.433 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/I4 SLICE_X110Y154 LUT5 (Prop_lut5_I4_O) 0.124 23.557 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O net (fo=12, routed) 0.657 24.214 u_cpu/u_csr/ds_to_es_bus_r[166]_i_4_0 SLICE_X112Y151 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_8/I1 SLICE_X112Y151 LUT2 (Prop_lut2_I1_O) 0.116 24.330 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_8/O net (fo=1, routed) 0.808 25.138 u_cpu/u_csr/ds_to_es_bus_r[165]_i_8_n_0 SLICE_X111Y151 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/I0 SLICE_X111Y151 LUT6 (Prop_lut6_I0_O) 0.328 25.466 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O net (fo=1, routed) 0.455 25.920 u_cpu/id_stage/ds_to_es_bus_r_reg[165] SLICE_X109Y151 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/I3 SLICE_X109Y151 LUT6 (Prop_lut6_I3_O) 0.124 26.044 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 26.044 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X109Y151 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X109Y151 FDRE (Setup_fdre_C_D) 0.029 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 27.125 arrival time -26.044 ------------------------------------------------------------------- slack 1.081 Slack (MET) : 1.086ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.690ns (logic 8.012ns (27.926%) route 20.678ns (72.074%)) Logic Levels: 33 (CARRY4=6 LUT3=1 LUT4=2 LUT5=9 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.924 23.437 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X110Y154 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/I2 SLICE_X110Y154 LUT5 (Prop_lut5_I2_O) 0.119 23.556 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 0.950 24.506 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X115Y152 f u_cpu/u_csr/ds_to_es_bus_r[180]_i_8/I1 SLICE_X115Y152 LUT5 (Prop_lut5_I1_O) 0.332 24.838 r u_cpu/u_csr/ds_to_es_bus_r[180]_i_8/O net (fo=1, routed) 0.451 25.289 u_cpu/id_stage/ds_to_es_bus_r_reg[180] SLICE_X113Y152 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_2/I1 SLICE_X113Y152 LUT6 (Prop_lut6_I1_O) 0.124 25.413 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_2/O net (fo=1, routed) 0.502 25.916 u_cpu/id_stage/ds_to_es_bus_r[180]_i_2_n_0 SLICE_X110Y158 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/I1 SLICE_X110Y158 LUT6 (Prop_lut6_I1_O) 0.124 26.040 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O net (fo=1, routed) 0.000 26.040 u_cpu/exe_stage/ds_to_es_bus[130] SLICE_X110Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.550 27.721 u_cpu/exe_stage/cpu_clk SLICE_X110Y158 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C clock pessimism -0.514 27.208 clock uncertainty -0.113 27.094 SLICE_X110Y158 FDRE (Setup_fdre_C_D) 0.031 27.125 u_cpu/exe_stage/ds_to_es_bus_r_reg[180] ------------------------------------------------------------------- required time 27.125 arrival time -26.040 ------------------------------------------------------------------- slack 1.086 Slack (MET) : 1.129ns (required time - arrival time) Source: u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 28.694ns (logic 8.012ns (27.922%) route 20.682ns (72.078%)) Logic Levels: 33 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns = ( 27.723 - 30.000 ) Source Clock Delay (SCD): -2.651ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.691 -2.651 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X129Y140 FDRE r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y140 FDRE (Prop_fdre_C_Q) 0.419 -2.232 r u_cpu/addr_trans/tlb_entry/tlb_vppn_reg[28][9]/Q net (fo=7, routed) 1.161 -1.071 u_cpu/addr_trans/tlb_entry/p_1_in8_in[0] SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/I1 SLICE_X129Y142 LUT6 (Prop_lut6_I1_O) 0.297 -0.774 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118/O net (fo=1, routed) 0.000 -0.774 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_118_n_0 SLICE_X129Y142 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/S[0] SLICE_X129Y142 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 -0.242 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34/CO[3] net (fo=1, routed) 1.596 1.354 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_34_n_0 SLICE_X129Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I3 SLICE_X129Y151 LUT6 (Prop_lut6_I3_O) 0.124 1.478 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.694 2.172 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X132Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 SLICE_X132Y151 LUT4 (Prop_lut4_I2_O) 0.116 2.288 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.592 2.880 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X134Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 SLICE_X134Y151 LUT5 (Prop_lut5_I0_O) 0.354 3.234 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 0.485 3.719 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X136Y151 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 SLICE_X136Y151 LUT6 (Prop_lut6_I0_O) 0.326 4.045 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.000 5.045 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X147Y153 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/S SLICE_X147Y153 MUXF7 (Prop_muxf7_S_O) 0.296 5.341 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65/O net (fo=1, routed) 0.000 5.341 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_65_n_0 SLICE_X147Y153 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/I0 SLICE_X147Y153 MUXF8 (Prop_muxf8_I0_O) 0.104 5.445 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45/O net (fo=1, routed) 1.259 6.704 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[239]_i_45_n_0 SLICE_X134Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/I0 SLICE_X134Y155 LUT5 (Prop_lut5_I0_O) 0.316 7.020 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20/O net (fo=1, routed) 0.407 7.427 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_20_n_0 SLICE_X135Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/I5 SLICE_X135Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.551 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7/O net (fo=1, routed) 0.315 7.866 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_7_n_0 SLICE_X130Y155 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/I5 SLICE_X130Y155 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2/O net (fo=10, routed) 1.363 9.353 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[239]_i_2_n_0 SLICE_X119Y139 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/I3 SLICE_X119Y139 LUT6 (Prop_lut6_I3_O) 0.124 9.477 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[233]_i_1/O net (fo=6, routed) 1.633 11.110 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[14] SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/I2 SLICE_X107Y123 LUT6 (Prop_lut6_I2_O) 0.124 11.234 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 11.234 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X107Y123 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/S[1] SLICE_X107Y123 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 11.784 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 11.784 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X107Y124 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CI SLICE_X107Y124 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 12.012 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 0.828 12.840 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X104Y128 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/I0 SLICE_X104Y128 LUT3 (Prop_lut3_I0_O) 0.306 13.146 f u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 1.003 14.149 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X95Y131 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/I5 SLICE_X95Y131 LUT6 (Prop_lut6_I5_O) 0.348 14.497 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[44]_i_5/O net (fo=3, routed) 0.814 15.311 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[11] SLICE_X95Y140 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/I1 SLICE_X95Y140 LUT5 (Prop_lut5_I1_O) 0.124 15.435 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15/O net (fo=1, routed) 0.510 15.945 u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_15_n_0 SLICE_X96Y141 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/I0 SLICE_X96Y141 LUT6 (Prop_lut6_I0_O) 0.124 16.069 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_6/O net (fo=1, routed) 0.589 16.658 u_cpu/u_div/ms_to_ws_bus_r_reg[36] SLICE_X96Y146 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/I4 SLICE_X96Y146 LUT5 (Prop_lut5_I4_O) 0.124 16.782 f u_cpu/u_div/ms_to_ws_bus_r[36]_i_3/O net (fo=1, routed) 0.750 17.532 u_cpu/mem_stage/ms_to_ws_bus_r_reg[36]_0 SLICE_X97Y154 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/I5 SLICE_X97Y154 LUT6 (Prop_lut6_I5_O) 0.124 17.656 f u_cpu/mem_stage/ms_to_ws_bus_r[36]_i_1/O net (fo=5, routed) 0.595 18.251 u_cpu/id_stage/ms_to_ds_forward_bus[4] SLICE_X98Y154 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/I2 SLICE_X98Y154 LUT5 (Prop_lut5_I2_O) 0.124 18.375 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_19/O net (fo=1, routed) 0.000 18.375 u_cpu/id_stage/ds_to_es_bus_r[173]_i_19_n_0 SLICE_X98Y154 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/S[1] SLICE_X98Y154 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 18.908 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 18.908 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X98Y155 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CI SLICE_X98Y155 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 19.025 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, routed) 0.000 19.025 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 SLICE_X98Y156 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI SLICE_X98Y156 CARRY4 (Prop_carry4_CI_O[1]) 0.323 19.348 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, routed) 0.844 20.192 u_cpu/id_stage/rd_csr_addr0[12] SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 SLICE_X100Y156 LUT5 (Prop_lut5_I0_O) 0.332 20.524 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, routed) 0.668 21.192 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 SLICE_X100Y156 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 SLICE_X100Y156 LUT5 (Prop_lut5_I1_O) 0.328 21.520 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.435 21.954 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 SLICE_X100Y155 LUT4 (Prop_lut4_I3_O) 0.124 22.078 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.311 22.390 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X100Y155 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 SLICE_X100Y155 LUT6 (Prop_lut6_I5_O) 0.124 22.514 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.773 23.287 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X104Y153 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/I1 SLICE_X104Y153 LUT6 (Prop_lut6_I1_O) 0.124 23.411 f u_cpu/id_stage/ds_to_es_bus_r[174]_i_8/O net (fo=32, routed) 0.922 24.333 u_cpu/u_csr/ds_to_es_bus_r_reg[166]_0 SLICE_X111Y151 f u_cpu/u_csr/ds_to_es_bus_r[167]_i_9/I1 SLICE_X111Y151 LUT2 (Prop_lut2_I1_O) 0.119 24.452 r u_cpu/u_csr/ds_to_es_bus_r[167]_i_9/O net (fo=1, routed) 0.505 24.957 u_cpu/id_stage/ds_to_es_bus_r_reg[167] SLICE_X110Y151 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_3/I5 SLICE_X110Y151 LUT6 (Prop_lut6_I5_O) 0.332 25.289 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_3/O net (fo=1, routed) 0.631 25.920 u_cpu/id_stage/ds_to_es_bus_r[167]_i_3_n_0 SLICE_X108Y152 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/I2 SLICE_X108Y152 LUT6 (Prop_lut6_I2_O) 0.124 26.044 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 26.044 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X108Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.552 27.723 u_cpu/exe_stage/cpu_clk SLICE_X108Y152 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/C clock pessimism -0.514 27.210 clock uncertainty -0.113 27.096 SLICE_X108Y152 FDRE (Setup_fdre_C_D) 0.077 27.173 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 27.173 arrival time -26.044 ------------------------------------------------------------------- slack 1.129 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.040ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_csr/csr_badv_reg[0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.405ns (logic 0.186ns (45.911%) route 0.219ns (54.089%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.274ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/wb_stage/cpu_clk SLICE_X113Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[0]/Q net (fo=3, routed) 0.219 -0.314 u_cpu/wb_stage/ms_to_ws_bus_r_reg_n_0_[0] SLICE_X107Y149 r u_cpu/wb_stage/csr_badv[0]_i_1/I2 SLICE_X107Y149 LUT6 (Prop_lut6_I2_O) 0.045 -0.269 r u_cpu/wb_stage/csr_badv[0]_i_1/O net (fo=1, routed) 0.000 -0.269 u_cpu/u_csr/csr_badv_reg[31]_4[0] SLICE_X107Y149 FDRE r u_cpu/u_csr/csr_badv_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.863 -0.445 u_cpu/u_csr/cpu_clk SLICE_X107Y149 FDRE r u_cpu/u_csr/csr_badv_reg[0]/C clock pessimism 0.045 -0.400 SLICE_X107Y149 FDRE (Hold_fdre_C_D) 0.091 -0.309 u_cpu/u_csr/csr_badv_reg[0] ------------------------------------------------------------------- required time 0.309 arrival time -0.269 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.049ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk SLICE_X117Y149 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q net (fo=4, routed) 0.068 -0.458 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 SLICE_X116Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK SLICE_X116Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/CLK clock pessimism -0.213 -0.654 SLICE_X116Y149 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA ------------------------------------------------------------------- required time 0.507 arrival time -0.458 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.058ns (arrival time - required time) Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.400ns (logic 0.164ns (40.951%) route 0.236ns (59.049%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.453ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_cpu/mem_stage/cpu_clk SLICE_X98Y152 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y152 FDRE (Prop_fdre_C_Q) 0.164 -0.521 r u_cpu/mem_stage/es_to_ms_bus_r_reg[121]/Q net (fo=2, routed) 0.236 -0.284 u_cpu/wb_stage/ms_to_ws_bus[78] SLICE_X99Y148 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.855 -0.453 u_cpu/wb_stage/cpu_clk SLICE_X99Y148 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[114]/C clock pessimism 0.045 -0.408 SLICE_X99Y148 FDRE (Hold_fdre_C_D) 0.066 -0.342 u_cpu/wb_stage/ms_to_ws_bus_r_reg[114] ------------------------------------------------------------------- required time 0.342 arrival time -0.284 ------------------------------------------------------------------- slack 0.058 Slack (MET) : 0.061ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.683ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.580 -0.683 u_cpu/wb_stage/cpu_clk SLICE_X103Y161 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y161 FDRE (Prop_fdre_C_Q) 0.141 -0.542 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/Q net (fo=6, routed) 0.080 -0.462 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/DIA0 SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/WCLK SLICE_X102Y161 RAMD32 r u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA/CLK clock pessimism -0.212 -0.670 SLICE_X102Y161 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.523 u_cpu/u_regfile/rf_reg_r2_0_31_18_23/RAMA ------------------------------------------------------------------- required time 0.523 arrival time -0.462 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.355ns (logic 0.128ns (36.084%) route 0.227ns (63.916%)) Logic Levels: 0 Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.586 -0.677 u_cpu/exe_stage/cpu_clk SLICE_X105Y150 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y150 FDRE (Prop_fdre_C_Q) 0.128 -0.549 r u_cpu/exe_stage/ds_to_es_bus_r_reg[211]/Q net (fo=1, routed) 0.227 -0.322 u_cpu/mem_stage/D[126] SLICE_X106Y149 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.863 -0.445 u_cpu/mem_stage/cpu_clk SLICE_X106Y149 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[126]/C clock pessimism 0.045 -0.400 SLICE_X106Y149 FDRE (Hold_fdre_C_D) 0.016 -0.384 u_cpu/mem_stage/es_to_ms_bus_r_reg[126] ------------------------------------------------------------------- required time 0.384 arrival time -0.322 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMA_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMD32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMC_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.062ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.581ns (logic 0.141ns (24.271%) route 0.440ns (75.729%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.583 -0.680 u_cpu/wb_stage/cpu_clk SLICE_X97Y146 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y146 FDRE (Prop_fdre_C_Q) 0.141 -0.539 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.440 -0.099 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/ADDRD2 SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.460 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X96Y156 RAMS32 r u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1/CLK clock pessimism 0.045 -0.415 SLICE_X96Y156 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.161 u_cpu/u_regfile/rf_reg_r1_0_31_6_11/RAMD_D1 ------------------------------------------------------------------- required time 0.161 arrival time -0.099 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.063ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.223ns (logic 0.141ns (63.098%) route 0.082ns (36.902%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk SLICE_X121Y148 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo0_reg[26]/Q net (fo=4, routed) 0.082 -0.444 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/DIA0 SLICE_X120Y148 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/WCLK SLICE_X120Y148 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA/CLK clock pessimism -0.213 -0.654 SLICE_X120Y148 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_18_19/RAMA ------------------------------------------------------------------- required time 0.507 arrival time -0.444 ------------------------------------------------------------------- slack 0.063 Slack (MET) : 0.064ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.443ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.594 -0.669 u_cpu/u_csr/cpu_clk SLICE_X109Y149 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 r u_cpu/u_csr/csr_tlbelo0_reg[5]/Q net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.865 -0.443 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/WCLK SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP/CLK clock pessimism -0.213 -0.656 SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.512 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/SP ------------------------------------------------------------------- required time 0.512 arrival time -0.448 ------------------------------------------------------------------- slack 0.064 Slack (MET) : 0.066ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.226ns (logic 0.141ns (62.492%) route 0.085ns (37.508%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.441ns Source Clock Delay (SCD): -0.667ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.596 -0.667 u_cpu/u_csr/cpu_clk SLICE_X117Y147 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y147 FDRE (Prop_fdre_C_Q) 0.141 -0.526 r u_cpu/u_csr/csr_tlbelo1_reg[14]/Q net (fo=4, routed) 0.085 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIA0 SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.867 -0.441 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/WCLK SLICE_X116Y147 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/CLK clock pessimism -0.213 -0.654 SLICE_X116Y147 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.507 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.507 arrival time -0.441 ------------------------------------------------------------------- slack 0.066 Slack (MET) : 0.084ns (arrival time - required time) Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.403ns (logic 0.164ns (40.684%) route 0.239ns (59.316%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): -0.679ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.584 -0.679 u_cpu/mem_stage/cpu_clk SLICE_X98Y148 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y148 FDRE (Prop_fdre_C_Q) 0.164 -0.515 r u_cpu/mem_stage/es_to_ms_bus_r_reg[112]/Q net (fo=2, routed) 0.239 -0.276 u_cpu/wb_stage/ms_to_ws_bus[69] SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.851 -0.457 u_cpu/wb_stage/cpu_clk SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[105]/C clock pessimism 0.045 -0.412 SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.052 -0.360 u_cpu/wb_stage/ms_to_ws_bus_r_reg[105] ------------------------------------------------------------------- required time 0.360 arrival time -0.276 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.085ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.479ns (logic 0.141ns (29.406%) route 0.338ns (70.594%)) Logic Levels: 0 Clock Path Skew: 0.275ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.444ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.589 -0.674 u_cpu/u_csr/cpu_clk SLICE_X115Y150 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y150 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q net (fo=4, routed) 0.338 -0.194 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 SLICE_X112Y141 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.864 -0.444 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/WCLK SLICE_X112Y141 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/CLK clock pessimism 0.045 -0.399 SLICE_X112Y141 RAMD32 (Hold_ramd32_CLK_I) 0.120 -0.279 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 ------------------------------------------------------------------- required time 0.279 arrival time -0.194 ------------------------------------------------------------------- slack 0.085 Slack (MET) : 0.089ns (arrival time - required time) Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.415ns (logic 0.141ns (33.953%) route 0.274ns (66.047%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): -0.679ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.584 -0.679 u_cpu/mem_stage/cpu_clk SLICE_X97Y148 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y148 FDRE (Prop_fdre_C_Q) 0.141 -0.538 r u_cpu/mem_stage/es_to_ms_bus_r_reg[111]/Q net (fo=2, routed) 0.274 -0.264 u_cpu/wb_stage/ms_to_ws_bus[68] SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.851 -0.457 u_cpu/wb_stage/cpu_clk SLICE_X100Y150 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[104]/C clock pessimism 0.045 -0.412 SLICE_X100Y150 FDRE (Hold_fdre_C_D) 0.059 -0.353 u_cpu/wb_stage/ms_to_ws_bus_r_reg[104] ------------------------------------------------------------------- required time 0.353 arrival time -0.264 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.091ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo0_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.443ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.594 -0.669 u_cpu/u_csr/cpu_clk SLICE_X109Y149 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y149 FDRE (Prop_fdre_C_Q) 0.141 -0.528 r u_cpu/u_csr/csr_tlbelo0_reg[5]/Q net (fo=7, routed) 0.080 -0.448 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/D SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.865 -0.443 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/WCLK SLICE_X108Y149 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP/CLK clock pessimism -0.213 -0.656 SLICE_X108Y149 RAMD32 (Hold_ramd32_CLK_I) 0.117 -0.539 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r3_0_31_1_1/DP ------------------------------------------------------------------- required time 0.539 arrival time -0.448 ------------------------------------------------------------------- slack 0.091 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: cpu_clk Waveform(ns): { 0.000 15.000 } Period(ns): 30.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y47 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y47 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y46 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y46 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y48 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y48 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X7Y49 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X7Y49 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y50 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y50 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y51 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y51 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y48 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y48 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X8Y49 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X8Y49 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X6Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X6Y50 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.000 27.056 RAMB18_X5Y52 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.000 27.056 RAMB18_X5Y52 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.000 130.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y105 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X70Y103 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y118 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.000 13.750 SLICE_X84Y117 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- From Clock: mlkem_clk To Clock: mlkem_clk Setup : 0 Failing Endpoints, Worst Slack 0.070ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.057ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 5.250ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.070ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 13.035ns (logic 0.752ns (5.769%) route 12.283ns (94.231%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.283 10.259 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/S SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[732]_i_1/O net (fo=1, routed) 0.000 10.555 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[732] SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732]/C clock pessimism -0.498 10.655 clock uncertainty -0.093 10.562 SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[732] ------------------------------------------------------------------- required time 10.626 arrival time -10.555 ------------------------------------------------------------------- slack 0.070 Slack (MET) : 0.088ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.599ns (logic 3.356ns (26.636%) route 9.243ns (73.364%)) Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[2]) 0.256 7.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[2] net (fo=2, routed) 0.792 7.924 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[10] SLICE_X122Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/I1 SLICE_X122Y74 LUT6 (Prop_lut6_I1_O) 0.302 8.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_128/O net (fo=1, routed) 0.624 8.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_12 SLICE_X135Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/I5 SLICE_X135Y73 LUT6 (Prop_lut6_I5_O) 0.124 8.974 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0/O net (fo=1, routed) 0.448 9.422 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_82__0_n_0 SLICE_X139Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/I0 SLICE_X139Y72 LUT5 (Prop_lut5_I0_O) 0.124 9.546 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_25__0/O net (fo=1, routed) 0.534 10.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[10] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[10]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -10.080 ------------------------------------------------------------------- slack 0.088 Slack (MET) : 0.091ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.597ns (logic 3.064ns (24.324%) route 9.533ns (75.676%)) Logic Levels: 12 (CARRY4=1 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_O[3]) 0.606 6.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/O[3] net (fo=2, routed) 0.948 7.775 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[3] SLICE_X127Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/I1 SLICE_X127Y75 LUT6 (Prop_lut6_I1_O) 0.306 8.081 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_146__0/O net (fo=1, routed) 0.620 8.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_5 SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/I5 SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.825 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0/O net (fo=1, routed) 0.419 9.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_92__0_n_0 SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/I0 SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.368 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_32__1/O net (fo=1, routed) 0.709 10.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[3] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[3] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[3]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -10.077 ------------------------------------------------------------------- slack 0.091 Slack (MET) : 0.128ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 13.053ns (logic 0.752ns (5.761%) route 12.301ns (94.239%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/S SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.296 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[948]_i_1/O net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[948] SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[948] ------------------------------------------------------------------- required time 10.701 arrival time -10.573 ------------------------------------------------------------------- slack 0.128 Slack (MET) : 0.129ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.558ns (logic 3.335ns (26.557%) route 9.223ns (73.443%)) Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[1]) 0.348 7.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[1] net (fo=2, routed) 1.107 8.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[5] SLICE_X130Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/I1 SLICE_X130Y74 LUT6 (Prop_lut6_I1_O) 0.303 8.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_140__0/O net (fo=1, routed) 0.438 8.948 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_7 SLICE_X134Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/I5 SLICE_X134Y74 LUT6 (Prop_lut6_I5_O) 0.124 9.072 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0/O net (fo=1, routed) 0.438 9.510 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_89__0_n_0 SLICE_X138Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/I0 SLICE_X138Y74 LUT5 (Prop_lut5_I0_O) 0.124 9.634 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_30__0/O net (fo=1, routed) 0.404 10.038 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[5] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[5] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[5]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -10.038 ------------------------------------------------------------------- slack 0.129 Slack (MET) : 0.135ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.971ns (logic 0.732ns (5.643%) route 12.239ns (94.357%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.847ns = ( 11.153 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.239 10.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X145Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/S SLICE_X145Y37 MUXF7 (Prop_muxf7_S_O) 0.276 10.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[731]_i_1/O net (fo=1, routed) 0.000 10.491 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[731] SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.982 11.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X145Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731]/C clock pessimism -0.498 10.655 clock uncertainty -0.093 10.562 SLICE_X145Y37 FDCE (Setup_fdce_C_D) 0.064 10.626 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[731] ------------------------------------------------------------------- required time 10.626 arrival time -10.491 ------------------------------------------------------------------- slack 0.135 Slack (MET) : 0.151ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.581ns (logic 3.752ns (29.822%) route 8.829ns (70.178%)) Logic Levels: 16 (CARRY4=3 LUT2=1 LUT5=3 LUT6=5 MUXF7=2 MUXF8=2) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) Source Clock Delay (SCD): -2.481ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O net (fo=29, routed) 0.725 6.593 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 SLICE_X139Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/I3 SLICE_X139Y84 LUT5 (Prop_lut5_I3_O) 0.124 6.717 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219/O net (fo=4, routed) 0.833 7.549 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_219_n_0 SLICE_X141Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/I3 SLICE_X141Y85 LUT6 (Prop_lut6_I3_O) 0.124 7.673 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_146/O net (fo=2, routed) 0.809 8.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_21 SLICE_X140Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/I5 SLICE_X140Y86 LUT6 (Prop_lut6_I5_O) 0.124 8.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76/O net (fo=12, routed) 0.918 9.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_76_n_0 SLICE_X140Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/I1 SLICE_X140Y87 LUT6 (Prop_lut6_I1_O) 0.124 9.648 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_28/O net (fo=1, routed) 0.453 10.101 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[5] RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[5] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK clock pessimism -0.426 10.586 clock uncertainty -0.093 10.493 RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5]) -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- required time 10.252 arrival time -10.101 ------------------------------------------------------------------- slack 0.151 Slack (MET) : 0.155ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.532ns (logic 3.449ns (27.521%) route 9.083ns (72.479%)) Logic Levels: 14 (CARRY4=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI SLICE_X106Y74 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 6.867 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CO[3] net (fo=1, routed) 0.009 6.876 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1_n_0 SLICE_X106Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/CI SLICE_X106Y75 CARRY4 (Prop_carry4_CI_O[1]) 0.348 7.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_1/O[1] net (fo=2, routed) 0.351 7.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[9] SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/I1 SLICE_X107Y75 LUT6 (Prop_lut6_I1_O) 0.303 7.878 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_129/O net (fo=1, routed) 0.264 8.142 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_11 SLICE_X107Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/I5 SLICE_X107Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.266 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0/O net (fo=1, routed) 0.991 9.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_83__0_n_0 SLICE_X138Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/I0 SLICE_X138Y75 LUT5 (Prop_lut5_I0_O) 0.124 9.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_26__0/O net (fo=1, routed) 0.632 10.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[9] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[9] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[9]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -10.013 ------------------------------------------------------------------- slack 0.155 Slack (MET) : 0.157ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.530ns (logic 3.242ns (25.874%) route 9.288ns (74.126%)) Logic Levels: 13 (CARRY4=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.000ns = ( 11.000 - 13.000 ) Source Clock Delay (SCD): -2.520ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X74Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/C ------------------------------------------------------------------- ------------------- SLICE_X74Y66 FDCE (Prop_fdce_C_Q) 0.478 -2.042 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep/Q net (fo=103, routed) 1.533 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg[6]_rep_n_0 SLICE_X78Y76 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/I2 SLICE_X78Y76 LUT6 (Prop_lut6_I2_O) 0.295 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438/O net (fo=2, routed) 0.828 0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_438_n_0 SLICE_X75Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/I1 SLICE_X75Y72 LUT6 (Prop_lut6_I1_O) 0.124 0.739 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195/O net (fo=2, routed) 0.692 1.431 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_195_n_0 SLICE_X82Y72 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/I0 SLICE_X82Y72 LUT6 (Prop_lut6_I0_O) 0.124 1.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87/O net (fo=4, routed) 0.606 2.161 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_87_n_0 SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/I5 SLICE_X83Y69 LUT6 (Prop_lut6_I5_O) 0.124 2.285 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43/O net (fo=1, routed) 0.000 2.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_43_n_0 SLICE_X83Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/I0 SLICE_X83Y69 MUXF7 (Prop_muxf7_I0_O) 0.212 2.497 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20/O net (fo=1, routed) 0.915 3.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[11]_i_20_n_0 SLICE_X98Y69 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/I4 SLICE_X98Y69 LUT5 (Prop_lut5_I4_O) 0.299 3.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10/O net (fo=2, routed) 1.263 4.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_10_n_0 SLICE_X107Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/I4 SLICE_X107Y73 LUT6 (Prop_lut6_I4_O) 0.124 5.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7/O net (fo=12, routed) 0.998 6.097 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[11]_i_7_n_0 SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/I2 SLICE_X106Y73 LUT4 (Prop_lut4_I2_O) 0.124 6.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6/O net (fo=1, routed) 0.000 6.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data[3]_i_6_n_0 SLICE_X106Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/S[0] SLICE_X106Y73 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 6.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 6.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[3]_i_1_n_0 SLICE_X106Y74 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/CI SLICE_X106Y74 CARRY4 (Prop_carry4_CI_O[2]) 0.256 7.009 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/cbdw_data_reg[7]_i_1/O[2] net (fo=2, routed) 0.982 7.991 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/D[6] SLICE_X129Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/I1 SLICE_X129Y75 LUT6 (Prop_lut6_I1_O) 0.302 8.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg_i_139/O net (fo=1, routed) 0.435 8.728 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_8 SLICE_X134Y75 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/I5 SLICE_X134Y75 LUT6 (Prop_lut6_I5_O) 0.124 8.852 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0/O net (fo=1, routed) 0.503 9.356 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_88__0_n_0 SLICE_X138Y73 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/I0 SLICE_X138Y73 LUT5 (Prop_lut5_I0_O) 0.124 9.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_29__0/O net (fo=1, routed) 0.531 10.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DIADI[6] RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/DIADI[6] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.828 11.000 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X7Y14 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism -0.498 10.502 clock uncertainty -0.093 10.409 RAMB36_X7Y14 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[6]) -0.241 10.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 10.168 arrival time -10.011 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.159ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 13.071ns (logic 0.770ns (5.891%) route 12.301ns (94.109%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.301 10.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X162Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/S SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.314 10.591 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[943]_i_2/O net (fo=1, routed) 0.000 10.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[943] SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[943] ------------------------------------------------------------------- required time 10.750 arrival time -10.591 ------------------------------------------------------------------- slack 0.159 Slack (MET) : 0.175ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.935ns (logic 0.818ns (6.324%) route 12.117ns (93.676%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: 0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.842ns = ( 11.158 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 12.117 10.093 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/I2 SLICE_X155Y43 LUT4 (Prop_lut4_I2_O) 0.124 10.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3/O net (fo=1, routed) 0.000 10.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[975]_i_3_n_0 SLICE_X155Y43 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/I0 SLICE_X155Y43 MUXF7 (Prop_muxf7_I0_O) 0.238 10.455 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[975]_i_2/O net (fo=1, routed) 0.000 10.455 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[975] SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.987 11.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X155Y43 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975]/C clock pessimism -0.498 10.660 clock uncertainty -0.093 10.567 SLICE_X155Y43 FDCE (Setup_fdce_C_D) 0.064 10.631 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[975] ------------------------------------------------------------------- required time 10.631 arrival time -10.455 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.181ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 13.053ns (logic 0.789ns (6.045%) route 12.264ns (93.955%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: 0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.768ns = ( 11.232 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 12.264 10.240 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/I2 SLICE_X162Y40 LUT4 (Prop_lut4_I2_O) 0.124 10.364 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2/O net (fo=1, routed) 0.000 10.364 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[888]_i_2_n_0 SLICE_X162Y40 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/I0 SLICE_X162Y40 MUXF7 (Prop_muxf7_I0_O) 0.209 10.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[888]_i_1/O net (fo=1, routed) 0.000 10.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[888] SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.061 11.232 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X162Y40 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888]/C clock pessimism -0.498 10.734 clock uncertainty -0.093 10.641 SLICE_X162Y40 FDCE (Setup_fdce_C_D) 0.113 10.754 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[888] ------------------------------------------------------------------- required time 10.754 arrival time -10.573 ------------------------------------------------------------------- slack 0.181 Slack (MET) : 0.181ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.552ns (logic 3.951ns (31.478%) route 8.601ns (68.522%)) Logic Levels: 16 (CARRY4=3 LUT2=1 LUT3=1 LUT5=2 LUT6=5 MUXF7=2 MUXF8=2) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) Source Clock Delay (SCD): -2.481ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O net (fo=29, routed) 0.719 6.587 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/I1 SLICE_X139Y86 LUT3 (Prop_lut3_I1_O) 0.120 6.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_91/O net (fo=3, routed) 0.689 7.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_166_n_0 SLICE_X141Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/I0 SLICE_X141Y84 LUT6 (Prop_lut6_I0_O) 0.327 7.723 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_143/O net (fo=2, routed) 0.726 8.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_18 SLICE_X141Y87 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/I2 SLICE_X141Y87 LUT6 (Prop_lut6_I2_O) 0.124 8.573 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78/O net (fo=12, routed) 1.061 9.634 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_78_n_0 SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/I3 SLICE_X140Y88 LUT6 (Prop_lut6_I3_O) 0.124 9.758 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_26/O net (fo=1, routed) 0.313 10.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[7] RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[7] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK clock pessimism -0.426 10.586 clock uncertainty -0.093 10.493 RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7]) -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- required time 10.252 arrival time -10.071 ------------------------------------------------------------------- slack 0.181 Slack (MET) : 0.185ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.995ns (logic 0.732ns (5.633%) route 12.263ns (94.367%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.209ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.773ns = ( 11.227 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.263 10.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X160Y33 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/S SLICE_X160Y33 MUXF7 (Prop_muxf7_S_O) 0.276 10.515 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O net (fo=1, routed) 0.000 10.515 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[812] SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.056 11.227 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X160Y33 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/C clock pessimism -0.498 10.729 clock uncertainty -0.093 10.636 SLICE_X160Y33 FDCE (Setup_fdce_C_D) 0.064 10.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] ------------------------------------------------------------------- required time 10.700 arrival time -10.515 ------------------------------------------------------------------- slack 0.185 Slack (MET) : 0.188ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.992ns (logic 0.732ns (5.634%) route 12.260ns (94.366%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X163Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/S SLICE_X163Y34 MUXF7 (Prop_muxf7_S_O) 0.276 10.513 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[946]_i_1/O net (fo=1, routed) 0.000 10.513 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[946] SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X163Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X163Y34 FDCE (Setup_fdce_C_D) 0.064 10.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[946] ------------------------------------------------------------------- required time 10.701 arrival time -10.513 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.208ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.969ns (logic 0.732ns (5.644%) route 12.237ns (94.356%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.775ns = ( 11.225 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.237 10.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X159Y32 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[921]_i_1/S SLICE_X159Y32 MUXF7 (Prop_muxf7_S_O) 0.276 10.490 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[921]_i_1/O net (fo=1, routed) 0.000 10.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[921] SLICE_X159Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.054 11.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X159Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921]/C clock pessimism -0.498 10.727 clock uncertainty -0.093 10.634 SLICE_X159Y32 FDCE (Setup_fdce_C_D) 0.064 10.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[921] ------------------------------------------------------------------- required time 10.698 arrival time -10.490 ------------------------------------------------------------------- slack 0.208 Slack (MET) : 0.216ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[6] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.516ns (logic 4.831ns (38.597%) route 7.685ns (61.403%)) Logic Levels: 16 (CARRY4=5 LUT2=2 LUT5=2 LUT6=3 MUXF7=2 MUXF8=2) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.988ns = ( 11.012 - 13.000 ) Source Clock Delay (SCD): -2.481ns Clock Pessimism Removal (CPR): -0.426ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.861 -2.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X118Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y91 FDCE (Prop_fdce_C_Q) 0.419 -2.062 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg[0]/Q net (fo=67, routed) 1.328 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_awidx_reg_n_0_[0] SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/I4 SLICE_X119Y93 LUT6 (Prop_lut6_I4_O) 0.297 -0.437 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454/O net (fo=1, routed) 0.000 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_454_n_0 SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/I1 SLICE_X119Y93 MUXF7 (Prop_muxf7_I1_O) 0.217 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_398_n_0 SLICE_X119Y93 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/I1 SLICE_X119Y93 MUXF8 (Prop_muxf8_I1_O) 0.094 -0.126 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370/O net (fo=1, routed) 0.885 0.759 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_370_n_0 SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/I5 SLICE_X121Y90 LUT6 (Prop_lut6_I5_O) 0.316 1.075 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356/O net (fo=1, routed) 0.000 1.075 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_356_n_0 SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/I0 SLICE_X121Y90 MUXF7 (Prop_muxf7_I0_O) 0.212 1.287 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350/O net (fo=1, routed) 0.000 1.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_350_n_0 SLICE_X121Y90 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/I1 SLICE_X121Y90 MUXF8 (Prop_muxf8_I1_O) 0.094 1.381 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mem_reg_i_292/O net (fo=12, routed) 0.984 2.365 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_0 SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/I1 SLICE_X134Y85 LUT2 (Prop_lut2_I1_O) 0.316 2.681 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212/O net (fo=1, routed) 0.000 2.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_212_n_0 SLICE_X134Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/S[0] SLICE_X134Y85 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 3.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115/CO[3] net (fo=1, routed) 0.000 3.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_115_n_0 SLICE_X134Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CI SLICE_X134Y86 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3.327 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_173/CO[3] net (fo=1, routed) 0.000 3.327 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_169[0] SLICE_X134Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/CI SLICE_X134Y87 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.549 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_i_148__0/O[0] net (fo=9, routed) 1.041 4.590 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/O[0] SLICE_X136Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/I4 SLICE_X136Y85 LUT5 (Prop_lut5_I4_O) 0.299 4.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207/O net (fo=1, routed) 0.855 5.744 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_207_n_0 SLICE_X138Y84 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/I3 SLICE_X138Y84 LUT5 (Prop_lut5_I3_O) 0.124 5.868 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_114/O net (fo=29, routed) 0.651 6.519 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub11 SLICE_X139Y85 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_182/I0 SLICE_X139Y85 LUT2 (Prop_lut2_I0_O) 0.150 6.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_182/O net (fo=1, routed) 0.617 7.286 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/u_vsub1[0] SLICE_X139Y86 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100/CYINIT SLICE_X139Y86 CARRY4 (Prop_carry4_CYINIT_CO[3]) 0.788 8.074 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100/CO[3] net (fo=1, routed) 0.000 8.074 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_100_n_0 SLICE_X139Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_87/CI SLICE_X139Y87 CARRY4 (Prop_carry4_CI_O[1]) 0.334 8.408 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg_i_87/O[1] net (fo=1, routed) 1.013 9.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_vq0[5] SLICE_X140Y88 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_27/I0 SLICE_X140Y88 LUT6 (Prop_lut6_I0_O) 0.303 9.723 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_reg_i_27/O net (fo=1, routed) 0.313 10.036 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/DIADI[6] RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/DIADI[6] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.840 11.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mlkem_clk RAMB18_X7Y35 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK clock pessimism -0.426 10.586 clock uncertainty -0.093 10.493 RAMB18_X7Y35 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[6]) -0.241 10.252 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg ------------------------------------------------------------------- required time 10.252 arrival time -10.036 ------------------------------------------------------------------- slack 0.216 Slack (MET) : 0.221ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 13.008ns (logic 0.748ns (5.750%) route 12.260ns (94.250%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.772ns = ( 11.228 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.260 10.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X162Y34 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[936]_i_1/S SLICE_X162Y34 MUXF7 (Prop_muxf7_S_O) 0.292 10.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[936]_i_1/O net (fo=1, routed) 0.000 10.529 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[936] SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.057 11.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X162Y34 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936]/C clock pessimism -0.498 10.730 clock uncertainty -0.093 10.637 SLICE_X162Y34 FDCE (Setup_fdce_C_D) 0.113 10.750 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[936] ------------------------------------------------------------------- required time 10.750 arrival time -10.529 ------------------------------------------------------------------- slack 0.221 Slack (MET) : 0.223ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.960ns (logic 0.752ns (5.803%) route 12.208ns (94.197%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.212ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.770ns = ( 11.230 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.208 10.184 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X160Y37 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[817]_i_1/S SLICE_X160Y37 MUXF7 (Prop_muxf7_S_O) 0.296 10.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[817]_i_1/O net (fo=1, routed) 0.000 10.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[817] SLICE_X160Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.059 11.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X160Y37 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817]/C clock pessimism -0.498 10.732 clock uncertainty -0.093 10.639 SLICE_X160Y37 FDCE (Setup_fdce_C_D) 0.064 10.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[817] ------------------------------------------------------------------- required time 10.703 arrival time -10.480 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.230ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 12.947ns (logic 0.732ns (5.654%) route 12.215ns (94.346%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.775ns = ( 11.225 - 13.000 ) Source Clock Delay (SCD): -2.480ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.862 -2.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X125Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/C ------------------------------------------------------------------- ------------------- SLICE_X125Y88 FDRE (Prop_fdre_C_Q) 0.456 -2.024 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg/Q net (fo=1088, routed) 12.215 10.192 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_2 SLICE_X156Y32 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[874]_i_1/S SLICE_X156Y32 MUXF7 (Prop_muxf7_S_O) 0.276 10.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[874]_i_1/O net (fo=1, routed) 0.000 10.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_1_in__1[874] SLICE_X156Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 2.054 11.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X156Y32 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874]/C clock pessimism -0.498 10.727 clock uncertainty -0.093 10.634 SLICE_X156Y32 FDCE (Setup_fdce_C_D) 0.064 10.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[874] ------------------------------------------------------------------- required time 10.698 arrival time -10.468 ------------------------------------------------------------------- slack 0.230 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.057ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.276ns (logic 0.141ns (51.000%) route 0.135ns (49.000%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.445ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X135Y114 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X135Y114 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[6]/Q net (fo=7, routed) 0.135 -0.394 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[6] SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.863 -0.445 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X136Y113 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK clock pessimism -0.189 -0.634 SLICE_X136Y113 SRL16E (Hold_srl16e_CLK_D) 0.183 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[6]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.451 arrival time -0.394 ------------------------------------------------------------------- slack 0.057 Slack (MET) : 0.062ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.455ns (logic 0.164ns (36.015%) route 0.291ns (63.985%)) Logic Levels: 0 Clock Path Skew: 0.334ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.375ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.594 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X108Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[16]/Q net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[16] SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.933 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16]/C clock pessimism 0.040 -0.335 SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.059 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[16] ------------------------------------------------------------------- required time 0.276 arrival time -0.214 ------------------------------------------------------------------- slack 0.062 Slack (MET) : 0.069ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.455ns (logic 0.164ns (36.017%) route 0.291ns (63.983%)) Logic Levels: 0 Clock Path Skew: 0.334ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.375ns Source Clock Delay (SCD): -0.669ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.594 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X108Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y101 FDCE (Prop_fdce_C_Q) 0.164 -0.505 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3_reg[17]/Q net (fo=1, routed) 0.291 -0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s3[17] SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.933 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X104Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17]/C clock pessimism 0.040 -0.335 SLICE_X104Y98 FDCE (Hold_fdce_C_D) 0.052 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s4_reg[17] ------------------------------------------------------------------- required time 0.283 arrival time -0.214 ------------------------------------------------------------------- slack 0.069 Slack (MET) : 0.085ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.281ns (logic 0.141ns (50.089%) route 0.140ns (49.911%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.211ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X133Y115 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[7]/Q net (fo=6, routed) 0.140 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[7] SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.862 -0.446 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK clock pessimism -0.211 -0.657 SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) 0.183 -0.474 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[7]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.474 arrival time -0.388 ------------------------------------------------------------------- slack 0.085 Slack (MET) : 0.089ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[5] RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mlkem_clk RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK clock pessimism 0.040 -0.333 RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.061 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.089ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.514ns (logic 0.164ns (31.895%) route 0.350ns (68.105%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]/Q net (fo=8, routed) 0.350 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[5] RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mlkem_clk RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK clock pessimism 0.040 -0.333 RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.061 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.103ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D (rising edge-triggered cell SRL16E clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.233ns (logic 0.141ns (60.420%) route 0.092ns (39.580%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.446ns Source Clock Delay (SCD): -0.670ns Clock Pessimism Removal (CPR): 0.211ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.593 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X133Y115 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y115 FDCE (Prop_fdce_C_Q) 0.141 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r_reg[2]/Q net (fo=7, routed) 0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_r[2] SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.862 -0.446 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/mlkem_clk SLICE_X132Y115 SRL16E r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3/CLK clock pessimism -0.211 -0.657 SLICE_X132Y115 SRL16E (Hold_srl16e_CLK_D) 0.117 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf1/a_d4_reg[2]_srl5_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_a0d_reg_c_3 ------------------------------------------------------------------- required time 0.540 arrival time -0.437 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[7] RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mlkem_clk RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK clock pessimism 0.040 -0.333 RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.040 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.536ns (logic 0.164ns (30.622%) route 0.372ns (69.378%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.372 -0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[7] RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mlkem_clk RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK clock pessimism 0.040 -0.333 RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.040 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.303ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/Q[6] RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.005 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mlkem_clk RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKARDCLK clock pessimism -0.214 -0.517 RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg ------------------------------------------------------------------- required time 0.334 arrival time -0.223 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.352ns (logic 0.164ns (46.530%) route 0.188ns (53.470%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.303ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[7]/Q net (fo=6, routed) 0.188 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/Q[6] RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRARDADDR[10] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.005 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mlkem_clk RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKARDCLK clock pessimism -0.214 -0.517 RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[10]) 0.183 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg ------------------------------------------------------------------- required time 0.334 arrival time -0.223 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[19]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[19] SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.935 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19]/C clock pessimism -0.229 -0.602 SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.078 -0.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[19] ------------------------------------------------------------------- required time 0.524 arrival time -0.405 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.301ns (logic 0.141ns (46.859%) route 0.160ns (53.141%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X57Y91 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y91 FDRE (Prop_fdre_C_Q) 0.141 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/Q net (fo=1, routed) 0.160 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIC0 SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK clock pessimism -0.192 -0.573 SLICE_X52Y90 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.429 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC ------------------------------------------------------------------- required time 0.429 arrival time -0.309 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.410ns (logic 0.186ns (45.405%) route 0.224ns (54.595%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.442ns Source Clock Delay (SCD): -0.600ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.662 -0.600 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X118Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y99 FDCE (Prop_fdce_C_Q) 0.141 -0.459 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0_reg[0]/Q net (fo=29, routed) 0.224 -0.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/d_s0[0] SLICE_X114Y100 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/I1 SLICE_X114Y100 LUT6 (Prop_lut6_I1_O) 0.045 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1[5]_i_1/O net (fo=1, routed) 0.000 -0.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_next0[5] SLICE_X114Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.866 -0.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X114Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5]/C clock pessimism 0.040 -0.402 SLICE_X114Y100 FDCE (Hold_fdce_C_D) 0.091 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_dividend_s1_reg[5] ------------------------------------------------------------------- required time 0.311 arrival time -0.191 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.598 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X138Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg_0[4] RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/ADDRBWRADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.004 -0.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mlkem_clk RAMB18_X7Y39 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKBWRCLK clock pessimism 0.040 -0.263 RAMB18_X7Y39 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.040 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.705ns (logic 0.141ns (20.006%) route 0.564ns (79.994%)) Logic Levels: 0 Clock Path Skew: 0.401ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.304ns Source Clock Delay (SCD): -0.665ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.598 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X138Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/issue_cnt_reg[4]/Q net (fo=7, routed) 0.564 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg_0[4] RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/ADDRBWRADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.004 -0.304 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mlkem_clk RAMB18_X7Y38 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKBWRCLK clock pessimism 0.040 -0.263 RAMB18_X7Y38 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8]) 0.183 -0.080 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg ------------------------------------------------------------------- required time 0.080 arrival time 0.040 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.373ns Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.461 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1_reg[18]/Q net (fo=1, routed) 0.056 -0.405 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s1[18] SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.935 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X115Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18]/C clock pessimism -0.229 -0.602 SLICE_X115Y95 FDCE (Hold_fdce_C_D) 0.076 -0.526 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_rounded_s2_reg[18] ------------------------------------------------------------------- required time 0.526 arrival time -0.405 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/Q[1] RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/ADDRARDADDR[4] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mlkem_clk RAMB18_X7Y40 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK clock pessimism 0.040 -0.333 RAMB18_X7Y40 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.029 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] (rising edge-triggered cell RAMB18E1 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.546ns (logic 0.164ns (30.040%) route 0.382ns (69.960%)) Logic Levels: 0 Clock Path Skew: 0.242ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.374ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.687 -0.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mlkem_clk SLICE_X140Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]/Q net (fo=9, routed) 0.382 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/Q[1] RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/ADDRARDADDR[4] ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mlkem_clk RAMB18_X7Y41 RAMB18E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK clock pessimism 0.040 -0.333 RAMB18_X7Y41 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[4]) 0.183 -0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg ------------------------------------------------------------------- required time 0.150 arrival time -0.029 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: mlkem_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.141ns (29.899%) route 0.331ns (70.101%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.331 -0.147 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/ADDRD0 SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X64Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK clock pessimism -0.192 -0.578 SLICE_X64Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.268 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA ------------------------------------------------------------------- required time 0.268 arrival time -0.147 ------------------------------------------------------------------- slack 0.122 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: mlkem_clk Waveform(ns): { 0.000 6.500 } Period(ns): 13.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y39 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y38 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y40 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y41 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB36_X7Y14 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y37 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X8Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X6Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y36 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y44 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y43 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y42 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 13.000 10.056 RAMB18_X7Y45 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y39 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y38 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y40 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 13.000 10.424 RAMB18_X7Y41 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg/CLKBWRCLK Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 13.000 147.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X52Y90 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 6.500 5.250 SLICE_X68Y89 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 6.500 5.250 SLICE_X66Y88 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- From Clock: sys_clk To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 0.125ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.024ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.125ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.605ns (logic 5.201ns (33.326%) route 10.404ns (66.674%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1 SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) 0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O net (fo=2, routed) 4.015 9.671 ext_ram_data_IOBUF[18]_inst/I AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I AB17 OBUFT (Prop_obuft_I_O) 3.527 13.197 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 13.197 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -13.197 ------------------------------------------------------------------- slack 0.125 Slack (MET) : 0.253ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.397ns (logic 6.886ns (44.722%) route 8.511ns (55.278%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.846 9.523 ext_ram_data_IOBUF[21]_inst/T AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T AC16 OBUFT (TriStatE_obuft_T_O) 3.546 13.069 r ext_ram_data_IOBUF[21]_inst/OBUFT/O net (fo=1, unset) 0.000 13.069 ext_ram_data[21] AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -13.069 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.342ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.308ns (logic 6.883ns (44.963%) route 8.425ns (55.037%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.760 9.437 ext_ram_data_IOBUF[22]_inst/T Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T Y15 OBUFT (TriStatE_obuft_T_O) 3.543 12.980 r ext_ram_data_IOBUF[22]_inst/OBUFT/O net (fo=1, unset) 0.000 12.980 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.980 ------------------------------------------------------------------- slack 0.342 Slack (MET) : 0.395ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.335ns (logic 5.244ns (34.199%) route 10.090ns (65.801%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.322 2.300 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRB1 SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/RADR1 SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) 0.152 2.452 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMB/O net (fo=1, routed) 0.667 3.119 u_matmul_axi_slave/ep_rd_c1[20] SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/I0 SLICE_X24Y78 LUT4 (Prop_lut4_I0_O) 0.348 3.467 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0/O net (fo=1, routed) 0.430 3.897 u_matmul_axi_slave/ram_reg_0_7_18_23_i_22__0_n_0 SLICE_X24Y78 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/I4 SLICE_X24Y78 LUT5 (Prop_lut5_I4_O) 0.124 4.021 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_16__0/O net (fo=1, routed) 0.598 4.620 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[20] SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/I5 SLICE_X28Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.744 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__1/O net (fo=3, routed) 0.682 5.425 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] SLICE_X28Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 SLICE_X28Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.549 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O net (fo=2, routed) 3.834 9.383 ext_ram_data_IOBUF[20]_inst/I AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I AD18 OBUFT (Prop_obuft_I_O) 3.544 12.927 r ext_ram_data_IOBUF[20]_inst/OBUFT/O net (fo=1, unset) 0.000 12.927 ext_ram_data[20] AD18 r ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.927 ------------------------------------------------------------------- slack 0.395 Slack (MET) : 0.403ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.248ns (logic 6.876ns (45.098%) route 8.371ns (54.902%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.706 9.383 ext_ram_data_IOBUF[16]_inst/T AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T AB16 OBUFT (TriStatE_obuft_T_O) 3.536 12.919 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.919 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.919 ------------------------------------------------------------------- slack 0.403 Slack (MET) : 0.416ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[6] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.314ns (logic 5.138ns (33.551%) route 10.176ns (66.449%)) Logic Levels: 8 (LUT3=1 LUT4=1 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.690 2.668 u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/ADDRB1 SLICE_X36Y83 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/RADR1 SLICE_X36Y83 RAMD32 (Prop_ramd32_RADR1_O) 0.152 2.820 r u_matmul_axi_slave/b1_c_reg_r2_0_15_36_41/RAMB/O net (fo=1, routed) 1.421 4.241 u_matmul_axi_slave/ep_rd_c1[38] SLICE_X23Y79 r u_matmul_axi_slave/ram_reg_i_46/I3 SLICE_X23Y79 LUT5 (Prop_lut5_I3_O) 0.348 4.589 r u_matmul_axi_slave/ram_reg_i_46/O net (fo=1, routed) 0.461 5.050 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[6] SLICE_X19Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/I5 SLICE_X19Y79 LUT6 (Prop_lut6_I5_O) 0.124 5.174 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_30/O net (fo=4, routed) 0.529 5.703 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 SLICE_X12Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/I0 SLICE_X12Y76 LUT3 (Prop_lut3_I0_O) 0.124 5.827 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[6]_inst_i_1/O net (fo=2, routed) 3.517 9.344 ext_ram_data_IOBUF[6]_inst/I AE20 r ext_ram_data_IOBUF[6]_inst/OBUFT/I AE20 OBUFT (Prop_obuft_I_O) 3.562 12.906 r ext_ram_data_IOBUF[6]_inst/OBUFT/O net (fo=1, unset) 0.000 12.906 ext_ram_data[6] AE20 r ext_ram_data[6] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.906 ------------------------------------------------------------------- slack 0.416 Slack (MET) : 0.422ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.308ns (logic 5.033ns (32.879%) route 10.275ns (67.121%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O net (fo=2, routed) 3.465 9.315 ext_ram_data_IOBUF[31]_inst/I AC23 r ext_ram_data_IOBUF[31]_inst/OBUFT/I AC23 OBUFT (Prop_obuft_I_O) 3.585 12.900 r ext_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.900 ext_ram_data[31] AC23 r ext_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.900 ------------------------------------------------------------------- slack 0.422 Slack (MET) : 0.475ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.176ns (logic 6.904ns (45.493%) route 8.272ns (54.507%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.488 9.283 base_ram_data_IOBUF[1]_inst/T L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T L25 OBUFT (TriStatE_obuft_T_O) 3.564 12.847 r base_ram_data_IOBUF[1]_inst/OBUFT/O net (fo=1, unset) 0.000 12.847 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.847 ------------------------------------------------------------------- slack 0.475 Slack (MET) : 0.483ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.247ns (logic 4.979ns (32.656%) route 10.268ns (67.344%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.359 2.448 u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/ADDRA0 SLICE_X22Y86 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/RADR0 SLICE_X22Y86 RAMD32 (Prop_ramd32_RADR0_O) 0.124 2.572 r u_matmul_axi_slave/b1_c_reg_r2_0_15_30_35/RAMA_D1/O net (fo=1, routed) 0.875 3.447 u_matmul_axi_slave/ep_rd_c1[31] SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/I0 SLICE_X24Y84 LUT4 (Prop_lut4_I0_O) 0.124 3.571 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0/O net (fo=1, routed) 0.574 4.145 u_matmul_axi_slave/ram_reg_0_7_30_35_i_12__0_n_0 SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/I4 SLICE_X24Y83 LUT5 (Prop_lut5_I4_O) 0.124 4.269 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_10__0/O net (fo=1, routed) 0.562 4.831 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[31] SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/I5 SLICE_X27Y83 LUT6 (Prop_lut6_I5_O) 0.124 4.955 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_7__1/O net (fo=3, routed) 0.771 5.726 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[31] SLICE_X30Y85 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/I0 SLICE_X30Y85 LUT3 (Prop_lut3_I0_O) 0.124 5.850 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[31]_inst_i_1/O net (fo=2, routed) 3.458 9.308 base_ram_data_IOBUF[31]_inst/I M22 r base_ram_data_IOBUF[31]_inst/OBUFT/I M22 OBUFT (Prop_obuft_I_O) 3.531 12.839 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.839 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.839 ------------------------------------------------------------------- slack 0.483 Slack (MET) : 0.489ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[19] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.161ns (logic 6.897ns (45.492%) route 8.264ns (54.508%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.599 9.276 ext_ram_data_IOBUF[19]_inst/T AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T AC18 OBUFT (TriStatE_obuft_T_O) 3.557 12.833 r ext_ram_data_IOBUF[19]_inst/OBUFT/O net (fo=1, unset) 0.000 12.833 ext_ram_data[19] AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.833 ------------------------------------------------------------------- slack 0.489 Slack (MET) : 0.508ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[23] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.143ns (logic 6.882ns (45.449%) route 8.261ns (54.551%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.595 9.272 ext_ram_data_IOBUF[23]_inst/T AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T AA15 OBUFT (TriStatE_obuft_T_O) 3.542 12.815 r ext_ram_data_IOBUF[23]_inst/OBUFT/O net (fo=1, unset) 0.000 12.815 ext_ram_data[23] AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.815 ------------------------------------------------------------------- slack 0.508 Slack (MET) : 0.518ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.133ns (logic 6.891ns (45.538%) route 8.241ns (54.462%)) Logic Levels: 13 (CARRY4=6 LUT5=1 LUT6=5 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.371 7.266 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X0Y129 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 SLICE_X0Y129 LUT6 (Prop_lut6_I5_O) 0.124 7.390 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 1.863 9.253 base_ram_be_n_OBUF[3] K25 r base_ram_be_n_OBUF[3]_inst/I K25 OBUF (Prop_obuf_I_O) 3.551 12.804 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 12.804 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.804 ------------------------------------------------------------------- slack 0.518 Slack (MET) : 0.535ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.116ns (logic 6.893ns (45.603%) route 8.223ns (54.397%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.659 5.553 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X3Y74 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 SLICE_X3Y74 LUT3 (Prop_lut3_I2_O) 0.124 5.677 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.557 9.234 ext_ram_data_IOBUF[25]_inst/T AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.788 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.788 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.788 ------------------------------------------------------------------- slack 0.535 Slack (MET) : 0.557ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.173ns (logic 5.026ns (33.126%) route 10.147ns (66.874%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 0.971 1.949 u_snix_axil_cdma_mux_8ch/ep_rd_elem[1] SLICE_X21Y79 r u_snix_axil_cdma_mux_8ch/ram_reg_i_77/I3 SLICE_X21Y79 LUT6 (Prop_lut6_I3_O) 0.124 2.073 r u_snix_axil_cdma_mux_8ch/ram_reg_i_77/O net (fo=32, routed) 1.329 3.402 u_matmul_axi_slave/ram_reg_i_51_1 SLICE_X24Y84 r u_matmul_axi_slave/ram_reg_i_67/I3 SLICE_X24Y84 LUT4 (Prop_lut4_I3_O) 0.124 3.526 r u_matmul_axi_slave/ram_reg_i_67/O net (fo=1, routed) 0.500 4.026 u_matmul_axi_slave/ram_reg_i_67_n_0 SLICE_X25Y84 r u_matmul_axi_slave/ram_reg_i_49/I4 SLICE_X25Y84 LUT5 (Prop_lut5_I4_O) 0.124 4.150 r u_matmul_axi_slave/ram_reg_i_49/O net (fo=1, routed) 0.645 4.795 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[3] SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_33/I5 SLICE_X29Y80 LUT6 (Prop_lut6_I5_O) 0.124 4.919 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_33/O net (fo=3, routed) 0.413 5.332 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[3] SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[3]_inst_i_1/I0 SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.456 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[3]_inst_i_1/O net (fo=2, routed) 3.731 9.187 ext_ram_data_IOBUF[3]_inst/I AE22 r ext_ram_data_IOBUF[3]_inst/OBUFT/I AE22 OBUFT (Prop_obuft_I_O) 3.578 12.765 r ext_ram_data_IOBUF[3]_inst/OBUFT/O net (fo=1, unset) 0.000 12.765 ext_ram_data[3] AE22 r ext_ram_data[3] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.765 ------------------------------------------------------------------- slack 0.557 Slack (MET) : 0.561ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.169ns (logic 5.223ns (34.430%) route 9.946ns (65.570%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT6=4 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.303 2.393 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA0 SLICE_X22Y84 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/RADR0 SLICE_X22Y84 RAMD32 (Prop_ramd32_RADR0_O) 0.150 2.543 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/O net (fo=1, routed) 0.961 3.504 u_matmul_axi_slave/ep_rd_c0[0] SLICE_X24Y82 r u_matmul_axi_slave/ram_reg_i_73/I2 SLICE_X24Y82 LUT4 (Prop_lut4_I2_O) 0.328 3.832 r u_matmul_axi_slave/ram_reg_i_73/O net (fo=1, routed) 0.667 4.499 u_matmul_axi_slave/ram_reg_i_73_n_0 SLICE_X24Y82 r u_matmul_axi_slave/ram_reg_i_52/I0 SLICE_X24Y82 LUT6 (Prop_lut6_I0_O) 0.124 4.623 r u_matmul_axi_slave/ram_reg_i_52/O net (fo=1, routed) 0.414 5.036 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[0] SLICE_X26Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_36/I5 SLICE_X26Y82 LUT6 (Prop_lut6_I5_O) 0.124 5.160 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_36/O net (fo=3, routed) 0.309 5.470 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[0] SLICE_X27Y83 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/I0 SLICE_X27Y83 LUT3 (Prop_lut3_I0_O) 0.124 5.594 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O net (fo=2, routed) 3.623 9.217 base_ram_data_IOBUF[0]_inst/I L24 r base_ram_data_IOBUF[0]_inst/OBUFT/I L24 OBUFT (Prop_obuft_I_O) 3.545 12.761 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 12.761 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.761 ------------------------------------------------------------------- slack 0.561 Slack (MET) : 0.585ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.145ns (logic 5.222ns (34.482%) route 9.923ns (65.518%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.356 2.446 u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/ADDRA0 SLICE_X22Y85 r u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/RAMA/RADR0 SLICE_X22Y85 RAMD32 (Prop_ramd32_RADR0_O) 0.150 2.596 r u_matmul_axi_slave/b0_c_reg_r2_0_15_30_35/RAMA/O net (fo=1, routed) 0.805 3.401 u_matmul_axi_slave/ep_rd_c0[30] SLICE_X24Y83 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0/I2 SLICE_X24Y83 LUT4 (Prop_lut4_I2_O) 0.328 3.729 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0/O net (fo=1, routed) 0.428 4.157 u_matmul_axi_slave/ram_reg_0_7_30_35_i_13__0_n_0 SLICE_X26Y82 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/I4 SLICE_X26Y82 LUT5 (Prop_lut5_I4_O) 0.124 4.281 r u_matmul_axi_slave/ram_reg_0_7_30_35_i_11__0/O net (fo=1, routed) 0.462 4.742 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[30] SLICE_X28Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_8__1/I5 SLICE_X28Y82 LUT6 (Prop_lut6_I5_O) 0.124 4.866 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_30_35_i_8__1/O net (fo=3, routed) 0.482 5.348 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[30] SLICE_X28Y82 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/I0 SLICE_X28Y82 LUT3 (Prop_lut3_I0_O) 0.124 5.472 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[30]_inst_i_1/O net (fo=2, routed) 3.721 9.193 base_ram_data_IOBUF[30]_inst/I M24 r base_ram_data_IOBUF[30]_inst/OBUFT/I M24 OBUFT (Prop_obuft_I_O) 3.544 12.737 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 12.737 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.737 ------------------------------------------------------------------- slack 0.585 Slack (MET) : 0.587ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.143ns (logic 5.221ns (34.475%) route 9.923ns (65.525%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.757 0.966 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I3 SLICE_X23Y80 LUT6 (Prop_lut6_I3_O) 0.124 1.090 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=136, routed) 1.328 2.418 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/ADDRA0 SLICE_X22Y82 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA/RADR0 SLICE_X22Y82 RAMD32 (Prop_ramd32_RADR0_O) 0.150 2.568 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA/O net (fo=1, routed) 0.801 3.369 u_matmul_axi_slave/ep_rd_c0[24] SLICE_X19Y77 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_20__0/I2 SLICE_X19Y77 LUT4 (Prop_lut4_I2_O) 0.328 3.697 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_20__0/O net (fo=1, routed) 0.151 3.848 u_matmul_axi_slave/ram_reg_0_7_24_29_i_20__0_n_0 SLICE_X19Y77 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_14__0/I4 SLICE_X19Y77 LUT5 (Prop_lut5_I4_O) 0.124 3.972 r u_matmul_axi_slave/ram_reg_0_7_24_29_i_14__0/O net (fo=1, routed) 0.433 4.405 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[24] SLICE_X19Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_8__1/I5 SLICE_X19Y77 LUT6 (Prop_lut6_I5_O) 0.124 4.529 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_8__1/O net (fo=3, routed) 0.840 5.368 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[24] SLICE_X11Y71 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[24]_inst_i_1/I0 SLICE_X11Y71 LUT3 (Prop_lut3_I0_O) 0.124 5.492 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[24]_inst_i_1/O net (fo=2, routed) 3.701 9.193 ext_ram_data_IOBUF[24]_inst/I AD17 r ext_ram_data_IOBUF[24]_inst/OBUFT/I AD17 OBUFT (Prop_obuft_I_O) 3.543 12.736 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 12.736 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.736 ------------------------------------------------------------------- slack 0.587 Slack (MET) : 0.616ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.035ns (logic 6.884ns (45.785%) route 8.151ns (54.215%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.367 9.162 base_ram_data_IOBUF[21]_inst/T M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T M20 OBUFT (TriStatE_obuft_T_O) 3.544 12.706 r base_ram_data_IOBUF[21]_inst/OBUFT/O net (fo=1, unset) 0.000 12.706 base_ram_data[21] M20 r base_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.706 ------------------------------------------------------------------- slack 0.616 Slack (MET) : 0.622ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.029ns (logic 6.910ns (45.974%) route 8.120ns (54.026%)) Logic Levels: 13 (CARRY4=6 LUT3=1 LUT5=1 LUT6=4 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.947ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.329ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 2.013 -2.329 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y69 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y69 FDCE (Prop_fdce_C_Q) 0.456 -1.873 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[4]/Q net (fo=10, routed) 0.822 -1.051 u_axi_ram/u_axi_sram_sp/len[4] SLICE_X7Y70 f u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/I4 SLICE_X7Y70 LUT5 (Prop_lut5_I4_O) 0.124 -0.927 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9/O net (fo=49, routed) 0.729 -0.198 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[19]_inst_i_9_n_0 SLICE_X5Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/I0 SLICE_X5Y69 LUT6 (Prop_lut6_I0_O) 0.124 -0.074 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_15/O net (fo=1, routed) 0.574 0.500 u_axi_ram/u_axi_sram_sp/p_1_in[10] SLICE_X4Y69 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/DI[0] SLICE_X4Y69 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.526 1.026 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.026 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X4Y70 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI SLICE_X4Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.140 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.140 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X4Y71 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI SLICE_X4Y71 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.254 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] net (fo=1, routed) 0.000 1.254 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 SLICE_X4Y72 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI SLICE_X4Y72 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 1.368 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] net (fo=1, routed) 0.000 1.368 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 SLICE_X4Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI SLICE_X4Y73 CARRY4 (Prop_carry4_CI_O[1]) 0.334 1.702 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] net (fo=3, routed) 0.684 2.386 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.303 2.689 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O net (fo=1, routed) 0.000 2.689 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] SLICE_X3Y73 CARRY4 (Prop_carry4_S[1]_CO[2]) 0.570 3.259 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] net (fo=23, routed) 0.504 3.763 u_axi_ram/u_axi_sram_sp/req_addr_d10_in SLICE_X1Y74 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.313 4.076 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.694 4.770 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X1Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.894 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.777 5.672 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.796 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.335 9.131 base_ram_data_IOBUF[3]_inst/T M25 f base_ram_data_IOBUF[3]_inst/OBUFT/T M25 OBUFT (TriStatE_obuft_T_O) 3.570 12.701 r base_ram_data_IOBUF[3]_inst/OBUFT/O net (fo=1, unset) 0.000 12.701 base_ram_data[3] M25 r base_ram_data[3] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.701 ------------------------------------------------------------------- slack 0.622 Slack (MET) : 0.628ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.102ns (logic 5.207ns (34.482%) route 9.895ns (65.518%)) Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.868ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.408ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.934 -2.408 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X33Y88 FDRE r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.952 r u_snix_axil_cdma_mux_8ch/ep_word_addr_r_reg[6]/Q net (fo=4, routed) 1.044 -0.908 u_snix_axil_cdma_mux_8ch/ep_word_addr_r[6] SLICE_X25Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/I0 SLICE_X25Y79 LUT4 (Prop_lut4_I0_O) 0.124 -0.784 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_7/O net (fo=4, routed) 0.868 0.085 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[6] SLICE_X24Y79 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/I2 SLICE_X24Y79 LUT6 (Prop_lut6_I2_O) 0.124 0.209 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=135, routed) 0.645 0.854 u_snix_axil_cdma_mux_8ch/ep_rd_elem[2] SLICE_X23Y80 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I4 SLICE_X23Y80 LUT5 (Prop_lut5_I4_O) 0.124 0.978 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O net (fo=136, routed) 1.291 2.268 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA1 SLICE_X20Y79 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR1 SLICE_X20Y79 RAMD32 (Prop_ramd32_RADR1_O) 0.146 2.414 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O net (fo=1, routed) 0.661 3.075 u_matmul_axi_slave/ep_rd_c1[18] SLICE_X21Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/I0 SLICE_X21Y79 LUT4 (Prop_lut4_I0_O) 0.328 3.403 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0/O net (fo=1, routed) 0.671 4.074 u_matmul_axi_slave/ram_reg_0_7_18_23_i_20__0_n_0 SLICE_X25Y79 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/I4 SLICE_X25Y79 LUT5 (Prop_lut5_I4_O) 0.124 4.198 r u_matmul_axi_slave/ram_reg_0_7_18_23_i_14__0/O net (fo=1, routed) 0.578 4.776 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[18] SLICE_X29Y79 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/I5 SLICE_X29Y79 LUT6 (Prop_lut6_I5_O) 0.124 4.900 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__1/O net (fo=3, routed) 0.632 5.532 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] SLICE_X29Y80 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 SLICE_X29Y80 LUT3 (Prop_lut3_I0_O) 0.124 5.656 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O net (fo=2, routed) 3.505 9.161 base_ram_data_IOBUF[18]_inst/I P23 r base_ram_data_IOBUF[18]_inst/OBUFT/I P23 OBUFT (Prop_obuft_I_O) 3.533 12.694 r base_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 12.694 base_ram_data[18] P23 r base_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.102 13.622 output delay -0.300 13.322 ------------------------------------------------------------------- required time 13.322 arrival time -12.694 ------------------------------------------------------------------- slack 0.628 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.024ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X57Y90 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.927 -0.381 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.287 arrival time -0.263 ------------------------------------------------------------------- slack 0.024 Slack (MET) : 0.024ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X57Y90 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y90 FDCE (Prop_fdce_C_Q) 0.141 -0.469 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.206 -0.263 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.927 -0.381 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X56Y90 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK clock pessimism -0.216 -0.597 SLICE_X56Y90 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.287 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.287 arrival time -0.263 ------------------------------------------------------------------- slack 0.024 Slack (MET) : 0.067ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.435ns (logic 0.249ns (57.247%) route 0.186ns (42.753%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.559 -0.704 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X82Y130 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[19]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[19] SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_1/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_1_n_0 SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[3] SLICE_X85Y129 CARRY4 (Prop_carry4_S[3]_O[3]) 0.063 -0.269 r u_axi_uart_controller/uart0/regs/M_next_carry/O[3] net (fo=1, routed) 0.000 -0.269 u_axi_uart_controller/uart0/regs/M_next[3] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[3]/C clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[3] ------------------------------------------------------------------- required time 0.336 arrival time -0.269 ------------------------------------------------------------------- slack 0.067 Slack (MET) : 0.071ns (arrival time - required time) Source: u_matmul_axi_slave/req_1_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/busy_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.362ns (logic 0.186ns (51.410%) route 0.176ns (48.590%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.655 -0.607 u_matmul_axi_slave/sys_clk SLICE_X45Y99 FDRE r u_matmul_axi_slave/req_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.466 r u_matmul_axi_slave/req_1_reg/Q net (fo=19, routed) 0.176 -0.291 u_matmul_axi_slave/p_5_in[1] SLICE_X45Y100 r u_matmul_axi_slave/busy_i_1/I2 SLICE_X45Y100 LUT6 (Prop_lut6_I2_O) 0.045 -0.246 r u_matmul_axi_slave/busy_i_1/O net (fo=1, routed) 0.000 -0.246 u_matmul_axi_slave/busy_i_1_n_0 SLICE_X45Y100 FDRE r u_matmul_axi_slave/busy_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.860 -0.448 u_matmul_axi_slave/sys_clk SLICE_X45Y100 FDRE r u_matmul_axi_slave/busy_reg/C clock pessimism 0.040 -0.408 SLICE_X45Y100 FDRE (Hold_fdre_C_D) 0.091 -0.317 u_matmul_axi_slave/busy_reg ------------------------------------------------------------------- required time 0.317 arrival time -0.246 ------------------------------------------------------------------- slack 0.071 Slack (MET) : 0.073ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.393ns (logic 0.227ns (57.716%) route 0.166ns (42.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.453ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.650 -0.612 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/sys_clk SLICE_X63Y98 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y98 FDRE (Prop_fdre_C_Q) 0.128 -0.484 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[1]/Q net (fo=7, routed) 0.166 -0.318 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[1] SLICE_X62Y100 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/I1 SLICE_X62Y100 LUT6 (Prop_lut6_I1_O) 0.099 -0.219 r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining[2]_i_1/O net (fo=1, routed) 0.000 -0.219 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/p_1_in[2] SLICE_X62Y100 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.855 -0.453 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/sys_clk SLICE_X62Y100 FDRE r u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2]/C clock pessimism 0.040 -0.413 SLICE_X62Y100 FDRE (Hold_fdre_C_D) 0.121 -0.292 u_AxiCrossbar_2x8/axiIn_0_readOnly_decoder/errorSlave/remaining_reg[2] ------------------------------------------------------------------- required time 0.292 arrival time -0.219 ------------------------------------------------------------------- slack 0.073 Slack (MET) : 0.073ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.437ns (logic 0.189ns (43.230%) route 0.248ns (56.770%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.257ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.486ns Source Clock Delay (SCD): -0.703ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk SLICE_X87Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.562 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/Q net (fo=21, routed) 0.248 -0.314 u_Axi_CDC/wFifo/Q[27] SLICE_X82Y126 r u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/I2 SLICE_X82Y126 LUT4 (Prop_lut4_I2_O) 0.048 -0.266 r u_Axi_CDC/wFifo/reg_datai_32[19]_i_1/O net (fo=1, routed) 0.000 -0.266 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[19] SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.822 -0.486 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19]/C clock pessimism 0.040 -0.446 SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.107 -0.339 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[19] ------------------------------------------------------------------- required time 0.339 arrival time -0.266 ------------------------------------------------------------------- slack 0.073 Slack (MET) : 0.074ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/dl_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.442ns (logic 0.256ns (57.951%) route 0.186ns (42.049%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.704ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.559 -0.704 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X82Y130 FDRE r u_axi_uart_controller/uart0/regs/dl_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y130 FDRE (Prop_fdre_C_Q) 0.141 -0.563 r u_axi_uart_controller/uart0/regs/dl_reg[16]/Q net (fo=4, routed) 0.186 -0.377 u_axi_uart_controller/uart0/regs/dl[16] SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/I1 SLICE_X85Y129 LUT2 (Prop_lut2_I1_O) 0.045 -0.332 r u_axi_uart_controller/uart0/regs/M_next_carry_i_4/O net (fo=1, routed) 0.000 -0.332 u_axi_uart_controller/uart0/regs/M_next_carry_i_4_n_0 SLICE_X85Y129 r u_axi_uart_controller/uart0/regs/M_next_carry/S[0] SLICE_X85Y129 CARRY4 (Prop_carry4_S[0]_O[0]) 0.070 -0.262 r u_axi_uart_controller/uart0/regs/M_next_carry/O[0] net (fo=1, routed) 0.000 -0.262 u_axi_uart_controller/uart0/regs/M_next[0] SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X85Y129 FDRE r u_axi_uart_controller/uart0/regs/M_cnt_reg[0]/C clock pessimism 0.040 -0.441 SLICE_X85Y129 FDRE (Hold_fdre_C_D) 0.105 -0.336 u_axi_uart_controller/uart0/regs/M_cnt_reg[0] ------------------------------------------------------------------- required time 0.336 arrival time -0.262 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.074ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.425ns (logic 0.209ns (49.172%) route 0.216ns (50.828%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.259ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.486ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk SLICE_X84Y128 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y128 FDRE (Prop_fdre_C_Q) 0.164 -0.541 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/Q net (fo=23, routed) 0.216 -0.325 u_Axi_CDC/wFifo/Q[19] SLICE_X82Y126 r u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/I3 SLICE_X82Y126 LUT6 (Prop_lut6_I3_O) 0.045 -0.280 r u_Axi_CDC/wFifo/reg_datai_32[3]_i_1/O net (fo=1, routed) 0.000 -0.280 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[3] SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.822 -0.486 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk SLICE_X82Y126 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3]/C clock pessimism 0.040 -0.446 SLICE_X82Y126 FDRE (Hold_fdre_C_D) 0.092 -0.354 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[3] ------------------------------------------------------------------- required time 0.354 arrival time -0.280 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.080ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/ier_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.436ns (logic 0.209ns (47.943%) route 0.227ns (52.057%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.476ns Source Clock Delay (SCD): -0.700ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.563 -0.700 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X84Y133 FDRE r u_axi_uart_controller/uart0/regs/ier_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/ier_reg[3]/Q net (fo=3, routed) 0.227 -0.309 u_axi_uart_controller/uart0/regs/transmitter/Q[0] SLICE_X83Y135 r u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/I1 SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.264 r u_axi_uart_controller/uart0/regs/transmitter/ms_int_pnd_i_1/O net (fo=1, routed) 0.000 -0.264 u_axi_uart_controller/uart0/regs/transmitter_n_1 SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.832 -0.476 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ms_int_pnd_reg/C clock pessimism 0.040 -0.436 SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ms_int_pnd_reg ------------------------------------------------------------------- required time 0.344 arrival time -0.264 ------------------------------------------------------------------- slack 0.080 Slack (MET) : 0.081ns (arrival time - required time) Source: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.186ns (40.004%) route 0.279ns (59.996%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk SLICE_X85Y128 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y128 FDRE (Prop_fdre_C_Q) 0.141 -0.564 r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/Q net (fo=20, routed) 0.279 -0.285 u_Axi_CDC/wFifo/Q[14] SLICE_X80Y128 r u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/I4 SLICE_X80Y128 LUT5 (Prop_lut5_I4_O) 0.045 -0.240 r u_Axi_CDC/wFifo/reg_datai_32[14]_i_1/O net (fo=1, routed) 0.000 -0.240 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[23]_0[14] SLICE_X80Y128 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.827 -0.481 u_axi_uart_controller/AA_axi2apb_bridge_cpu/sys_clk SLICE_X80Y128 FDRE r u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14]/C clock pessimism 0.040 -0.441 SLICE_X80Y128 FDRE (Hold_fdre_C_D) 0.120 -0.321 u_axi_uart_controller/AA_axi2apb_bridge_cpu/reg_datai_32_reg[14] ------------------------------------------------------------------- required time 0.321 arrival time -0.240 ------------------------------------------------------------------- slack 0.081 Slack (MET) : 0.083ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/ier_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.439ns (logic 0.209ns (47.634%) route 0.230ns (52.366%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.476ns Source Clock Delay (SCD): -0.700ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.563 -0.700 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X84Y133 FDRE r u_axi_uart_controller/uart0/regs/ier_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.536 r u_axi_uart_controller/uart0/regs/ier_reg[0]/Q net (fo=6, routed) 0.230 -0.306 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/Q[0] SLICE_X83Y135 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/I1 SLICE_X83Y135 LUT6 (Prop_lut6_I1_O) 0.045 -0.261 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/ti_int_pnd_i_1/O net (fo=1, routed) 0.000 -0.261 u_axi_uart_controller/uart0/regs/receiver_n_1 SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.832 -0.476 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X83Y135 FDRE r u_axi_uart_controller/uart0/regs/ti_int_pnd_reg/C clock pessimism 0.040 -0.436 SLICE_X83Y135 FDRE (Hold_fdre_C_D) 0.092 -0.344 u_axi_uart_controller/uart0/regs/ti_int_pnd_reg ------------------------------------------------------------------- required time 0.344 arrival time -0.261 ------------------------------------------------------------------- slack 0.083 Slack (MET) : 0.084ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk SLICE_X43Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/Q[7] RAMB18_X2Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/ADDRARDADDR[11] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.962 -0.346 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/sys_clk RAMB18_X2Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK clock pessimism -0.213 -0.559 RAMB18_X2Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.292 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.324ns (logic 0.141ns (43.580%) route 0.183ns (56.420%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.346ns Source Clock Delay (SCD): -0.615ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk SLICE_X43Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/aw_addr_reg_reg[9]/Q net (fo=4, routed) 0.183 -0.292 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/Q[7] RAMB18_X2Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/ADDRARDADDR[11] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.962 -0.346 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/sys_clk RAMB18_X2Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK clock pessimism -0.213 -0.559 RAMB18_X2Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg ------------------------------------------------------------------- required time 0.376 arrival time -0.292 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.086ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.411ns (logic 0.141ns (34.332%) route 0.270ns (65.668%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk SLICE_X79Y131 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.561 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q net (fo=20, routed) 0.270 -0.291 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK SLICE_X80Y132 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK clock pessimism -0.210 -0.687 SLICE_X80Y132 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.377 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD ------------------------------------------------------------------- required time 0.377 arrival time -0.291 ------------------------------------------------------------------- slack 0.086 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X2Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X2Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X2Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X2Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y6 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y84 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y94 u_matmul_axi_slave/b0_c_reg_r1_0_15_42_47/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y82 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y92 u_matmul_axi_slave/b0_c_reg_r1_0_15_24_29/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y98 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y91 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: cpu_clk To Clock: cpu_clk Setup : 0 Failing Endpoints, Worst Slack 26.018ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.681ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 26.018ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 26.696 arrival time -0.678 ------------------------------------------------------------------- slack 26.018 Slack (MET) : 26.018ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 26.696 arrival time -0.678 ------------------------------------------------------------------- slack 26.018 Slack (MET) : 26.018ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 26.696 arrival time -0.678 ------------------------------------------------------------------- slack 26.018 Slack (MET) : 26.018ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X63Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X63Y101 FDCE (Recov_fdce_C_CLR) -0.405 26.696 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 26.696 arrival time -0.678 ------------------------------------------------------------------- slack 26.018 Slack (MET) : 26.062ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.361 26.740 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 26.740 arrival time -0.678 ------------------------------------------------------------------- slack 26.062 Slack (MET) : 26.062ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.361 26.740 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 26.740 arrival time -0.678 ------------------------------------------------------------------- slack 26.062 Slack (MET) : 26.104ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.782 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 26.782 arrival time -0.678 ------------------------------------------------------------------- slack 26.104 Slack (MET) : 26.104ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.356ns (logic 0.773ns (23.034%) route 2.583ns (76.966%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns = ( 27.721 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.418 0.678 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X62Y101 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.549 27.721 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.507 27.214 clock uncertainty -0.113 27.101 SLICE_X62Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.782 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 26.782 arrival time -0.678 ------------------------------------------------------------------- slack 26.104 Slack (MET) : 26.156ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.270ns (logic 0.642ns (19.635%) route 2.628ns (80.365%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.299ns = ( 27.701 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.986 0.592 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y127 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.529 27.701 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y127 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.435 27.266 clock uncertainty -0.113 27.153 SLICE_X89Y127 FDCE (Recov_fdce_C_CLR) -0.405 26.748 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 26.748 arrival time -0.592 ------------------------------------------------------------------- slack 26.156 Slack (MET) : 26.156ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.270ns (logic 0.642ns (19.635%) route 2.628ns (80.365%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.299ns = ( 27.701 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.986 0.592 u_Axi_CDC/wFifo/p_0_in SLICE_X89Y127 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.529 27.701 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y127 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C clock pessimism -0.435 27.266 clock uncertainty -0.113 27.153 SLICE_X89Y127 FDCE (Recov_fdce_C_CLR) -0.405 26.748 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] ------------------------------------------------------------------- required time 26.748 arrival time -0.592 ------------------------------------------------------------------- slack 26.156 Slack (MET) : 26.290ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.507 27.212 clock uncertainty -0.113 27.099 SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.361 26.738 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 26.738 arrival time -0.448 ------------------------------------------------------------------- slack 26.290 Slack (MET) : 26.332ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.507 27.212 clock uncertainty -0.113 27.099 SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.319 26.780 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 26.780 arrival time -0.448 ------------------------------------------------------------------- slack 26.332 Slack (MET) : 26.332ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.507 27.212 clock uncertainty -0.113 27.099 SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.319 26.780 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 26.780 arrival time -0.448 ------------------------------------------------------------------- slack 26.332 Slack (MET) : 26.332ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.126ns (logic 0.773ns (24.731%) route 2.353ns (75.269%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 27.719 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.187 0.448 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y103 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 27.719 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.507 27.212 clock uncertainty -0.113 27.099 SLICE_X64Y103 FDCE (Recov_fdce_C_CLR) -0.319 26.780 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 26.780 arrival time -0.448 ------------------------------------------------------------------- slack 26.332 Slack (MET) : 26.351ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C clock pessimism -0.507 27.213 clock uncertainty -0.113 27.100 SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.361 26.739 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 26.739 arrival time -0.388 ------------------------------------------------------------------- slack 26.351 Slack (MET) : 26.393ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C clock pessimism -0.507 27.213 clock uncertainty -0.113 27.100 SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.781 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 26.781 arrival time -0.388 ------------------------------------------------------------------- slack 26.393 Slack (MET) : 26.393ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C clock pessimism -0.507 27.213 clock uncertainty -0.113 27.100 SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.781 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 26.781 arrival time -0.388 ------------------------------------------------------------------- slack 26.393 Slack (MET) : 26.393ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 3.066ns (logic 0.773ns (25.212%) route 2.293ns (74.788%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 27.720 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.478 -2.200 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.165 -2.034 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.295 -1.739 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 2.128 0.388 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X64Y101 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.548 27.720 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y101 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C clock pessimism -0.507 27.213 clock uncertainty -0.113 27.100 SLICE_X64Y101 FDCE (Recov_fdce_C_CLR) -0.319 26.781 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 26.781 arrival time -0.388 ------------------------------------------------------------------- slack 26.393 Slack (MET) : 26.825ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 26.749 arrival time 0.077 ------------------------------------------------------------------- slack 26.825 Slack (MET) : 26.825ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.000ns (cpu_clk rise@30.000ns - cpu_clk rise@0.000ns) Data Path Delay: 2.601ns (logic 0.642ns (24.682%) route 1.959ns (75.318%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.298ns = ( 27.702 - 30.000 ) Source Clock Delay (SCD): -2.678ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.113ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.664 -2.678 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.518 -2.160 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.641 -1.518 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.124 -1.394 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.318 -0.077 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X86Y104 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.000 30.000 r K21 0.000 30.000 r clk (IN) net (fo=0) 0.000 30.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 31.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.081 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.172 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 27.702 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.435 27.267 clock uncertainty -0.113 27.154 SLICE_X86Y104 FDCE (Recov_fdce_C_CLR) -0.405 26.749 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 26.749 arrival time 0.077 ------------------------------------------------------------------- slack 26.825 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.681ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.596ns (logic 0.246ns (41.259%) route 0.350ns (58.741%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.007ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.293 -0.089 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X93Y122 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y122 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.209 -0.678 SLICE_X93Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.770 arrival time -0.089 ------------------------------------------------------------------- slack 0.681 Slack (MET) : 0.692ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.189 -0.656 SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.723 arrival time -0.031 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.692ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C clock pessimism -0.189 -0.656 SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.723 arrival time -0.031 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.692ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C clock pessimism -0.189 -0.656 SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.723 arrival time -0.031 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.692ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.654ns (logic 0.246ns (37.598%) route 0.408ns (62.402%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.467ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.351 -0.031 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X96Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/bFifo/cpu_clk SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.189 -0.656 SLICE_X96Y122 FDCE (Remov_fdce_C_CLR) -0.067 -0.723 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.723 arrival time -0.031 ------------------------------------------------------------------- slack 0.692 Slack (MET) : 0.750ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.007ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/bFifo/cpu_clk SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/C clock pessimism -0.209 -0.678 SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.770 arrival time -0.020 ------------------------------------------------------------------- slack 0.750 Slack (MET) : 0.750ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.007ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/bFifo/cpu_clk SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.209 -0.678 SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.770 arrival time -0.020 ------------------------------------------------------------------- slack 0.750 Slack (MET) : 0.750ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.665ns (logic 0.246ns (37.015%) route 0.419ns (62.985%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.007ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.361 -0.020 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X95Y122 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.839 -0.469 u_Axi_CDC/bFifo/cpu_clk SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.209 -0.678 SLICE_X95Y122 FDCE (Remov_fdce_C_CLR) -0.092 -0.770 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.770 arrival time -0.020 ------------------------------------------------------------------- slack 0.750 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.764ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.687ns (logic 0.209ns (30.411%) route 0.478ns (69.589%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.278 0.002 u_Axi_CDC/awFifo/p_0_in SLICE_X93Y113 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.847 -0.461 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.209 -0.670 SLICE_X93Y113 FDCE (Remov_fdce_C_CLR) -0.092 -0.762 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 0.762 arrival time 0.002 ------------------------------------------------------------------- slack 0.764 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.803ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.719ns (logic 0.246ns (34.214%) route 0.473ns (65.786%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.468ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.148 -0.537 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.057 -0.480 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X92Y115 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.098 -0.382 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__3/O net (fo=30, routed) 0.416 0.034 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X95Y121 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.840 -0.468 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.209 -0.677 SLICE_X95Y121 FDCE (Remov_fdce_C_CLR) -0.092 -0.769 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.769 arrival time 0.034 ------------------------------------------------------------------- slack 0.803 Slack (MET) : 0.808ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.759ns (logic 0.209ns (27.528%) route 0.550ns (72.472%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.018ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.685ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.578 -0.685 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y115 FDCE (Prop_fdce_C_Q) 0.164 -0.521 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.200 -0.321 pll_clk.u_rst_cpu/cpu_resetn SLICE_X92Y115 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X92Y115 LUT1 (Prop_lut1_I0_O) 0.045 -0.276 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.350 0.074 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X92Y111 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.209 -0.667 SLICE_X92Y111 FDCE (Remov_fdce_C_CLR) -0.067 -0.734 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.734 arrival time 0.074 ------------------------------------------------------------------- slack 0.808 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: mlkem_clk To Clock: mlkem_clk Setup : 0 Failing Endpoints, Worst Slack 3.826ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.658ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.826ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.817ns (logic 0.642ns (7.282%) route 8.175ns (92.718%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.108ns = ( 10.892 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.745 6.147 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X96Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.720 10.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X96Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22]/C clock pessimism -0.507 10.385 clock uncertainty -0.093 10.292 SLICE_X96Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.973 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[0][22] ------------------------------------------------------------------- required time 9.973 arrival time -6.147 ------------------------------------------------------------------- slack 3.826 Slack (MET) : 3.860ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.747ns (logic 0.642ns (7.340%) route 8.105ns (92.660%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.102ns = ( 10.898 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.675 6.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X104Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.726 10.898 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X104Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5]/C clock pessimism -0.507 10.391 clock uncertainty -0.093 10.298 SLICE_X104Y85 FDCE (Recov_fdce_C_CLR) -0.361 9.937 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][5] ------------------------------------------------------------------- required time 9.937 arrival time -6.077 ------------------------------------------------------------------- slack 3.860 Slack (MET) : 3.902ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.747ns (logic 0.642ns (7.340%) route 8.105ns (92.660%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.102ns = ( 10.898 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.675 6.077 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X104Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.726 10.898 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X104Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26]/C clock pessimism -0.507 10.391 clock uncertainty -0.093 10.298 SLICE_X104Y85 FDCE (Recov_fdce_C_CLR) -0.319 9.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][26] ------------------------------------------------------------------- required time 9.979 arrival time -6.077 ------------------------------------------------------------------- slack 3.902 Slack (MET) : 4.068ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][22] ------------------------------------------------------------------- required time 9.883 arrival time -5.815 ------------------------------------------------------------------- slack 4.068 Slack (MET) : 4.068ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][8] ------------------------------------------------------------------- required time 9.883 arrival time -5.815 ------------------------------------------------------------------- slack 4.068 Slack (MET) : 4.068ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X95Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X95Y99 FDCE (Recov_fdce_C_CLR) -0.405 9.883 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[5][9] ------------------------------------------------------------------- required time 9.883 arrival time -5.815 ------------------------------------------------------------------- slack 4.068 Slack (MET) : 4.115ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][12] ------------------------------------------------------------------- required time 9.884 arrival time -5.769 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][31] ------------------------------------------------------------------- required time 9.884 arrival time -5.769 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][3] ------------------------------------------------------------------- required time 9.884 arrival time -5.769 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][4] ------------------------------------------------------------------- required time 9.884 arrival time -5.769 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][5] ------------------------------------------------------------------- required time 9.884 arrival time -5.769 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.115ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X101Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X101Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X101Y86 FDCE (Recov_fdce_C_CLR) -0.405 9.884 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[4][6] ------------------------------------------------------------------- required time 9.884 arrival time -5.769 ------------------------------------------------------------------- slack 4.115 Slack (MET) : 4.154ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X94Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X94Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X94Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][6] ------------------------------------------------------------------- required time 9.969 arrival time -5.815 ------------------------------------------------------------------- slack 4.154 Slack (MET) : 4.154ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.485ns (logic 0.642ns (7.567%) route 7.843ns (92.433%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.112ns = ( 10.888 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.413 5.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X94Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 10.888 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X94Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8]/C clock pessimism -0.507 10.381 clock uncertainty -0.093 10.288 SLICE_X94Y99 FDCE (Recov_fdce_C_CLR) -0.319 9.969 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][8] ------------------------------------------------------------------- required time 9.969 arrival time -5.815 ------------------------------------------------------------------- slack 4.154 Slack (MET) : 4.159ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X100Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X100Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X100Y86 FDCE (Recov_fdce_C_CLR) -0.361 9.928 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][26] ------------------------------------------------------------------- required time 9.928 arrival time -5.769 ------------------------------------------------------------------- slack 4.159 Slack (MET) : 4.201ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.438ns (logic 0.642ns (7.608%) route 7.796ns (92.392%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.111ns = ( 10.889 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.366 5.769 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X100Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.717 10.889 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X100Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25]/C clock pessimism -0.507 10.382 clock uncertainty -0.093 10.289 SLICE_X100Y86 FDCE (Recov_fdce_C_CLR) -0.319 9.970 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][25] ------------------------------------------------------------------- required time 9.970 arrival time -5.769 ------------------------------------------------------------------- slack 4.201 Slack (MET) : 4.223ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24]/C clock pessimism -0.507 10.384 clock uncertainty -0.093 10.291 SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][24] ------------------------------------------------------------------- required time 9.886 arrival time -5.662 ------------------------------------------------------------------- slack 4.223 Slack (MET) : 4.223ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27]/C clock pessimism -0.507 10.384 clock uncertainty -0.093 10.291 SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][27] ------------------------------------------------------------------- required time 9.886 arrival time -5.662 ------------------------------------------------------------------- slack 4.223 Slack (MET) : 4.223ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4]/C clock pessimism -0.507 10.384 clock uncertainty -0.093 10.291 SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][4] ------------------------------------------------------------------- required time 9.886 arrival time -5.662 ------------------------------------------------------------------- slack 4.223 Slack (MET) : 4.223ns (required time - arrival time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 13.000ns (mlkem_clk rise@13.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 8.332ns (logic 0.642ns (7.705%) route 7.690ns (92.295%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.109ns = ( 10.891 - 13.000 ) Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.093ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.172ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 5.260 5.662 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_busy_m_reg_0 SLICE_X103Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 13.000 13.000 r K21 0.000 13.000 r clk (IN) net (fo=0) 0.000 13.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 14.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 15.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 7.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 9.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 9.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.719 10.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X103Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7]/C clock pessimism -0.507 10.384 clock uncertainty -0.093 10.291 SLICE_X103Y85 FDCE (Recov_fdce_C_CLR) -0.405 9.886 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[5][7] ------------------------------------------------------------------- required time 9.886 arrival time -5.662 ------------------------------------------------------------------- slack 4.223 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.658ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 0.923ns (logic 0.227ns (24.583%) route 0.696ns (75.417%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.332ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.414 0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X72Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C clock pessimism 0.040 -0.348 SLICE_X72Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.415 arrival time 0.243 ------------------------------------------------------------------- slack 0.658 Slack (MET) : 0.796ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism 0.040 -0.350 SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.417 arrival time 0.379 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.796ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism 0.040 -0.350 SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.417 arrival time 0.379 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.796ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism 0.040 -0.350 SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.417 arrival time 0.379 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.796ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.059ns (logic 0.227ns (21.435%) route 0.832ns (78.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.330ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.390ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.549 0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X74Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.918 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism 0.040 -0.350 SLICE_X74Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.417 arrival time 0.379 ------------------------------------------------------------------- slack 0.796 Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C clock pessimism 0.040 -0.351 SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.418 arrival time 0.389 ------------------------------------------------------------------- slack 0.807 Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C clock pessimism 0.040 -0.351 SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.418 arrival time 0.389 ------------------------------------------------------------------- slack 0.807 Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism 0.040 -0.351 SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.418 arrival time 0.389 ------------------------------------------------------------------- slack 0.807 Slack (MET) : 0.807ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X76Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism 0.040 -0.351 SLICE_X76Y97 FDCE (Remov_fdce_C_CLR) -0.067 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.418 arrival time 0.389 ------------------------------------------------------------------- slack 0.807 Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/C clock pessimism 0.040 -0.351 SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.443 arrival time 0.389 ------------------------------------------------------------------- slack 0.832 Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/C clock pessimism 0.040 -0.351 SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.443 arrival time 0.389 ------------------------------------------------------------------- slack 0.832 Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/C clock pessimism 0.040 -0.351 SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.443 arrival time 0.389 ------------------------------------------------------------------- slack 0.832 Slack (MET) : 0.832ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.227ns (21.233%) route 0.842ns (78.767%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.559 0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X77Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X77Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/C clock pessimism 0.040 -0.351 SLICE_X77Y97 FDCE (Remov_fdce_C_CLR) -0.092 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.443 arrival time 0.389 ------------------------------------------------------------------- slack 0.832 Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg/C clock pessimism 0.040 -0.345 SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.437 arrival time 0.447 ------------------------------------------------------------------- slack 0.884 Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0]/C clock pessimism 0.040 -0.345 SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.437 arrival time 0.447 ------------------------------------------------------------------- slack 0.884 Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1]/C clock pessimism 0.040 -0.345 SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.437 arrival time 0.447 ------------------------------------------------------------------- slack 0.884 Slack (MET) : 0.884ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.127ns (logic 0.227ns (20.136%) route 0.900ns (79.864%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.283 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X65Y102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X65Y102 LUT1 (Prop_lut1_I0_O) 0.099 -0.170 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.618 0.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X53Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X53Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2]/C clock pessimism 0.040 -0.345 SLICE_X53Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.437 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.437 arrival time 0.447 ------------------------------------------------------------------- slack 0.884 Slack (MET) : 0.906ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.080ns (logic 0.226ns (20.934%) route 0.854ns (79.066%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.683 0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X93Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15]/C clock pessimism 0.040 -0.347 SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[15] ------------------------------------------------------------------- required time 0.506 arrival time 0.400 ------------------------------------------------------------------- slack 0.906 Slack (MET) : 0.906ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.080ns (logic 0.226ns (20.934%) route 0.854ns (79.066%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.683 0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd_n_0 SLICE_X93Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X93Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53]/C clock pessimism 0.040 -0.347 SLICE_X93Y91 FDCE (Remov_fdce_C_CLR) -0.159 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[53] ------------------------------------------------------------------- required time 0.506 arrival time 0.400 ------------------------------------------------------------------- slack 0.906 Slack (MET) : 0.927ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR (removal check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk rise@0.000ns - mlkem_clk rise@0.000ns) Data Path Delay: 1.132ns (logic 0.226ns (19.963%) route 0.906ns (80.037%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X95Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y102 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q net (fo=6, routed) 0.171 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/srst_cnt_reg[2] SLICE_X95Y102 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/I2 SLICE_X95Y102 LUT5 (Prop_lut5_I2_O) 0.098 -0.283 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3/O net (fo=15647, routed) 0.735 0.452 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/valid_r_reg_5 SLICE_X100Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X100Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16]/C clock pessimism 0.040 -0.341 SLICE_X100Y98 FDCE (Remov_fdce_C_CLR) -0.134 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s4_reg[16] ------------------------------------------------------------------- required time 0.475 arrival time 0.452 ------------------------------------------------------------------- slack 0.927 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 6.335ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.573ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 6.335ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C clock pessimism -0.514 17.184 clock uncertainty -0.102 17.081 SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[1] ------------------------------------------------------------------- required time 16.558 arrival time -10.223 ------------------------------------------------------------------- slack 6.335 Slack (MET) : 6.335ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C clock pessimism -0.514 17.184 clock uncertainty -0.102 17.081 SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[2] ------------------------------------------------------------------- required time 16.558 arrival time -10.223 ------------------------------------------------------------------- slack 6.335 Slack (MET) : 6.335ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C clock pessimism -0.514 17.184 clock uncertainty -0.102 17.081 SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[5] ------------------------------------------------------------------- required time 16.558 arrival time -10.223 ------------------------------------------------------------------- slack 6.335 Slack (MET) : 6.335ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.797ns (logic 0.668ns (5.220%) route 12.129ns (94.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 9.016 10.223 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y165 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.526 17.697 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C clock pessimism -0.514 17.184 clock uncertainty -0.102 17.081 SLICE_X62Y165 FDCE (Recov_fdce_C_CLR) -0.523 16.558 u_confreg/u_digitaltube_controller/dpy1_reg_reg[6] ------------------------------------------------------------------- required time 16.558 arrival time -10.223 ------------------------------------------------------------------- slack 6.335 Slack (MET) : 6.478ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.242ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C clock pessimism -0.514 17.185 clock uncertainty -0.102 17.082 SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[0] ------------------------------------------------------------------- required time 16.559 arrival time -10.081 ------------------------------------------------------------------- slack 6.478 Slack (MET) : 6.478ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.242ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C clock pessimism -0.514 17.185 clock uncertainty -0.102 17.082 SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[3] ------------------------------------------------------------------- required time 16.559 arrival time -10.081 ------------------------------------------------------------------- slack 6.478 Slack (MET) : 6.478ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.242ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C clock pessimism -0.514 17.185 clock uncertainty -0.102 17.082 SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[4] ------------------------------------------------------------------- required time 16.559 arrival time -10.081 ------------------------------------------------------------------- slack 6.478 Slack (MET) : 6.478ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.655ns (logic 0.668ns (5.279%) route 11.987ns (94.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.242ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.302ns = ( 17.698 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.874 10.081 u_confreg/u_digitaltube_controller/p_0_in SLICE_X62Y164 FDCE f u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.527 17.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C clock pessimism -0.514 17.185 clock uncertainty -0.102 17.082 SLICE_X62Y164 FDCE (Recov_fdce_C_CLR) -0.523 16.559 u_confreg/u_digitaltube_controller/dpy1_reg_reg[7] ------------------------------------------------------------------- required time 16.559 arrival time -10.081 ------------------------------------------------------------------- slack 6.478 Slack (MET) : 6.900ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.246ns (logic 0.668ns (5.455%) route 11.578ns (94.545%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns = ( 17.719 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.466 9.673 u_confreg/u_digitaltube_controller/p_0_in SLICE_X63Y141 FDCE f u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.547 17.719 u_confreg/u_digitaltube_controller/sys_clk SLICE_X63Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C clock pessimism -0.435 17.284 clock uncertainty -0.102 17.182 SLICE_X63Y141 FDCE (Recov_fdce_C_CLR) -0.609 16.573 u_confreg/u_digitaltube_controller/dpy0_reg_reg[0] ------------------------------------------------------------------- required time 16.573 arrival time -9.673 ------------------------------------------------------------------- slack 6.900 Slack (MET) : 6.930ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.290ns (logic 0.668ns (5.435%) route 11.622ns (94.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.155ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.509 9.716 u_confreg/u_int_ctrl/p_0_in SLICE_X70Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.534 17.706 u_confreg/u_int_ctrl/sys_clk SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C clock pessimism -0.435 17.271 clock uncertainty -0.102 17.169 SLICE_X70Y133 FDCE (Recov_fdce_C_CLR) -0.523 16.646 u_confreg/u_int_ctrl/int_in_sync_d1_reg[1] ------------------------------------------------------------------- required time 16.646 arrival time -9.716 ------------------------------------------------------------------- slack 6.930 Slack (MET) : 6.930ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 12.290ns (logic 0.668ns (5.435%) route 11.622ns (94.565%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.155ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 8.509 9.716 u_confreg/u_int_ctrl/p_0_in SLICE_X70Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.534 17.706 u_confreg/u_int_ctrl/sys_clk SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[1]/C clock pessimism -0.435 17.271 clock uncertainty -0.102 17.169 SLICE_X70Y133 FDCE (Recov_fdce_C_CLR) -0.523 16.646 u_confreg/u_int_ctrl/int_in_sync_d2_reg[1] ------------------------------------------------------------------- required time 16.646 arrival time -9.716 ------------------------------------------------------------------- slack 6.930 Slack (MET) : 7.490ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.649ns (logic 0.668ns (5.734%) route 10.981ns (94.266%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.288ns = ( 17.712 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.868 9.076 u_confreg/u_int_ctrl/p_0_in SLICE_X65Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.540 17.712 u_confreg/u_int_ctrl/sys_clk SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C clock pessimism -0.435 17.277 clock uncertainty -0.102 17.175 SLICE_X65Y133 FDCE (Recov_fdce_C_CLR) -0.609 16.566 u_confreg/u_int_ctrl/int_in_sync_d1_reg[2] ------------------------------------------------------------------- required time 16.566 arrival time -9.076 ------------------------------------------------------------------- slack 7.490 Slack (MET) : 7.490ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d2_reg[2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.649ns (logic 0.668ns (5.734%) route 10.981ns (94.266%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.288ns = ( 17.712 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.868 9.076 u_confreg/u_int_ctrl/p_0_in SLICE_X65Y133 FDCE f u_confreg/u_int_ctrl/int_in_sync_d2_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.540 17.712 u_confreg/u_int_ctrl/sys_clk SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[2]/C clock pessimism -0.435 17.277 clock uncertainty -0.102 17.175 SLICE_X65Y133 FDCE (Recov_fdce_C_CLR) -0.609 16.566 u_confreg/u_int_ctrl/int_in_sync_d2_reg[2] ------------------------------------------------------------------- required time 16.566 arrival time -9.076 ------------------------------------------------------------------- slack 7.490 Slack (MET) : 7.742ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[23]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.496ns (logic 0.668ns (5.811%) route 10.828ns (94.189%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.715 8.922 u_confreg/u_int_ctrl/p_0_in SLICE_X46Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk SLICE_X46Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[23]/C clock pessimism -0.435 17.289 clock uncertainty -0.102 17.187 SLICE_X46Y140 FDCE (Recov_fdce_C_CLR) -0.523 16.664 u_confreg/u_int_ctrl/edge_int_state_reg[23] ------------------------------------------------------------------- required time 16.664 arrival time -8.922 ------------------------------------------------------------------- slack 7.742 Slack (MET) : 7.801ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[21]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.350ns (logic 0.668ns (5.885%) route 10.682ns (94.115%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.569 8.777 u_confreg/u_int_ctrl/p_0_in SLICE_X47Y139 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk SLICE_X47Y139 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[21]/C clock pessimism -0.435 17.289 clock uncertainty -0.102 17.187 SLICE_X47Y139 FDCE (Recov_fdce_C_CLR) -0.609 16.578 u_confreg/u_int_ctrl/edge_int_state_reg[21] ------------------------------------------------------------------- required time 16.578 arrival time -8.777 ------------------------------------------------------------------- slack 7.801 Slack (MET) : 7.821ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[29]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.414ns (logic 0.668ns (5.852%) route 10.746ns (94.148%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.634 8.841 u_confreg/u_int_ctrl/p_0_in SLICE_X56Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk SLICE_X56Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[29]/C clock pessimism -0.435 17.287 clock uncertainty -0.102 17.185 SLICE_X56Y140 FDCE (Recov_fdce_C_CLR) -0.523 16.662 u_confreg/u_int_ctrl/edge_int_state_reg[29] ------------------------------------------------------------------- required time 16.662 arrival time -8.841 ------------------------------------------------------------------- slack 7.821 Slack (MET) : 7.851ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[30]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.298ns (logic 0.668ns (5.912%) route 10.630ns (94.088%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns = ( 17.722 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.517 8.725 u_confreg/u_int_ctrl/p_0_in SLICE_X55Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 17.722 u_confreg/u_int_ctrl/sys_clk SLICE_X55Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[30]/C clock pessimism -0.435 17.287 clock uncertainty -0.102 17.185 SLICE_X55Y140 FDCE (Recov_fdce_C_CLR) -0.609 16.576 u_confreg/u_int_ctrl/edge_int_state_reg[30] ------------------------------------------------------------------- required time 16.576 arrival time -8.725 ------------------------------------------------------------------- slack 7.851 Slack (MET) : 7.963ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[20]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.189ns (logic 0.668ns (5.970%) route 10.521ns (94.030%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.276ns = ( 17.724 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.408 8.616 u_confreg/u_int_ctrl/p_0_in SLICE_X49Y140 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.552 17.724 u_confreg/u_int_ctrl/sys_clk SLICE_X49Y140 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[20]/C clock pessimism -0.435 17.289 clock uncertainty -0.102 17.187 SLICE_X49Y140 FDCE (Recov_fdce_C_CLR) -0.609 16.578 u_confreg/u_int_ctrl/edge_int_state_reg[20] ------------------------------------------------------------------- required time 16.578 arrival time -8.616 ------------------------------------------------------------------- slack 7.963 Slack (MET) : 8.025ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/edge_int_state_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.122ns (logic 0.668ns (6.006%) route 10.454ns (93.994%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.342 8.549 u_confreg/u_int_ctrl/p_0_in SLICE_X58Y137 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk SLICE_X58Y137 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[5]/C clock pessimism -0.435 17.285 clock uncertainty -0.102 17.183 SLICE_X58Y137 FDCE (Recov_fdce_C_CLR) -0.609 16.574 u_confreg/u_int_ctrl/edge_int_state_reg[5] ------------------------------------------------------------------- required time 16.574 arrival time -8.549 ------------------------------------------------------------------- slack 8.025 Slack (MET) : 8.025ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 11.122ns (logic 0.668ns (6.006%) route 10.454ns (93.994%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns = ( 17.720 - 20.000 ) Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): -0.435ns Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.342 8.549 u_confreg/u_int_ctrl/p_0_in SLICE_X58Y137 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 17.720 u_confreg/u_int_ctrl/sys_clk SLICE_X58Y137 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/C clock pessimism -0.435 17.285 clock uncertainty -0.102 17.183 SLICE_X58Y137 FDCE (Recov_fdce_C_CLR) -0.609 16.574 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] ------------------------------------------------------------------- required time 16.574 arrival time -8.549 ------------------------------------------------------------------- slack 8.025 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.573ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.019ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.213 -0.600 SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.667 arrival time -0.094 ------------------------------------------------------------------- slack 0.573 Slack (MET) : 0.573ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.019ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.213 -0.600 SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.667 arrival time -0.094 ------------------------------------------------------------------- slack 0.573 Slack (MET) : 0.573ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.525ns (logic 0.227ns (43.225%) route 0.298ns (56.775%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.019ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.159 -0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X66Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.213 -0.600 SLICE_X66Y93 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.667 arrival time -0.094 ------------------------------------------------------------------- slack 0.573 Slack (MET) : 0.837ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.812ns (logic 0.227ns (27.961%) route 0.585ns (72.039%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.445 0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X64Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X64Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.192 -0.577 SLICE_X64Y95 FDCE (Remov_fdce_C_CLR) -0.067 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.644 arrival time 0.192 ------------------------------------------------------------------- slack 0.837 Slack (MET) : 0.871ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.822ns (logic 0.227ns (27.605%) route 0.595ns (72.395%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.456 0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/C clock pessimism -0.192 -0.576 SLICE_X65Y99 FDCE (Remov_fdce_C_CLR) -0.092 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.668 arrival time 0.203 ------------------------------------------------------------------- slack 0.871 Slack (MET) : 0.871ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.822ns (logic 0.227ns (27.605%) route 0.595ns (72.395%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.643 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X67Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.491 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.139 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X67Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X67Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.456 0.203 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/C clock pessimism -0.192 -0.576 SLICE_X65Y99 FDCE (Remov_fdce_C_CLR) -0.092 -0.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.668 arrival time 0.203 ------------------------------------------------------------------- slack 0.871 Slack (MET) : 0.912ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.189 -0.666 SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.733 arrival time 0.179 ------------------------------------------------------------------- slack 0.912 Slack (MET) : 0.912ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.189 -0.666 SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.733 arrival time 0.179 ------------------------------------------------------------------- slack 0.912 Slack (MET) : 0.912ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.189 -0.666 SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.733 arrival time 0.179 ------------------------------------------------------------------- slack 0.912 Slack (MET) : 0.912ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X88Y126 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.189 -0.666 SLICE_X88Y126 FDCE (Remov_fdce_C_CLR) -0.067 -0.733 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.733 arrival time 0.179 ------------------------------------------------------------------- slack 0.912 Slack (MET) : 0.919ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.023ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.209 -0.670 SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.737 arrival time 0.182 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.919ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.023ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.209 -0.670 SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.737 arrival time 0.182 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.919ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.023ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.209 -0.670 SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.737 arrival time 0.182 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.919ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.875ns (logic 0.246ns (28.106%) route 0.629ns (71.894%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.023ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.343 0.182 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X92Y113 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.209 -0.670 SLICE_X92Y113 FDCE (Remov_fdce_C_CLR) -0.067 -0.737 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.737 arrival time 0.182 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 Slack (MET) : 0.937ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.872ns (logic 0.246ns (28.199%) route 0.626ns (71.801%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.477ns Source Clock Delay (SCD): -0.693ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.570 -0.693 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X92Y123 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y123 FDCE (Prop_fdce_C_Q) 0.148 -0.545 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.259 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X92Y123 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X92Y123 LUT1 (Prop_lut1_I0_O) 0.098 -0.161 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=43, routed) 0.340 0.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X89Y126 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.831 -0.477 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.189 -0.666 SLICE_X89Y126 FDCE (Remov_fdce_C_CLR) -0.092 -0.758 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.758 arrival time 0.179 ------------------------------------------------------------------- slack 0.937 -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: cpu_clk Max Delay 59 Endpoints Min Delay 59 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_cpu/delay_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.617 7.824 pll_clk.u_rst_cpu/p_0_in_0 SLICE_X92Y115 FDCE f pll_clk.u_rst_cpu/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.544 -2.284 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[0]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_cpu/delay_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.617 7.824 pll_clk.u_rst_cpu/p_0_in_0 SLICE_X92Y115 FDCE f pll_clk.u_rst_cpu/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.544 -2.284 pll_clk.u_rst_cpu/cpu_clk SLICE_X92Y115 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.617 7.824 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 SLICE_X92Y115 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.544 -2.284 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 10.398ns (logic 0.668ns (6.425%) route 9.730ns (93.575%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.617 7.824 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 SLICE_X92Y115 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.544 -2.284 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X92Y115 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.208ns (logic 1.344ns (25.806%) route 3.864ns (74.194%)) Logic Levels: 0 Clock Path Skew: 0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.053 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 3.864 2.811 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.118ns (logic 1.336ns (26.105%) route 3.782ns (73.895%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.062 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 3.782 2.720 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.096ns (logic 1.317ns (25.844%) route 3.779ns (74.156%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.080 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 3.779 2.699 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.064ns (logic 1.314ns (25.947%) route 3.750ns (74.053%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.084 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 3.750 2.667 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.040ns (logic 1.309ns (25.973%) route 3.731ns (74.027%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.089 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 3.731 2.642 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.035ns (logic 1.314ns (26.100%) route 3.721ns (73.900%)) Logic Levels: 0 Clock Path Skew: 0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.083 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 3.721 2.638 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.971ns (logic 1.344ns (27.035%) route 3.627ns (72.965%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.054 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 3.627 2.574 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.947ns (logic 1.344ns (27.169%) route 3.603ns (72.831%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 1.344 -1.054 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 3.603 2.549 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.937ns (logic 1.317ns (26.677%) route 3.620ns (73.323%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.081 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 3.620 2.539 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.925ns (logic 1.309ns (26.579%) route 3.616ns (73.421%)) Logic Levels: 0 Clock Path Skew: 0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.089 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 3.616 2.527 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.852ns (logic 1.317ns (27.146%) route 3.535ns (72.854%)) Logic Levels: 0 Clock Path Skew: 0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X22Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y91 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.081 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 3.535 2.454 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] SLICE_X93Y111 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y111 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.709ns (logic 1.336ns (28.372%) route 3.373ns (71.628%)) Logic Levels: 0 Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X40Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y92 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.076 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 3.373 2.297 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.686ns (logic 1.314ns (28.042%) route 3.372ns (71.958%)) Logic Levels: 0 Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.412ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.930 -2.412 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X40Y91 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y91 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.098 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 3.372 2.274 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X93Y123 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.616ns (logic 1.336ns (28.941%) route 3.280ns (71.059%)) Logic Levels: 0 Clock Path Skew: 0.104ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 1.336 -1.061 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 3.280 2.220 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.535 -2.293 u_Axi_CDC/rFifo/cpu_clk SLICE_X90Y121 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.560ns (logic 1.343ns (29.450%) route 3.217ns (70.550%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns Source Clock Delay (SCD): -2.398ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.944 -2.398 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X22Y92 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y92 RAMD32 (Prop_ramd32_CLK_O) 1.343 -1.055 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 3.217 2.163 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 4.469ns (logic 1.309ns (29.293%) route 3.160ns (70.707%)) Logic Levels: 0 Clock Path Skew: 0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns Source Clock Delay (SCD): -2.397ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.945 -2.397 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X22Y95 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y95 RAMD32 (Prop_ramd32_CLK_O) 1.309 -1.088 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 3.160 2.072 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/rFifo/cpu_clk SLICE_X92Y122 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.669ns (logic 0.518ns (77.393%) route 0.151ns (22.607%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.396ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.301ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.527 -2.301 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X74Y119 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y119 FDRE (Prop_fdre_C_Q) 0.418 -1.883 r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/Q net (fo=3, routed) 0.151 -1.732 u_snix_axil_cdma_mux_8ch/ch_done_reg[2]_0 SLICE_X75Y119 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/I1 SLICE_X75Y119 LUT5 (Prop_lut5_I1_O) 0.100 -1.632 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O net (fo=1, routed) 0.000 -1.632 u_cpu/u_csr/interrupt[1] SLICE_X75Y119 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.645 -2.697 u_cpu/u_csr/cpu_clk SLICE_X75Y119 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.682ns (logic 0.418ns (61.288%) route 0.264ns (38.712%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.694ns Source Clock Delay (SCD): -2.300ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.418 -1.882 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.264 -1.618 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.672ns (logic 0.418ns (62.183%) route 0.254ns (37.817%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.685ns Source Clock Delay (SCD): -2.290ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.538 -2.290 u_Axi_CDC/bFifo/sys_clk SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.418 -1.872 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.254 -1.618 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.657 -2.685 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.776ns (logic 0.385ns (49.618%) route 0.391ns (50.382%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.694ns Source Clock Delay (SCD): -2.300ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.385 -1.915 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.391 -1.524 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X91Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.803ns (logic 0.418ns (52.045%) route 0.385ns (47.955%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.280ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 -2.280 u_Axi_CDC/awFifo/sys_clk SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y110 FDCE (Prop_fdce_C_Q) 0.418 -1.862 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.385 -1.477 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[0] SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.837ns (logic 0.418ns (49.921%) route 0.419ns (50.079%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.694ns Source Clock Delay (SCD): -2.300ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.418 -1.882 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.419 -1.463 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.838ns (logic 0.418ns (49.893%) route 0.420ns (50.107%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.280ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 -2.280 u_Axi_CDC/awFifo/sys_clk SLICE_X92Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y110 FDCE (Prop_fdce_C_Q) 0.418 -1.862 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.420 -1.442 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.857ns (logic 0.367ns (42.833%) route 0.490ns (57.167%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.280ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.548 -2.280 u_Axi_CDC/awFifo/sys_clk SLICE_X93Y110 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y110 FDCE (Prop_fdce_C_Q) 0.367 -1.913 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.490 -1.423 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X92Y111 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.968ns (logic 0.418ns (43.176%) route 0.550ns (56.824%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.694ns Source Clock Delay (SCD): -2.300ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.528 -2.300 u_Axi_CDC/wFifo/sys_clk SLICE_X88Y126 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y126 FDCE (Prop_fdce_C_Q) 0.418 -1.882 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.550 -1.332 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.648 -2.694 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X90Y126 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.007ns (logic 0.385ns (38.250%) route 0.622ns (61.750%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.685ns Source Clock Delay (SCD): -2.290ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.538 -2.290 u_Axi_CDC/bFifo/sys_clk SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.385 -1.905 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.622 -1.283 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.657 -2.685 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.033ns (logic 0.418ns (40.449%) route 0.615ns (59.551%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.685ns Source Clock Delay (SCD): -2.290ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.538 -2.290 u_Axi_CDC/bFifo/sys_clk SLICE_X94Y121 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y121 FDCE (Prop_fdce_C_Q) 0.418 -1.872 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.615 -1.256 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.657 -2.685 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X95Y121 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.901ns (logic 0.337ns (37.384%) route 0.564ns (62.616%)) Logic Levels: 0 Clock Path Skew: -0.556ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.692ns Source Clock Delay (SCD): -2.135ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.693 -2.135 u_Axi_CDC/arFifo/sys_clk SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.337 -1.798 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.564 -1.234 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.650 -2.692 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_confreg/int_out_or_q2_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.082ns (logic 0.367ns (33.922%) route 0.715ns (66.078%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.691ns Source Clock Delay (SCD): -2.302ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.526 -2.302 u_confreg/sys_clk SLICE_X78Y141 FDRE r u_confreg/int_out_or_q2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X78Y141 FDRE (Prop_fdre_C_Q) 0.367 -1.935 r u_confreg/int_out_or_q2_reg/Q net (fo=1, routed) 0.715 -1.220 u_cpu/u_csr/interrupt[0] SLICE_X84Y149 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.651 -2.691 u_cpu/u_csr/cpu_clk SLICE_X84Y149 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.927ns (logic 0.367ns (39.581%) route 0.560ns (60.419%)) Logic Levels: 0 Clock Path Skew: -0.556ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.692ns Source Clock Delay (SCD): -2.135ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.693 -2.135 u_Axi_CDC/arFifo/sys_clk SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.367 -1.768 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.560 -1.208 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.650 -2.692 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.999ns (logic 0.418ns (41.855%) route 0.581ns (58.145%)) Logic Levels: 0 Clock Path Skew: -0.558ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.418 -1.697 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=2, routed) 0.581 -1.117 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.010ns (logic 0.418ns (41.371%) route 0.592ns (58.629%)) Logic Levels: 0 Clock Path Skew: -0.558ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.418 -1.697 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.592 -1.105 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.033ns (logic 0.367ns (35.528%) route 0.666ns (64.472%)) Logic Levels: 0 Clock Path Skew: -0.556ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.692ns Source Clock Delay (SCD): -2.135ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.693 -2.135 u_Axi_CDC/arFifo/sys_clk SLICE_X78Y99 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y99 FDCE (Prop_fdce_C_Q) 0.367 -1.768 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.666 -1.102 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.650 -2.692 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X86Y104 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.099ns (logic 0.385ns (35.032%) route 0.714ns (64.968%)) Logic Levels: 0 Clock Path Skew: -0.558ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk SLICE_X62Y95 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y95 FDCE (Prop_fdce_C_Q) 0.385 -1.730 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=4, routed) 0.714 -1.016 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X63Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.234ns (logic 0.418ns (33.873%) route 0.816ns (66.127%)) Logic Levels: 0 Clock Path Skew: -0.558ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.674ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.713 -2.115 u_Axi_CDC/rFifo/sys_clk SLICE_X62Y94 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y94 FDCE (Prop_fdce_C_Q) 0.418 -1.697 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.816 -0.881 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.668 -2.674 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X62Y101 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.609ns (logic 0.385ns (23.934%) route 1.224ns (76.066%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.670ns Source Clock Delay (SCD): -2.276ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.552 -2.276 u_fft_mlkem_axi_slave/sys_clk SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y110 FDCE (Prop_fdce_C_Q) 0.385 -1.891 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/Q net (fo=1, routed) 1.224 -0.667 u_cpu/u_csr/interrupt[3] SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.672 -2.670 u_cpu/u_csr/cpu_clk SLICE_X96Y139 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: mlkem_clk Max Delay 112 Endpoints Min Delay 112 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 10.980ns (logic 0.668ns (6.084%) route 10.312ns (93.916%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.301ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.273ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 7.199 8.406 pll_clk.u_rst_mlkem/p_0_in SLICE_X96Y101 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.555 -2.273 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X96Y101 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 10.561ns (logic 0.668ns (6.325%) route 9.893ns (93.675%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 6.780 7.987 pll_clk.u_rst_mlkem/p_0_in SLICE_X92Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.551 -2.277 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 6.643ns (logic 0.668ns (10.055%) route 5.975ns (89.945%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.294ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 2.863 4.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.548 -2.280 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 6.643ns (logic 0.668ns (10.055%) route 5.975ns (89.945%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.294ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.280ns Source Clock Delay (SCD): -2.574ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.768 -2.574 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0] SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=4121, routed) 2.863 4.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.548 -2.280 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X65Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.143ns (logic 0.612ns (53.534%) route 0.531ns (46.466%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/O net (fo=1, routed) 0.531 0.756 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[36] SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.059ns (logic 0.612ns (57.810%) route 0.447ns (42.190%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X44Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.447 0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.002ns (logic 0.595ns (59.409%) route 0.407ns (40.591%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 0.407 0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7] SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.994ns (logic 0.612ns (61.564%) route 0.382ns (38.436%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.617ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X68Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y97 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O net (fo=1, routed) 0.382 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48] SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.982ns (logic 0.612ns (62.344%) route 0.370ns (37.656%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.384ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 0.370 0.597 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0] SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.966ns (logic 0.612ns (63.335%) route 0.354ns (36.665%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.611ns Source Clock Delay (SCD): -0.380ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/WCLK SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.232 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O net (fo=1, routed) 0.354 0.586 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36] SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.963ns (logic 0.491ns (50.975%) route 0.472ns (49.025%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.614ns Source Clock Delay (SCD): -0.384ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.107 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O net (fo=1, routed) 0.472 0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2] SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.957ns (logic 0.595ns (62.185%) route 0.362ns (37.815%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.617ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O net (fo=1, routed) 0.362 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13] SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.957ns (logic 0.482ns (50.382%) route 0.475ns (49.618%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.617ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O net (fo=1, routed) 0.475 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15] SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.954ns (logic 0.482ns (50.537%) route 0.472ns (49.463%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X52Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.095 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/O net (fo=1, routed) 0.472 0.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[9] SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.940ns (logic 0.595ns (63.287%) route 0.345ns (36.713%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X44Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.345 0.551 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1] SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.935ns (logic 0.612ns (65.444%) route 0.323ns (34.556%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O net (fo=1, routed) 0.323 0.550 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12] SLICE_X67Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X67Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.927ns (logic 0.595ns (64.162%) route 0.332ns (35.838%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.613ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X44Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.332 0.539 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.925ns (logic 0.595ns (64.303%) route 0.330ns (35.697%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.615ns Source Clock Delay (SCD): -0.391ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X46Y79 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.204 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.330 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[7] SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.919ns (logic 0.595ns (64.745%) route 0.324ns (35.255%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.385ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X64Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 0.324 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[7] SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.908ns (logic 0.612ns (67.424%) route 0.296ns (32.576%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.616ns Source Clock Delay (SCD): -0.387ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X70Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y98 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O net (fo=1, routed) 0.296 0.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42] SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/C Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.629ns (logic 0.367ns (58.312%) route 0.262ns (41.688%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.112ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X54Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y91 FDCE (Prop_fdce_C_Q) 0.367 -1.745 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.262 -1.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[2] SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.660ns (logic 0.337ns (51.055%) route 0.323ns (48.945%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.504ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X51Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y83 FDCE (Prop_fdce_C_Q) 0.337 -1.780 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.323 -1.457 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.672ns (logic 0.385ns (57.253%) route 0.287ns (42.747%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.511ns Source Clock Delay (SCD): -2.125ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.703 -2.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X74Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y96 FDCE (Prop_fdce_C_Q) 0.385 -1.740 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.287 -1.453 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.831 -2.511 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.673ns (logic 0.418ns (62.094%) route 0.255ns (37.906%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.506ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X68Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X68Y92 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.255 -1.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[3] SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.672ns (logic 0.367ns (54.616%) route 0.305ns (45.384%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.504ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X51Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y83 FDCE (Prop_fdce_C_Q) 0.367 -1.750 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.305 -1.445 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[1] SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.680ns (logic 0.385ns (56.580%) route 0.295ns (43.420%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.385 -1.735 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=4, routed) 0.295 -1.440 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[3] SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.722ns (logic 0.418ns (57.896%) route 0.304ns (42.104%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.304 -1.398 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[0] SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.760ns (logic 0.385ns (50.673%) route 0.375ns (49.327%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.506ns Source Clock Delay (SCD): -2.119ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y93 FDCE (Prop_fdce_C_Q) 0.385 -1.734 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.375 -1.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[2] SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.756ns (logic 0.367ns (48.571%) route 0.389ns (51.429%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.500ns Source Clock Delay (SCD): -2.112ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X54Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y91 FDCE (Prop_fdce_C_Q) 0.367 -1.745 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.389 -1.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[1] SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.842 -2.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X54Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.784ns (logic 0.418ns (53.295%) route 0.366ns (46.705%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.505ns Source Clock Delay (SCD): -2.119ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y93 FDCE (Prop_fdce_C_Q) 0.418 -1.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.366 -1.335 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[1] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.837 -2.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.788ns (logic 0.367ns (46.589%) route 0.421ns (53.411%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.504ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X51Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y83 FDCE (Prop_fdce_C_Q) 0.367 -1.750 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.421 -1.330 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[0] SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X50Y83 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.801ns (logic 0.418ns (52.179%) route 0.383ns (47.821%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.511ns Source Clock Delay (SCD): -2.125ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.703 -2.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X74Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y96 FDCE (Prop_fdce_C_Q) 0.418 -1.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.383 -1.324 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[1] SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.831 -2.511 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X74Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.794ns (logic 0.367ns (46.198%) route 0.427ns (53.802%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.112ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X54Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y91 FDCE (Prop_fdce_C_Q) 0.367 -1.745 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.427 -1.318 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[0] SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X59Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.924ns (logic 0.418ns (45.244%) route 0.506ns (54.756%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=2, routed) 0.506 -1.196 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[2] SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.948ns (logic 0.418ns (44.102%) route 0.530ns (55.898%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.513ns Source Clock Delay (SCD): -2.125ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.703 -2.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X74Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y96 FDCE (Prop_fdce_C_Q) 0.418 -1.707 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.530 -1.177 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[0] SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.829 -2.513 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.961ns (logic 0.418ns (43.489%) route 0.543ns (56.511%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk SLICE_X48Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y79 FDCE (Prop_fdce_C_Q) 0.418 -1.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.543 -1.159 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[1] SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X48Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.504ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 1.084 -1.033 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 0.162 -0.871 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[30] SLICE_X49Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.838 -2.504 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y82 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.314ns (logic 1.062ns (80.806%) route 0.252ns (19.194%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.119ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X46Y81 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y81 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.057 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 0.252 -0.805 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[21] SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.326ns (logic 0.418ns (31.525%) route 0.908ns (68.475%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.506ns Source Clock Delay (SCD): -2.119ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.709 -2.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X66Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y93 FDCE (Prop_fdce_C_Q) 0.418 -1.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.908 -0.793 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[0] SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.836 -2.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X68Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.332ns (logic 1.062ns (79.740%) route 0.270ns (20.260%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.707 -2.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X70Y97 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.059 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/O net (fo=1, routed) 0.270 -0.789 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[39] SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: cpu_clk To Clock: sys_clk Max Delay 162 Endpoints Min Delay 162 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.425ns (logic 0.485ns (34.039%) route 0.940ns (65.961%)) Logic Levels: 0 Clock Path Skew: -0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.674ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.018 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/O net (fo=1, routed) 0.940 0.958 u_Axi_CDC/awFifo/_zz_ram_port10[22] SLICE_X52Y101 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.589 -0.674 u_Axi_CDC/awFifo/sys_clk SLICE_X52Y101 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.308ns (logic 0.482ns (36.863%) route 0.826ns (63.137%)) Logic Levels: 0 Clock Path Skew: -0.204ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.681ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.005 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/O net (fo=1, routed) 0.826 0.830 u_Axi_CDC/arFifo/_zz_ram_port10__1[9] SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.582 -0.681 u_Axi_CDC/arFifo/sys_clk SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.238ns (logic 0.485ns (39.176%) route 0.753ns (60.824%)) Logic Levels: 0 Clock Path Skew: -0.204ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.681ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.008 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/O net (fo=1, routed) 0.753 0.761 u_Axi_CDC/arFifo/_zz_ram_port10__1[10] SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.582 -0.681 u_Axi_CDC/arFifo/sys_clk SLICE_X61Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.212ns (logic 0.485ns (40.001%) route 0.727ns (59.999%)) Logic Levels: 0 Clock Path Skew: -0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.608ns Source Clock Delay (SCD): -0.458ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X70Y105 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y105 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.027 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/O net (fo=1, routed) 0.727 0.754 u_Axi_CDC/arFifo/_zz_ram_port10__1[22] SLICE_X47Y95 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.654 -0.608 u_Axi_CDC/arFifo/sys_clk SLICE_X47Y95 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.193ns (logic 0.612ns (51.321%) route 0.581ns (48.679%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.702ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.834 -0.474 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X88Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y128 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.138 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 0.581 0.718 u_Axi_CDC/wFifo/_zz_ram_port10__0[18] SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.185ns (logic 0.612ns (51.630%) route 0.573ns (48.370%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.702ns Source Clock Delay (SCD): -0.475ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.833 -0.475 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/WCLK SLICE_X90Y125 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y125 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.137 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/O net (fo=1, routed) 0.573 0.710 u_Axi_CDC/wFifo/_zz_ram_port10__0[36] SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.173ns (logic 0.612ns (52.170%) route 0.561ns (47.830%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.700ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.145 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/O net (fo=1, routed) 0.561 0.706 u_Axi_CDC/awFifo/_zz_ram_port10[18] SLICE_X82Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.563 -0.700 u_Axi_CDC/awFifo/sys_clk SLICE_X82Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.116ns (logic 0.482ns (43.203%) route 0.634ns (56.797%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.695ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X88Y114 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y114 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.015 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/O net (fo=1, routed) 0.634 0.648 u_Axi_CDC/awFifo/_zz_ram_port10[21] SLICE_X81Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.568 -0.695 u_Axi_CDC/awFifo/sys_clk SLICE_X81Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.100ns (logic 0.612ns (55.644%) route 0.488ns (44.356%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.698ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.145 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/O net (fo=1, routed) 0.488 0.633 u_Axi_CDC/awFifo/_zz_ram_port10[6] SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.080ns (logic 0.612ns (56.690%) route 0.468ns (43.310%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.698ns Source Clock Delay (SCD): -0.465ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.843 -0.465 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X90Y115 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y115 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.147 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 0.468 0.614 u_Axi_CDC/awFifo/_zz_ram_port10[0] SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk SLICE_X84Y112 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.075ns (logic 0.485ns (45.122%) route 0.590ns (54.878%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.702ns Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X90Y128 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y128 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.014 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.590 0.604 u_Axi_CDC/wFifo/_zz_ram_port10__0[16] SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.561 -0.702 u_Axi_CDC/wFifo/sys_clk SLICE_X81Y118 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.070ns (logic 0.612ns (57.190%) route 0.458ns (42.810%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.696ns Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X84Y109 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y109 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.141 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/O net (fo=1, routed) 0.458 0.599 u_Axi_CDC/arFifo/_zz_ram_port10__1[24] SLICE_X80Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.567 -0.696 u_Axi_CDC/arFifo/sys_clk SLICE_X80Y108 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.061ns (logic 0.491ns (46.270%) route 0.570ns (53.730%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.698ns Source Clock Delay (SCD): -0.467ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.841 -0.467 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.024 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/O net (fo=1, routed) 0.570 0.594 u_Axi_CDC/awFifo/_zz_ram_port10[8] SLICE_X82Y111 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.565 -0.698 u_Axi_CDC/awFifo/sys_clk SLICE_X82Y111 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.048ns (logic 0.595ns (56.753%) route 0.453ns (43.247%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.699ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.118 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 0.453 0.571 u_Axi_CDC/arFifo/_zz_ram_port10__1[7] SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/arFifo/sys_clk SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.024ns (logic 0.612ns (59.777%) route 0.412ns (40.223%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.680ns Source Clock Delay (SCD): -0.455ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.853 -0.455 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X64Y106 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y106 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.157 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/O net (fo=1, routed) 0.412 0.569 u_Axi_CDC/awFifo/_zz_ram_port10[42] SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.583 -0.680 u_Axi_CDC/awFifo/sys_clk SLICE_X63Y106 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.025ns (logic 0.595ns (58.034%) route 0.430ns (41.966%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.703ns Source Clock Delay (SCD): -0.472ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.836 -0.472 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X88Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y130 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.123 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.430 0.553 u_Axi_CDC/wFifo/_zz_ram_port10__0[1] SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.009ns (logic 0.612ns (60.640%) route 0.397ns (39.360%)) Logic Levels: 0 Clock Path Skew: -0.157ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.615ns Source Clock Delay (SCD): -0.458ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.850 -0.458 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X70Y105 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X70Y105 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.154 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/O net (fo=1, routed) 0.397 0.551 u_Axi_CDC/arFifo/_zz_ram_port10__1[18] SLICE_X66Y97 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.647 -0.615 u_Axi_CDC/arFifo/sys_clk SLICE_X66Y97 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.006ns (logic 0.491ns (48.819%) route 0.515ns (51.181%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.699ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.831 -0.477 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X84Y116 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y116 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.014 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/O net (fo=1, routed) 0.515 0.529 u_Axi_CDC/arFifo/_zz_ram_port10__1[8] SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.564 -0.699 u_Axi_CDC/arFifo/sys_clk SLICE_X82Y112 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.992ns (logic 0.612ns (61.686%) route 0.380ns (38.314%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.703ns Source Clock Delay (SCD): -0.472ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.836 -0.472 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X88Y130 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y130 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.140 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.380 0.520 u_Axi_CDC/wFifo/_zz_ram_port10__0[0] SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.560 -0.703 u_Axi_CDC/wFifo/sys_clk SLICE_X86Y130 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.990ns (logic 0.595ns (60.095%) route 0.395ns (39.905%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.705ns Source Clock Delay (SCD): -0.471ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.837 -0.471 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X88Y131 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y131 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.124 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.395 0.519 u_Axi_CDC/wFifo/_zz_ram_port10__0[7] SLICE_X82Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.558 -0.705 u_Axi_CDC/wFifo/sys_clk SLICE_X82Y129 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/C Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.514ns (logic 0.367ns (71.372%) route 0.147ns (28.628%)) Logic Levels: 0 Clock Path Skew: -0.396ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.688ns Source Clock Delay (SCD): -2.292ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/bFifo/cpu_clk SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y122 FDCE (Prop_fdce_C_Q) 0.367 -1.925 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.147 -1.778 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[1] SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.654 -2.688 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.611ns (logic 0.337ns (55.112%) route 0.274ns (44.888%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.302ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y125 FDCE (Prop_fdce_C_Q) 0.337 -1.965 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=5, routed) 0.274 -1.690 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[3] SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.665ns (logic 0.385ns (57.882%) route 0.280ns (42.118%)) Logic Levels: 0 Clock Path Skew: -0.400ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.688ns Source Clock Delay (SCD): -2.288ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.540 -2.288 u_Axi_CDC/bFifo/cpu_clk SLICE_X96Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y122 FDCE (Prop_fdce_C_Q) 0.385 -1.903 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.280 -1.623 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[2] SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.654 -2.688 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.672ns (logic 0.418ns (62.186%) route 0.254ns (37.814%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.675ns Source Clock Delay (SCD): -2.281ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.418 -1.863 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.254 -1.609 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[3] SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.738ns (logic 0.337ns (45.657%) route 0.401ns (54.343%)) Logic Levels: 0 Clock Path Skew: -0.402ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.700ns Source Clock Delay (SCD): -2.298ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 -2.298 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y105 FDCE (Prop_fdce_C_Q) 0.337 -1.961 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.401 -1.560 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.642 -2.700 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.779ns (logic 0.367ns (47.087%) route 0.412ns (52.913%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.302ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y125 FDCE (Prop_fdce_C_Q) 0.367 -1.935 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=3, routed) 0.412 -1.522 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[2] SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.781ns (logic 0.367ns (46.998%) route 0.414ns (53.002%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.302ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.526 -2.302 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y125 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y125 FDCE (Prop_fdce_C_Q) 0.367 -1.935 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.414 -1.521 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[0] SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.792ns (logic 0.367ns (46.340%) route 0.425ns (53.660%)) Logic Levels: 0 Clock Path Skew: -0.396ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.688ns Source Clock Delay (SCD): -2.292ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.536 -2.292 u_Axi_CDC/bFifo/cpu_clk SLICE_X95Y122 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y122 FDCE (Prop_fdce_C_Q) 0.367 -1.925 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.425 -1.500 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[0] SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.654 -2.688 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X94Y122 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.791ns (logic 0.367ns (46.425%) route 0.424ns (53.575%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.676ns Source Clock Delay (SCD): -2.283ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.545 -2.283 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y113 FDCE (Prop_fdce_C_Q) 0.367 -1.916 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.424 -1.492 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[1] SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.790ns (logic 0.418ns (52.908%) route 0.372ns (47.092%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.676ns Source Clock Delay (SCD): -2.281ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.418 -1.863 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.372 -1.491 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[1] SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.793ns (logic 0.367ns (46.304%) route 0.426ns (53.696%)) Logic Levels: 0 Clock Path Skew: -0.392ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.675ns Source Clock Delay (SCD): -2.283ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.545 -2.283 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y113 FDCE (Prop_fdce_C_Q) 0.367 -1.916 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.426 -1.490 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[0] SLICE_X92Y112 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y112 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.829ns (logic 0.418ns (50.441%) route 0.411ns (49.559%)) Logic Levels: 0 Clock Path Skew: -0.395ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.676ns Source Clock Delay (SCD): -2.281ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.418 -1.863 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.411 -1.452 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[0] SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X64Y104 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.847ns (logic 0.367ns (43.340%) route 0.480ns (56.660%)) Logic Levels: 0 Clock Path Skew: -0.398ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.697ns Source Clock Delay (SCD): -2.299ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.529 -2.299 u_Axi_CDC/wFifo/cpu_clk SLICE_X89Y127 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y127 FDCE (Prop_fdce_C_Q) 0.367 -1.932 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.480 -1.452 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[1] SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.645 -2.697 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X89Y126 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.870ns (logic 0.367ns (42.168%) route 0.503ns (57.832%)) Logic Levels: 0 Clock Path Skew: -0.402ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.700ns Source Clock Delay (SCD): -2.298ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 -2.298 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y105 FDCE (Prop_fdce_C_Q) 0.367 -1.931 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.503 -1.428 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[1] SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.642 -2.700 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.892ns (logic 0.367ns (41.125%) route 0.525ns (58.875%)) Logic Levels: 0 Clock Path Skew: -0.402ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.700ns Source Clock Delay (SCD): -2.298ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.530 -2.298 u_Axi_CDC/arFifo/cpu_clk SLICE_X86Y105 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y105 FDCE (Prop_fdce_C_Q) 0.367 -1.931 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.525 -1.405 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[0] SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.642 -2.700 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk SLICE_X83Y105 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.974ns (logic 0.337ns (34.595%) route 0.637ns (65.405%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.676ns Source Clock Delay (SCD): -2.283ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.545 -2.283 u_Axi_CDC/awFifo/cpu_clk SLICE_X93Y113 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y113 FDCE (Prop_fdce_C_Q) 0.337 -1.946 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.637 -1.309 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.666 -2.676 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X92Y113 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.171ns (logic 0.385ns (32.864%) route 0.786ns (67.136%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.675ns Source Clock Delay (SCD): -2.281ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.547 -2.281 u_Axi_CDC/rFifo/cpu_clk SLICE_X64Y103 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y103 FDCE (Prop_fdce_C_Q) 0.385 -1.896 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.786 -1.109 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[2] SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.667 -2.675 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X64Y102 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.215ns (logic 1.056ns (86.901%) route 0.159ns (13.099%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.684ns Source Clock Delay (SCD): -2.290ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.538 -2.290 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X88Y113 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X88Y113 RAMD32 (Prop_ramd32_CLK_O) 1.056 -1.234 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 0.159 -1.075 u_Axi_CDC/awFifo/_zz_ram_port10[7] SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.658 -2.684 u_Axi_CDC/awFifo/sys_clk SLICE_X89Y113 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%)) Logic Levels: 0 Clock Path Skew: -0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.669ns Source Clock Delay (SCD): -2.275ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.553 -2.275 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X60Y100 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y100 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.213 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/O net (fo=1, routed) 0.159 -1.054 u_Axi_CDC/awFifo/_zz_ram_port10[33] SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.673 -2.669 u_Axi_CDC/awFifo/sys_clk SLICE_X61Y100 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.000ns period=30.000ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.312ns (logic 1.062ns (80.930%) route 0.250ns (19.070%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.699ns Source Clock Delay (SCD): -2.306ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.233ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.216ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 r pll_clk.u_clk_pll/inst/clkout1_buf/I BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.522 -2.306 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X84Y117 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y117 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.244 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/O net (fo=1, routed) 0.250 -0.994 u_Axi_CDC/arFifo/_zz_ram_port10__1[15] SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.643 -2.699 u_Axi_CDC/arFifo/sys_clk SLICE_X85Y115 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: mlkem_clk To Clock: sys_clk Max Delay 61 Endpoints Min Delay 61 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 5.746ns (logic 0.642ns (11.174%) route 5.104ns (88.826%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.546ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 2.674 3.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1 SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.705 -2.123 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 5.746ns (logic 0.642ns (11.174%) route 5.104ns (88.826%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.546ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.123ns Source Clock Delay (SCD): -2.670ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.672 -2.670 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X92Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0] SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0 SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O net (fo=1066, routed) 2.674 3.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1 SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.705 -2.123 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X67Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.364ns (logic 0.612ns (44.884%) route 0.752ns (55.116%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 0.752 0.977 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.284ns (logic 0.612ns (47.657%) route 0.672ns (52.343%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.672 0.895 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0] SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.195ns (logic 0.595ns (49.811%) route 0.600ns (50.189%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.600 0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.183ns (logic 0.595ns (50.304%) route 0.588ns (49.696%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.386ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.588 0.797 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.169ns (logic 0.612ns (52.356%) route 0.557ns (47.644%)) Logic Levels: 0 Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.612ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 0.557 0.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.167ns (logic 0.612ns (52.454%) route 0.555ns (47.546%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.555 0.779 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.166ns (logic 0.480ns (41.172%) route 0.686ns (58.828%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.092 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 0.686 0.778 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.160ns (logic 0.612ns (52.737%) route 0.548ns (47.263%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.548 0.771 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.139ns (logic 0.612ns (53.734%) route 0.527ns (46.266%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.527 0.750 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.128ns (logic 0.595ns (52.742%) route 0.533ns (47.258%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X66Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.533 0.739 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.122ns (logic 0.595ns (53.042%) route 0.527ns (46.958%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.527 0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.103ns (logic 0.482ns (43.685%) route 0.621ns (56.315%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 0.621 0.714 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.093ns (logic 0.485ns (44.377%) route 0.608ns (55.623%)) Logic Levels: 0 Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.388ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X68Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.608 0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10] SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.073ns (logic 0.595ns (55.460%) route 0.478ns (44.540%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.478 0.684 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.071ns (logic 0.595ns (55.545%) route 0.476ns (44.455%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.476 0.682 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.064ns (logic 0.485ns (45.566%) route 0.579ns (54.434%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.609ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X66Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 0.579 0.675 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.051ns (logic 0.485ns (46.153%) route 0.566ns (53.847%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X68Y89 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 0.566 0.662 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4] SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.028ns (logic 0.485ns (47.163%) route 0.543ns (52.837%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.610ns Source Clock Delay (SCD): -0.389ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X68Y88 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.543 0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.636ns (logic 0.367ns (57.746%) route 0.269ns (42.254%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.367 -1.755 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.269 -1.487 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.633ns (logic 0.367ns (57.963%) route 0.266ns (42.037%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.499ns Source Clock Delay (SCD): -2.113ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 -2.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.266 -1.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[1] SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.637ns (logic 0.367ns (57.593%) route 0.270ns (42.407%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.367 -1.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.270 -1.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.682ns (logic 0.418ns (61.266%) route 0.264ns (38.734%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.514ns Source Clock Delay (SCD): -2.127ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.701 -2.127 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y97 FDCE (Prop_fdce_C_Q) 0.418 -1.709 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.264 -1.445 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.828 -2.514 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.684ns (logic 0.418ns (61.086%) route 0.266ns (38.914%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.514ns Source Clock Delay (SCD): -2.127ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.701 -2.127 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X76Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y97 FDCE (Prop_fdce_C_Q) 0.418 -1.709 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.266 -1.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[1] SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.828 -2.514 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.730ns (logic 0.337ns (46.159%) route 0.393ns (53.841%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.499ns Source Clock Delay (SCD): -2.113ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 -2.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.337 -1.776 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.393 -1.383 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.750ns (logic 0.367ns (48.935%) route 0.383ns (51.065%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.367 -1.755 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=3, routed) 0.383 -1.372 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2] SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.770ns (logic 0.367ns (47.632%) route 0.403ns (52.368%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.367 -1.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.403 -1.350 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[1] SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.776ns (logic 0.337ns (43.419%) route 0.439ns (56.581%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.337 -1.785 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=5, routed) 0.439 -1.346 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.792ns (logic 0.367ns (46.358%) route 0.425ns (53.642%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.367 -1.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.425 -1.324 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.837ns (logic 0.418ns (49.937%) route 0.419ns (50.063%)) Logic Levels: 0 Clock Path Skew: -0.391ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.514ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y96 FDCE (Prop_fdce_C_Q) 0.418 -1.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.419 -1.285 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.828 -2.514 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X76Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.844ns (logic 0.367ns (43.474%) route 0.477ns (56.526%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.367 -1.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.477 -1.276 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[0] SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.848ns (logic 0.337ns (39.750%) route 0.511ns (60.250%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.337 -1.783 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.511 -1.272 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.044ns (logic 0.367ns (35.163%) route 0.677ns (64.837%)) Logic Levels: 0 Clock Path Skew: -0.393ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.670ns Source Clock Delay (SCD): -2.277ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.551 -2.277 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X93Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y102 FDCE (Prop_fdce_C_Q) 0.367 -1.910 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q net (fo=2, routed) 0.677 -1.233 u_fft_mlkem_axi_slave/mlkem_intr_m SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.672 -2.670 u_fft_mlkem_axi_slave/sys_clk SLICE_X96Y110 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.902ns (logic 0.367ns (40.694%) route 0.535ns (59.306%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.509ns Source Clock Delay (SCD): -2.120ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.708 -2.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X49Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y80 FDCE (Prop_fdce_C_Q) 0.367 -1.753 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.535 -1.218 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[3] SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.833 -2.509 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X49Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.908ns (logic 0.367ns (40.413%) route 0.541ns (59.587%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.503ns Source Clock Delay (SCD): -2.115ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.713 -2.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X50Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y85 FDCE (Prop_fdce_C_Q) 0.367 -1.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.541 -1.207 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[1] SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.839 -2.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X50Y84 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.925ns (logic 0.367ns (39.693%) route 0.558ns (60.307%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.499ns Source Clock Delay (SCD): -2.113ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.715 -2.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X54Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y90 FDCE (Prop_fdce_C_Q) 0.367 -1.746 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.558 -1.189 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.843 -2.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X54Y89 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.985ns (logic 0.367ns (37.277%) route 0.618ns (62.723%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.507ns Source Clock Delay (SCD): -2.122ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.706 -2.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X67Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y88 FDCE (Prop_fdce_C_Q) 0.367 -1.755 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.618 -1.138 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y90 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.240ns (logic 1.078ns (86.936%) route 0.162ns (13.064%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.498ns Source Clock Delay (SCD): -2.112ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.716 -2.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y90 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y90 RAMD32 (Prop_ramd32_CLK_O) 1.078 -1.034 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 0.162 -0.872 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] SLICE_X53Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.844 -2.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X53Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.467ns (logic 1.062ns (72.369%) route 0.405ns (27.631%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.502ns Source Clock Delay (SCD): -2.117ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 r pll_clk.u_clk_pll/inst/clkout3_buf/I BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=17272, routed) 1.711 -2.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X64Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O) 1.062 -1.055 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O net (fo=1, routed) 0.405 -0.650 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.840 -2.502 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X63Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: clkfbout_clk_pll To Clock: Max Delay 1 Endpoint Min Delay 1 Endpoint -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT (clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Path Group: (none) Path Type: Max at Fast Process Corner Data Path Delay: 1.519ns (logic 0.029ns (1.909%) route 1.490ns (98.091%)) Logic Levels: 1 (BUFG=1) Clock Uncertainty: 0.225ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.110ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clkfbout_clk_pll fall edge) 10.000 10.000 f K21 0.000 10.000 f clk (IN) net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 K21 f pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 10.419 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 10.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.847 8.053 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT net (fo=1, routed) 0.611 8.663 pll_clk.u_clk_pll/inst/clkfbout_clk_pll BUFGCTRL_X0Y19 f pll_clk.u_clk_pll/inst/clkf_buf/I BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 8.692 f pll_clk.u_clk_pll/inst/clkf_buf/O net (fo=1, routed) 0.880 9.572 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN ------------------------------------------------------------------- ------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT (clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Path Group: (none) Path Type: Min at Slow Process Corner Data Path Delay: 3.498ns (logic 0.091ns (2.602%) route 3.407ns (97.398%)) Logic Levels: 1 (BUFG=1) Clock Uncertainty: 0.225ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.110ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clkfbout_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/clkfbout_clk_pll BUFGCTRL_X0Y19 r pll_clk.u_clk_pll/inst/clkf_buf/I BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkf_buf/O net (fo=1, routed) 1.652 -2.177 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: Max Delay 41 Endpoints Min Delay 41 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_axi_dvi/DVI_SQU_DIR_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 15.825ns (logic 6.208ns (39.226%) route 9.618ns (60.774%)) Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_axi_dvi/sys_clk SLICE_X42Y81 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.989 r u_axi_dvi/DVI_SQU_DIR_reg[0]/Q net (fo=5, routed) 1.348 -0.641 u_axi_dvi/DVI_SQU_DIR_reg_n_0_[0] SLICE_X42Y84 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/I0 SLICE_X42Y84 LUT2 (Prop_lut2_I0_O) 0.124 -0.517 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/O net (fo=1, routed) 0.000 -0.517 u_axi_dvi/video_red_OBUF[2]_inst_i_264_n_0 SLICE_X42Y84 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/S[0] SLICE_X42Y84 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 -0.004 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/CO[3] net (fo=1, routed) 0.000 -0.004 u_axi_dvi/video_red_OBUF[2]_inst_i_225_n_0 SLICE_X42Y85 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CI SLICE_X42Y85 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 0.113 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CO[3] net (fo=1, routed) 0.000 0.113 u_axi_dvi/video_red_OBUF[2]_inst_i_165_n_0 SLICE_X42Y86 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/CI SLICE_X42Y86 CARRY4 (Prop_carry4_CI_O[1]) 0.323 0.436 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/O[1] net (fo=1, routed) 1.222 1.658 u_axi_dvi/video_red_OBUF[2]_inst_i_96_n_6 SLICE_X42Y82 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/I1 SLICE_X42Y82 LUT2 (Prop_lut2_I1_O) 0.306 1.964 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/O net (fo=1, routed) 0.000 1.964 u_axi_dvi/video_red_OBUF[2]_inst_i_38_n_0 SLICE_X42Y82 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/S[1] SLICE_X42Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 2.497 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/CO[3] net (fo=1, routed) 0.000 2.497 u_axi_dvi/video_red_OBUF[2]_inst_i_7_n_0 SLICE_X42Y83 r u_axi_dvi/video_red_OBUF[2]_inst_i_2/CI SLICE_X42Y83 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 2.614 f u_axi_dvi/video_red_OBUF[2]_inst_i_2/CO[3] net (fo=1, routed) 1.354 3.969 u_axi_dvi/video_red_OBUF[2]_inst_i_2_n_0 SLICE_X41Y85 f u_axi_dvi/video_red_OBUF[2]_inst_i_1/I0 SLICE_X41Y85 LUT5 (Prop_lut5_I0_O) 0.124 4.093 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 5.693 9.786 video_red_OBUF[0] K23 r video_red_OBUF[0]_inst/I K23 OBUF (Prop_obuf_I_O) 3.533 13.319 r video_red_OBUF[0]_inst/O net (fo=0) 0.000 13.319 video_red[0] K23 r video_red[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_SQU_DIR_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 15.712ns (logic 6.235ns (39.686%) route 9.476ns (60.314%)) Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_axi_dvi/sys_clk SLICE_X42Y81 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.989 r u_axi_dvi/DVI_SQU_DIR_reg[0]/Q net (fo=5, routed) 1.348 -0.641 u_axi_dvi/DVI_SQU_DIR_reg_n_0_[0] SLICE_X42Y84 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/I0 SLICE_X42Y84 LUT2 (Prop_lut2_I0_O) 0.124 -0.517 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/O net (fo=1, routed) 0.000 -0.517 u_axi_dvi/video_red_OBUF[2]_inst_i_264_n_0 SLICE_X42Y84 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/S[0] SLICE_X42Y84 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 -0.004 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/CO[3] net (fo=1, routed) 0.000 -0.004 u_axi_dvi/video_red_OBUF[2]_inst_i_225_n_0 SLICE_X42Y85 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CI SLICE_X42Y85 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 0.113 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CO[3] net (fo=1, routed) 0.000 0.113 u_axi_dvi/video_red_OBUF[2]_inst_i_165_n_0 SLICE_X42Y86 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/CI SLICE_X42Y86 CARRY4 (Prop_carry4_CI_O[1]) 0.323 0.436 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/O[1] net (fo=1, routed) 1.222 1.658 u_axi_dvi/video_red_OBUF[2]_inst_i_96_n_6 SLICE_X42Y82 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/I1 SLICE_X42Y82 LUT2 (Prop_lut2_I1_O) 0.306 1.964 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/O net (fo=1, routed) 0.000 1.964 u_axi_dvi/video_red_OBUF[2]_inst_i_38_n_0 SLICE_X42Y82 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/S[1] SLICE_X42Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 2.497 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/CO[3] net (fo=1, routed) 0.000 2.497 u_axi_dvi/video_red_OBUF[2]_inst_i_7_n_0 SLICE_X42Y83 r u_axi_dvi/video_red_OBUF[2]_inst_i_2/CI SLICE_X42Y83 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 2.614 f u_axi_dvi/video_red_OBUF[2]_inst_i_2/CO[3] net (fo=1, routed) 1.354 3.969 u_axi_dvi/video_red_OBUF[2]_inst_i_2_n_0 SLICE_X41Y85 f u_axi_dvi/video_red_OBUF[2]_inst_i_1/I0 SLICE_X41Y85 LUT5 (Prop_lut5_I0_O) 0.124 4.093 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 5.552 9.645 video_red_OBUF[0] F24 r video_red_OBUF[1]_inst/I F24 OBUF (Prop_obuf_I_O) 3.560 13.205 r video_red_OBUF[1]_inst/O net (fo=0) 0.000 13.205 video_red[1] F24 r video_red[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_SQU_DIR_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 15.445ns (logic 6.262ns (40.541%) route 9.183ns (59.459%)) Logic Levels: 9 (CARRY4=5 LUT2=2 LUT5=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.835 -2.507 u_axi_dvi/sys_clk SLICE_X42Y81 FDRE r u_axi_dvi/DVI_SQU_DIR_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.989 r u_axi_dvi/DVI_SQU_DIR_reg[0]/Q net (fo=5, routed) 1.348 -0.641 u_axi_dvi/DVI_SQU_DIR_reg_n_0_[0] SLICE_X42Y84 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/I0 SLICE_X42Y84 LUT2 (Prop_lut2_I0_O) 0.124 -0.517 r u_axi_dvi/video_red_OBUF[2]_inst_i_264/O net (fo=1, routed) 0.000 -0.517 u_axi_dvi/video_red_OBUF[2]_inst_i_264_n_0 SLICE_X42Y84 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/S[0] SLICE_X42Y84 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 -0.004 r u_axi_dvi/video_red_OBUF[2]_inst_i_225/CO[3] net (fo=1, routed) 0.000 -0.004 u_axi_dvi/video_red_OBUF[2]_inst_i_225_n_0 SLICE_X42Y85 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CI SLICE_X42Y85 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 0.113 r u_axi_dvi/video_red_OBUF[2]_inst_i_165/CO[3] net (fo=1, routed) 0.000 0.113 u_axi_dvi/video_red_OBUF[2]_inst_i_165_n_0 SLICE_X42Y86 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/CI SLICE_X42Y86 CARRY4 (Prop_carry4_CI_O[1]) 0.323 0.436 r u_axi_dvi/video_red_OBUF[2]_inst_i_96/O[1] net (fo=1, routed) 1.222 1.658 u_axi_dvi/video_red_OBUF[2]_inst_i_96_n_6 SLICE_X42Y82 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/I1 SLICE_X42Y82 LUT2 (Prop_lut2_I1_O) 0.306 1.964 r u_axi_dvi/video_red_OBUF[2]_inst_i_38/O net (fo=1, routed) 0.000 1.964 u_axi_dvi/video_red_OBUF[2]_inst_i_38_n_0 SLICE_X42Y82 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/S[1] SLICE_X42Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 2.497 r u_axi_dvi/video_red_OBUF[2]_inst_i_7/CO[3] net (fo=1, routed) 0.000 2.497 u_axi_dvi/video_red_OBUF[2]_inst_i_7_n_0 SLICE_X42Y83 r u_axi_dvi/video_red_OBUF[2]_inst_i_2/CI SLICE_X42Y83 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 2.614 f u_axi_dvi/video_red_OBUF[2]_inst_i_2/CO[3] net (fo=1, routed) 1.354 3.969 u_axi_dvi/video_red_OBUF[2]_inst_i_2_n_0 SLICE_X41Y85 f u_axi_dvi/video_red_OBUF[2]_inst_i_1/I0 SLICE_X41Y85 LUT5 (Prop_lut5_I0_O) 0.124 4.093 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 5.259 9.352 video_red_OBUF[0] E26 r video_red_OBUF[2]_inst/I E26 OBUF (Prop_obuf_I_O) 3.587 12.938 r video_red_OBUF[2]_inst/O net (fo=0) 0.000 12.938 video_red[2] E26 r video_red[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_clk (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.589ns (logic 3.629ns (42.252%) route 4.960ns (57.748%)) Logic Levels: 2 (BUFG=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk fall edge) 10.000 10.000 f K21 0.000 10.000 f clk (IN) net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 K21 f pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 11.463 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 12.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 3.725 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 5.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 f pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 5.658 f pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 3.123 8.781 video_clk_OBUF H22 f video_clk_OBUF_inst/I H22 OBUF (Prop_obuf_I_O) 3.533 12.314 f video_clk_OBUF_inst/O net (fo=0) 0.000 12.314 video_clk H22 f video_clk (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_vsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 12.805ns (logic 4.379ns (34.194%) route 8.427ns (65.806%)) Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.838 -2.504 u_axi_dvi/sys_clk SLICE_X47Y82 FDRE r u_axi_dvi/vdata_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y82 FDRE (Prop_fdre_C_Q) 0.456 -2.048 f u_axi_dvi/vdata_reg[6]/Q net (fo=13, routed) 1.558 -0.490 u_axi_dvi/vdata_reg_n_0_[6] SLICE_X49Y83 f u_axi_dvi/video_vsync_OBUF_inst_i_5/I1 SLICE_X49Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.366 f u_axi_dvi/video_vsync_OBUF_inst_i_5/O net (fo=1, routed) 0.667 0.301 u_axi_dvi/video_vsync_OBUF_inst_i_5_n_0 SLICE_X49Y83 f u_axi_dvi/video_vsync_OBUF_inst_i_3/I5 SLICE_X49Y83 LUT6 (Prop_lut6_I5_O) 0.124 0.425 r u_axi_dvi/video_vsync_OBUF_inst_i_3/O net (fo=1, routed) 0.298 0.723 u_axi_dvi/video_vsync_OBUF_inst_i_3_n_0 SLICE_X49Y81 r u_axi_dvi/video_vsync_OBUF_inst_i_1/I2 SLICE_X49Y81 LUT4 (Prop_lut4_I2_O) 0.124 0.847 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O net (fo=1, routed) 5.904 6.751 video_vsync_OBUF H24 r video_vsync_OBUF_inst/I H24 OBUF (Prop_obuf_I_O) 3.551 10.302 r video_vsync_OBUF_inst/O net (fo=0) 0.000 10.302 video_vsync H24 r video_vsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_de (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 12.756ns (logic 4.389ns (34.405%) route 8.367ns (65.595%)) Logic Levels: 4 (LUT2=1 LUT6=2 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.836 -2.506 u_axi_dvi/sys_clk SLICE_X47Y81 FDRE r u_axi_dvi/vdata_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y81 FDRE (Prop_fdre_C_Q) 0.456 -2.050 f u_axi_dvi/vdata_reg[3]/Q net (fo=11, routed) 1.027 -1.023 u_axi_dvi/vdata_reg_n_0_[3] SLICE_X48Y83 f u_axi_dvi/vdata[11]_i_4/I0 SLICE_X48Y83 LUT2 (Prop_lut2_I0_O) 0.124 -0.899 r u_axi_dvi/vdata[11]_i_4/O net (fo=3, routed) 0.717 -0.182 u_axi_dvi/vdata[11]_i_4_n_0 SLICE_X49Y83 r u_axi_dvi/video_de_OBUF_inst_i_2/I2 SLICE_X49Y83 LUT6 (Prop_lut6_I2_O) 0.124 -0.058 r u_axi_dvi/video_de_OBUF_inst_i_2/O net (fo=1, routed) 0.863 0.805 u_axi_dvi/video_de_OBUF_inst_i_2_n_0 SLICE_X46Y83 r u_axi_dvi/video_de_OBUF_inst_i_1/I0 SLICE_X46Y83 LUT6 (Prop_lut6_I0_O) 0.124 0.929 r u_axi_dvi/video_de_OBUF_inst_i_1/O net (fo=1, routed) 5.761 6.690 video_de_OBUF G24 r video_de_OBUF_inst/I G24 OBUF (Prop_obuf_I_O) 3.561 10.251 r video_de_OBUF_inst/O net (fo=0) 0.000 10.251 video_de G24 r video_de (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[4]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_hsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.845ns (logic 4.311ns (36.394%) route 7.534ns (63.606%)) Logic Levels: 3 (LUT5=2 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.840 -2.502 u_axi_dvi/sys_clk SLICE_X46Y84 FDRE r u_axi_dvi/hdata_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y84 FDRE (Prop_fdre_C_Q) 0.518 -1.984 r u_axi_dvi/hdata_reg[4]/Q net (fo=11, routed) 1.550 -0.433 u_axi_dvi/hdata_reg_n_0_[4] SLICE_X41Y85 r u_axi_dvi/video_hsync_OBUF_inst_i_2/I4 SLICE_X41Y85 LUT5 (Prop_lut5_I4_O) 0.124 -0.309 f u_axi_dvi/video_hsync_OBUF_inst_i_2/O net (fo=1, routed) 0.291 -0.018 u_axi_dvi/video_hsync_OBUF_inst_i_2_n_0 SLICE_X41Y86 f u_axi_dvi/video_hsync_OBUF_inst_i_1/I4 SLICE_X41Y86 LUT5 (Prop_lut5_I4_O) 0.124 0.106 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O net (fo=1, routed) 5.693 5.799 video_hsync_OBUF J24 r video_hsync_OBUF_inst/I J24 OBUF (Prop_obuf_I_O) 3.545 9.343 r video_hsync_OBUF_inst/O net (fo=0) 0.000 9.343 video_hsync J24 r video_hsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.827ns (logic 4.074ns (37.631%) route 6.753ns (62.369%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q net (fo=1, routed) 6.753 4.594 dpy0_OBUF[6] B17 r dpy0_OBUF[6]_inst/I B17 OBUF (Prop_obuf_I_O) 3.556 8.151 r dpy0_OBUF[6]_inst/O net (fo=0) 0.000 8.151 dpy0[6] B17 r dpy0[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_TX (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.830ns (logic 4.317ns (39.866%) route 6.513ns (60.134%)) Logic Levels: 2 (LUT3=1 OBUFT=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.638 -2.704 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X80Y133 FDRE r u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y133 FDRE (Prop_fdre_C_Q) 0.478 -2.226 f u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/Q net (fo=13, routed) 1.393 -0.832 u_axi_uart_controller/uart0/regs/transmitter/tf_pop_reg_0[1] SLICE_X77Y137 f u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/I1 SLICE_X77Y137 LUT3 (Prop_lut3_I1_O) 0.295 -0.537 f u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O net (fo=1, routed) 5.119 4.582 UART_TX_IOBUF_inst/T H18 f UART_TX_IOBUF_inst/OBUFT/T H18 OBUFT (TriStatE_obuft_T_O) 3.544 8.126 r UART_TX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 8.126 UART_TX H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.564ns (logic 4.063ns (38.456%) route 6.502ns (61.544%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q net (fo=1, routed) 6.502 4.343 dpy0_OBUF[7] C17 r dpy0_OBUF[7]_inst/I C17 OBUF (Prop_obuf_I_O) 3.545 7.888 r dpy0_OBUF[7]_inst/O net (fo=0) 0.000 7.888 dpy0[7] C17 r dpy0[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.495ns (logic 4.057ns (38.657%) route 6.438ns (61.343%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q net (fo=1, routed) 6.438 4.280 dpy0_OBUF[4] E18 r dpy0_OBUF[4]_inst/I E18 OBUF (Prop_obuf_I_O) 3.539 7.819 r dpy0_OBUF[4]_inst/O net (fo=0) 0.000 7.819 dpy0[4] E18 r dpy0[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_RX (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.517ns (logic 4.100ns (38.989%) route 6.416ns (61.011%)) Logic Levels: 2 (LUT2=1 OBUFT=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.643 -2.699 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X85Y134 FDRE r u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y134 FDRE (Prop_fdre_C_Q) 0.456 -2.243 r u_axi_uart_controller/uart0/regs/mode_reg_reg[3]/Q net (fo=2, routed) 0.810 -1.433 u_axi_uart_controller/uart0/regs/sclk_por SLICE_X86Y135 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/I1 SLICE_X86Y135 LUT2 (Prop_lut2_I1_O) 0.124 -1.309 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/O net (fo=1, routed) 5.607 4.298 UART_RX_IOBUF_inst/I J20 r UART_RX_IOBUF_inst/OBUFT/I J20 OBUFT (Prop_obuft_I_O) 3.520 7.818 r UART_RX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 7.818 UART_RX J20 r UART_RX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.196ns (logic 4.016ns (39.389%) route 6.180ns (60.611%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.666 -2.676 u_confreg/u_digitaltube_controller/sys_clk SLICE_X63Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y141 FDCE (Prop_fdce_C_Q) 0.456 -2.220 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q net (fo=1, routed) 6.180 3.960 dpy0_OBUF[0] B19 r dpy0_OBUF[0]_inst/I B19 OBUF (Prop_obuf_I_O) 3.560 7.520 r dpy0_OBUF[0]_inst/O net (fo=0) 0.000 7.520 dpy0[0] B19 r dpy0[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.115ns (logic 4.038ns (39.923%) route 6.077ns (60.077%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q net (fo=1, routed) 6.077 3.899 dpy1_OBUF[7] G17 r dpy1_OBUF[7]_inst/I G17 OBUF (Prop_obuf_I_O) 3.520 7.419 r dpy1_OBUF[7]_inst/O net (fo=0) 0.000 7.419 dpy1[7] G17 r dpy1[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.022ns (logic 4.002ns (39.929%) route 6.021ns (60.071%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.456 -2.221 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q net (fo=1, routed) 6.021 3.800 dpy0_OBUF[5] C19 r dpy0_OBUF[5]_inst/I C19 OBUF (Prop_obuf_I_O) 3.546 7.346 r dpy0_OBUF[5]_inst/O net (fo=0) 0.000 7.346 dpy0[5] C19 r dpy0[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.920ns (logic 4.091ns (41.241%) route 5.829ns (58.759%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.665 -2.677 u_confreg/u_digitaltube_controller/sys_clk SLICE_X64Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y141 FDCE (Prop_fdce_C_Q) 0.518 -2.159 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q net (fo=1, routed) 5.829 3.670 dpy0_OBUF[3] A19 r dpy0_OBUF[3]_inst/I A19 OBUF (Prop_obuf_I_O) 3.573 7.243 r dpy0_OBUF[3]_inst/O net (fo=0) 0.000 7.243 dpy0[3] A19 r dpy0[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.911ns (logic 4.032ns (40.684%) route 5.879ns (59.316%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q net (fo=1, routed) 5.879 3.701 dpy1_OBUF[3] F17 r dpy1_OBUF[3]_inst/I F17 OBUF (Prop_obuf_I_O) 3.514 7.215 r dpy1_OBUF[3]_inst/O net (fo=0) 0.000 7.215 dpy1[3] F17 r dpy1[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.858ns (logic 4.055ns (41.135%) route 5.803ns (58.865%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.644 -2.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.518 -2.180 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q net (fo=1, routed) 5.803 3.623 dpy1_OBUF[6] F15 r dpy1_OBUF[6]_inst/I F15 OBUF (Prop_obuf_I_O) 3.537 7.160 r dpy1_OBUF[6]_inst/O net (fo=0) 0.000 7.160 dpy1[6] F15 r dpy1[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.779ns (logic 4.052ns (41.435%) route 5.727ns (58.565%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.644 -2.698 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.518 -2.180 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q net (fo=1, routed) 5.727 3.547 dpy1_OBUF[5] G16 r dpy1_OBUF[5]_inst/I G16 OBUF (Prop_obuf_I_O) 3.534 7.081 r dpy1_OBUF[5]_inst/O net (fo=0) 0.000 7.081 dpy1[5] G16 r dpy1[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.775ns (logic 4.060ns (41.529%) route 5.716ns (58.471%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.646 -2.696 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y164 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y164 FDCE (Prop_fdce_C_Q) 0.518 -2.178 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q net (fo=1, routed) 5.716 3.538 dpy1_OBUF[4] E16 r dpy1_OBUF[4]_inst/I E16 OBUF (Prop_obuf_I_O) 3.542 7.079 r dpy1_OBUF[4]_inst/O net (fo=0) 0.000 7.079 dpy1[4] E16 r dpy1[4] (OUT) ------------------------------------------------------------------- ------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_clk (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.614ns (logic 1.260ns (48.196%) route 1.354ns (51.804%)) Logic Levels: 2 (BUFG=1 OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.794 -0.468 video_clk_OBUF H22 r video_clk_OBUF_inst/I H22 OBUF (Prop_obuf_I_O) 1.234 0.766 r video_clk_OBUF_inst/O net (fo=0) 0.000 0.766 video_clk H22 r video_clk (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[9]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[9] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.581ns (logic 1.447ns (56.055%) route 1.134ns (43.945%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X14Y141 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X14Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[9]_lopt_replica/Q net (fo=1, routed) 1.134 0.663 lopt_15 A23 r leds_OBUF[9]_inst/I A23 OBUF (Prop_obuf_I_O) 1.283 1.946 r leds_OBUF[9]_inst/O net (fo=0) 0.000 1.946 leds[9] A23 r leds[9] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[15]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[15] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.597ns (logic 1.427ns (54.964%) route 1.170ns (45.036%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X12Y142 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[15]_lopt_replica/Q net (fo=1, routed) 1.170 0.699 lopt_6 B20 r leds_OBUF[15]_inst/I B20 OBUF (Prop_obuf_I_O) 1.263 1.962 r leds_OBUF[15]_inst/O net (fo=0) 0.000 1.962 leds[15] B20 r leds[15] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[10]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[10] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.666ns (logic 1.412ns (52.947%) route 1.255ns (47.053%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk SLICE_X20Y141 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X20Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[10]_lopt_replica/Q net (fo=1, routed) 1.255 0.781 lopt_1 D21 r leds_OBUF[10]_inst/I D21 OBUF (Prop_obuf_I_O) 1.248 2.028 r leds_OBUF[10]_inst/O net (fo=0) 0.000 2.028 leds[10] D21 r leds[10] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[12]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[12] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.709ns (logic 1.384ns (51.091%) route 1.325ns (48.909%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X13Y142 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X13Y142 FDRE (Prop_fdre_C_Q) 0.141 -0.494 r u_confreg/led_data_reg[12]_lopt_replica/Q net (fo=1, routed) 1.325 0.831 lopt_3 D20 r leds_OBUF[12]_inst/I D20 OBUF (Prop_obuf_I_O) 1.243 2.074 r leds_OBUF[12]_inst/O net (fo=0) 0.000 2.074 leds[12] D20 r leds[12] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.736ns (logic 1.439ns (52.603%) route 1.297ns (47.397%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk SLICE_X22Y141 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[0]_lopt_replica/Q net (fo=1, routed) 1.297 0.823 lopt B24 r leds_OBUF[0]_inst/I B24 OBUF (Prop_obuf_I_O) 1.275 2.098 r leds_OBUF[0]_inst/O net (fo=0) 0.000 2.098 leds[0] B24 r leds[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[11]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[11] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.765ns (logic 1.431ns (51.772%) route 1.333ns (48.228%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X12Y141 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[11]_lopt_replica/Q net (fo=1, routed) 1.333 0.862 lopt_2 A18 r leds_OBUF[11]_inst/I A18 OBUF (Prop_obuf_I_O) 1.267 2.130 r leds_OBUF[11]_inst/O net (fo=0) 0.000 2.130 leds[11] A18 r leds[11] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[1]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.956ns (logic 1.406ns (47.555%) route 1.550ns (52.445%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X12Y142 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[1]_lopt_replica/Q net (fo=1, routed) 1.550 1.079 lopt_7 E21 r leds_OBUF[1]_inst/I E21 OBUF (Prop_obuf_I_O) 1.242 2.321 r leds_OBUF[1]_inst/O net (fo=0) 0.000 2.321 leds[1] E21 r leds[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[13]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[13] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.031ns (logic 1.412ns (46.583%) route 1.619ns (53.417%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X13Y142 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X13Y142 FDRE (Prop_fdre_C_Q) 0.141 -0.494 r u_confreg/led_data_reg[13]_lopt_replica/Q net (fo=1, routed) 1.619 1.125 lopt_4 A22 r leds_OBUF[13]_inst/I A22 OBUF (Prop_obuf_I_O) 1.271 2.396 r leds_OBUF[13]_inst/O net (fo=0) 0.000 2.396 leds[13] A22 r leds[13] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[5]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[5] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.069ns (logic 1.418ns (46.208%) route 1.651ns (53.792%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk SLICE_X20Y141 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X20Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[5]_lopt_replica/Q net (fo=1, routed) 1.651 1.177 lopt_11 C21 r leds_OBUF[5]_inst/I C21 OBUF (Prop_obuf_I_O) 1.254 2.431 r leds_OBUF[5]_inst/O net (fo=0) 0.000 2.431 leds[5] C21 r leds[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[3]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[3] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.092ns (logic 1.427ns (46.147%) route 1.665ns (53.853%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.617 -0.646 u_confreg/sys_clk SLICE_X36Y141 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X36Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.482 r u_confreg/led_data_reg[3]_lopt_replica/Q net (fo=1, routed) 1.665 1.183 lopt_9 D23 r leds_OBUF[3]_inst/I D23 OBUF (Prop_obuf_I_O) 1.263 2.446 r leds_OBUF[3]_inst/O net (fo=0) 0.000 2.446 leds[3] D23 r leds[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[8]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[8] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.086ns (logic 1.426ns (46.198%) route 1.660ns (53.802%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk SLICE_X22Y141 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[8]_lopt_replica/Q net (fo=1, routed) 1.660 1.186 lopt_14 C23 r leds_OBUF[8]_inst/I C23 OBUF (Prop_obuf_I_O) 1.262 2.448 r leds_OBUF[8]_inst/O net (fo=0) 0.000 2.448 leds[8] C23 r leds[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[4]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[4] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.088ns (logic 1.427ns (46.209%) route 1.661ns (53.791%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk SLICE_X22Y141 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[4]_lopt_replica/Q net (fo=1, routed) 1.661 1.187 lopt_10 C22 r leds_OBUF[4]_inst/I C22 OBUF (Prop_obuf_I_O) 1.263 2.450 r leds_OBUF[4]_inst/O net (fo=0) 0.000 2.450 leds[4] C22 r leds[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[7]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.095ns (logic 1.437ns (46.407%) route 1.659ns (53.593%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X12Y142 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[7]_lopt_replica/Q net (fo=1, routed) 1.659 1.188 lopt_13 B22 r leds_OBUF[7]_inst/I B22 OBUF (Prop_obuf_I_O) 1.273 2.461 r leds_OBUF[7]_inst/O net (fo=0) 0.000 2.461 leds[7] B22 r leds[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[6]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[6] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.132ns (logic 1.406ns (44.897%) route 1.726ns (55.103%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.628 -0.635 u_confreg/sys_clk SLICE_X12Y142 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X12Y142 FDRE (Prop_fdre_C_Q) 0.164 -0.471 r u_confreg/led_data_reg[6]_lopt_replica/Q net (fo=1, routed) 1.726 1.255 lopt_12 E20 r leds_OBUF[6]_inst/I E20 OBUF (Prop_obuf_I_O) 1.242 2.497 r leds_OBUF[6]_inst/O net (fo=0) 0.000 2.497 leds[6] E20 r leds[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[14]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[14] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.179ns (logic 1.427ns (44.902%) route 1.752ns (55.098%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.625 -0.638 u_confreg/sys_clk SLICE_X22Y141 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X22Y141 FDRE (Prop_fdre_C_Q) 0.164 -0.474 r u_confreg/led_data_reg[14]_lopt_replica/Q net (fo=1, routed) 1.752 1.278 lopt_5 A20 r leds_OBUF[14]_inst/I A20 OBUF (Prop_obuf_I_O) 1.263 2.541 r leds_OBUF[14]_inst/O net (fo=0) 0.000 2.541 leds[14] A20 r leds[14] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[2]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.213ns (logic 1.451ns (45.157%) route 1.762ns (54.843%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.617 -0.646 u_confreg/sys_clk SLICE_X36Y140 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X36Y140 FDRE (Prop_fdre_C_Q) 0.164 -0.482 r u_confreg/led_data_reg[2]_lopt_replica/Q net (fo=1, routed) 1.762 1.280 lopt_8 A24 r leds_OBUF[2]_inst/I A24 OBUF (Prop_obuf_I_O) 1.287 2.567 r leds_OBUF[2]_inst/O net (fo=0) 0.000 2.567 leds[2] A24 r leds[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_TX (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.463ns (logic 1.033ns (29.825%) route 2.430ns (70.175%)) Logic Levels: 2 (LUT3=1 OBUFT=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.572 -0.691 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X76Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C ------------------------------------------------------------------- ------------------- SLICE_X76Y137 FDRE (Prop_fdre_C_Q) 0.164 -0.527 r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/Q net (fo=2, routed) 0.147 -0.380 u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en SLICE_X77Y137 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/I0 SLICE_X77Y137 LUT3 (Prop_lut3_I0_O) 0.045 -0.335 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O net (fo=1, routed) 2.283 1.949 UART_TX_IOBUF_inst/T H18 r UART_TX_IOBUF_inst/OBUFT/T H18 OBUFT (TriStatD_obuft_T_O) 0.824 2.773 r UART_TX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 2.773 UART_TX H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.498ns (logic 1.406ns (40.207%) route 2.091ns (59.793%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.573 -0.690 u_confreg/u_digitaltube_controller/sys_clk SLICE_X62Y165 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y165 FDCE (Prop_fdce_C_Q) 0.164 -0.526 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q net (fo=1, routed) 2.091 1.566 dpy1_OBUF[2] E17 r dpy1_OBUF[2]_inst/I E17 OBUF (Prop_obuf_I_O) 1.242 2.808 r dpy1_OBUF[2]_inst/O net (fo=0) 0.000 2.808 dpy1[2] E17 r dpy1[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.553ns (logic 1.387ns (39.035%) route 2.166ns (60.965%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.581 -0.682 u_confreg/u_digitaltube_controller/sys_clk SLICE_X65Y141 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y141 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q net (fo=1, routed) 2.166 1.625 dpy0_OBUF[1] D19 r dpy0_OBUF[1]_inst/I D19 OBUF (Prop_obuf_I_O) 1.246 2.871 r dpy0_OBUF[1]_inst/O net (fo=0) 0.000 2.871 dpy0[1] D19 r dpy0[1] (OUT) ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: To Clock: sys_clk Max Delay 43 Endpoints Min Delay 43 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: dip_sw[22] (input port) Destination: u_confreg/s_rdata_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.330ns (logic 1.710ns (20.531%) route 6.620ns (79.469%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P6 0.000 0.000 r dip_sw[22] (IN) net (fo=0) 0.000 0.000 dip_sw[22] P6 r dip_sw_IBUF[22]_inst/I P6 IBUF (Prop_ibuf_I_O) 1.462 1.462 r dip_sw_IBUF[22]_inst/O net (fo=1, routed) 5.658 7.120 u_confreg/dip_sw_IBUF[22] SLICE_X58Y140 r u_confreg/s_rdata[22]_i_4/I4 SLICE_X58Y140 LUT5 (Prop_lut5_I4_O) 0.124 7.244 r u_confreg/s_rdata[22]_i_4/O net (fo=1, routed) 0.963 8.206 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 SLICE_X52Y140 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/I4 SLICE_X52Y140 LUT6 (Prop_lut6_I4_O) 0.124 8.330 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O net (fo=1, routed) 0.000 8.330 u_confreg/u_int_ctrl_n_9 SLICE_X52Y140 FDRE r u_confreg/s_rdata_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.551 -2.277 u_confreg/sys_clk SLICE_X52Y140 FDRE r u_confreg/s_rdata_reg[22]/C Slack: inf Source: dip_sw[29] (input port) Destination: u_confreg/s_rdata_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.156ns (logic 1.726ns (21.164%) route 6.430ns (78.836%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T5 0.000 0.000 r dip_sw[29] (IN) net (fo=0) 0.000 0.000 dip_sw[29] T5 r dip_sw_IBUF[29]_inst/I T5 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[29]_inst/O net (fo=1, routed) 5.466 6.944 u_confreg/dip_sw_IBUF[29] SLICE_X60Y139 r u_confreg/s_rdata[29]_i_4/I4 SLICE_X60Y139 LUT5 (Prop_lut5_I4_O) 0.124 7.068 r u_confreg/s_rdata[29]_i_4/O net (fo=1, routed) 0.963 8.032 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 SLICE_X57Y140 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/I4 SLICE_X57Y140 LUT6 (Prop_lut6_I4_O) 0.124 8.156 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O net (fo=1, routed) 0.000 8.156 u_confreg/u_int_ctrl_n_2 SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[29]/C Slack: inf Source: dip_sw[19] (input port) Destination: u_confreg/s_rdata_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.100ns (logic 1.726ns (21.311%) route 6.374ns (78.689%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L4 0.000 0.000 r dip_sw[19] (IN) net (fo=0) 0.000 0.000 dip_sw[19] L4 r dip_sw_IBUF[19]_inst/I L4 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[19]_inst/O net (fo=1, routed) 5.423 6.901 u_confreg/dip_sw_IBUF[19] SLICE_X54Y136 r u_confreg/s_rdata[19]_i_4/I4 SLICE_X54Y136 LUT5 (Prop_lut5_I4_O) 0.124 7.025 r u_confreg/s_rdata[19]_i_4/O net (fo=1, routed) 0.951 7.976 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 SLICE_X48Y135 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/I4 SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.124 8.100 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O net (fo=1, routed) 0.000 8.100 u_confreg/u_int_ctrl_n_12 SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[19]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.928ns (logic 1.980ns (24.979%) route 5.948ns (75.021%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) Clock Path Skew: -2.306ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 f UART_TX_IOBUF_inst/IBUF/I H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 5.067 6.541 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X79Y136 f u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/I1 SLICE_X79Y136 LUT2 (Prop_lut2_I1_O) 0.152 6.693 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.881 7.574 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X78Y136 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/I1 SLICE_X78Y136 LUT5 (Prop_lut5_I1_O) 0.354 7.928 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O net (fo=1, routed) 0.000 7.928 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 SLICE_X78Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.522 -2.306 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X78Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C Slack: inf Source: dip_sw[14] (input port) Destination: u_confreg/s_rdata_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.857ns (logic 1.763ns (22.438%) route 6.094ns (77.562%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J1 0.000 0.000 r dip_sw[14] (IN) net (fo=0) 0.000 0.000 dip_sw[14] J1 r dip_sw_IBUF[14]_inst/I J1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r dip_sw_IBUF[14]_inst/O net (fo=1, routed) 4.730 6.245 u_confreg/dip_sw_IBUF[14] SLICE_X62Y135 r u_confreg/s_rdata[14]_i_4/I4 SLICE_X62Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.369 r u_confreg/s_rdata[14]_i_4/O net (fo=1, routed) 1.365 7.733 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 SLICE_X49Y135 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/I4 SLICE_X49Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.857 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O net (fo=1, routed) 0.000 7.857 u_confreg/u_int_ctrl_n_17 SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[14]/C Slack: inf Source: dip_sw[27] (input port) Destination: u_confreg/s_rdata_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.823ns (logic 1.753ns (22.406%) route 6.070ns (77.594%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R1 0.000 0.000 r dip_sw[27] (IN) net (fo=0) 0.000 0.000 dip_sw[27] R1 r dip_sw_IBUF[27]_inst/I R1 IBUF (Prop_ibuf_I_O) 1.505 1.505 r dip_sw_IBUF[27]_inst/O net (fo=1, routed) 4.956 6.461 u_confreg/dip_sw_IBUF[27] SLICE_X61Y135 r u_confreg/s_rdata[27]_i_4/I4 SLICE_X61Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.585 r u_confreg/s_rdata[27]_i_4/O net (fo=1, routed) 1.114 7.699 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 SLICE_X50Y137 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/I4 SLICE_X50Y137 LUT6 (Prop_lut6_I4_O) 0.124 7.823 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O net (fo=1, routed) 0.000 7.823 u_confreg/u_int_ctrl_n_4 SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[27]/C Slack: inf Source: dip_sw[15] (input port) Destination: u_confreg/s_rdata_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.701ns (logic 1.742ns (22.623%) route 5.959ns (77.377%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L2 0.000 0.000 r dip_sw[15] (IN) net (fo=0) 0.000 0.000 dip_sw[15] L2 r dip_sw_IBUF[15]_inst/I L2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[15]_inst/O net (fo=1, routed) 5.004 6.498 u_confreg/dip_sw_IBUF[15] SLICE_X58Y135 r u_confreg/s_rdata[15]_i_4/I4 SLICE_X58Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.622 r u_confreg/s_rdata[15]_i_4/O net (fo=1, routed) 0.955 7.577 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 SLICE_X49Y135 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/I4 SLICE_X49Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.701 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O net (fo=1, routed) 0.000 7.701 u_confreg/u_int_ctrl_n_16 SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X49Y135 FDRE r u_confreg/s_rdata_reg[15]/C Slack: inf Source: dip_sw[7] (input port) Destination: u_confreg/s_rdata_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.567ns (logic 1.719ns (22.721%) route 5.848ns (77.279%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.286ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N6 0.000 0.000 r dip_sw[7] (IN) net (fo=0) 0.000 0.000 dip_sw[7] N6 r dip_sw_IBUF[7]_inst/I N6 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[7]_inst/O net (fo=1, routed) 4.586 6.058 u_confreg/dip_sw_IBUF[7] SLICE_X66Y139 r u_confreg/s_rdata[7]_i_4/I4 SLICE_X66Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.182 r u_confreg/s_rdata[7]_i_4/O net (fo=1, routed) 1.261 7.443 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 SLICE_X56Y131 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/I4 SLICE_X56Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.567 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O net (fo=1, routed) 0.000 7.567 u_confreg/u_int_ctrl_n_24 SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[7]/C Slack: inf Source: dip_sw[12] (input port) Destination: u_confreg/s_rdata_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.550ns (logic 1.717ns (22.743%) route 5.833ns (77.257%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M5 0.000 0.000 r dip_sw[12] (IN) net (fo=0) 0.000 0.000 dip_sw[12] M5 r dip_sw_IBUF[12]_inst/I M5 IBUF (Prop_ibuf_I_O) 1.469 1.469 r dip_sw_IBUF[12]_inst/O net (fo=1, routed) 4.809 6.278 u_confreg/dip_sw_IBUF[12] SLICE_X59Y137 r u_confreg/s_rdata[12]_i_4/I4 SLICE_X59Y137 LUT5 (Prop_lut5_I4_O) 0.124 6.402 r u_confreg/s_rdata[12]_i_4/O net (fo=1, routed) 1.024 7.426 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 SLICE_X48Y135 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/I4 SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.550 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O net (fo=1, routed) 0.000 7.550 u_confreg/u_int_ctrl_n_19 SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[12]/C Slack: inf Source: dip_sw[16] (input port) Destination: u_confreg/s_rdata_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.532ns (logic 1.748ns (23.209%) route 5.784ns (76.791%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.279ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K2 0.000 0.000 r dip_sw[16] (IN) net (fo=0) 0.000 0.000 dip_sw[16] K2 r dip_sw_IBUF[16]_inst/I K2 IBUF (Prop_ibuf_I_O) 1.500 1.500 r dip_sw_IBUF[16]_inst/O net (fo=1, routed) 4.874 6.374 u_confreg/dip_sw_IBUF[16] SLICE_X62Y135 r u_confreg/s_rdata[16]_i_4/I4 SLICE_X62Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.498 r u_confreg/s_rdata[16]_i_4/O net (fo=1, routed) 0.910 7.408 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 SLICE_X48Y135 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/I4 SLICE_X48Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.532 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O net (fo=1, routed) 0.000 7.532 u_confreg/u_int_ctrl_n_15 SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.549 -2.279 u_confreg/sys_clk SLICE_X48Y135 FDRE r u_confreg/s_rdata_reg[16]/C Slack: inf Source: dip_sw[25] (input port) Destination: u_confreg/s_rdata_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.498ns (logic 1.737ns (23.169%) route 5.761ns (76.831%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R3 0.000 0.000 r dip_sw[25] (IN) net (fo=0) 0.000 0.000 dip_sw[25] R3 r dip_sw_IBUF[25]_inst/I R3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[25]_inst/O net (fo=1, routed) 5.036 6.525 u_confreg/dip_sw_IBUF[25] SLICE_X55Y138 r u_confreg/s_rdata[25]_i_4/I4 SLICE_X55Y138 LUT5 (Prop_lut5_I4_O) 0.124 6.649 r u_confreg/s_rdata[25]_i_4/O net (fo=1, routed) 0.725 7.374 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 SLICE_X51Y138 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/I4 SLICE_X51Y138 LUT6 (Prop_lut6_I4_O) 0.124 7.498 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O net (fo=1, routed) 0.000 7.498 u_confreg/u_int_ctrl_n_6 SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[25]/C Slack: inf Source: dip_sw[24] (input port) Destination: u_confreg/s_rdata_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.497ns (logic 1.714ns (22.868%) route 5.783ns (77.132%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.277ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P5 0.000 0.000 r dip_sw[24] (IN) net (fo=0) 0.000 0.000 dip_sw[24] P5 r dip_sw_IBUF[24]_inst/I P5 IBUF (Prop_ibuf_I_O) 1.466 1.466 r dip_sw_IBUF[24]_inst/O net (fo=1, routed) 5.182 6.648 u_confreg/dip_sw_IBUF[24] SLICE_X55Y139 r u_confreg/s_rdata[24]_i_4/I4 SLICE_X55Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.772 r u_confreg/s_rdata[24]_i_4/O net (fo=1, routed) 0.601 7.373 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 SLICE_X52Y139 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/I4 SLICE_X52Y139 LUT6 (Prop_lut6_I4_O) 0.124 7.497 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O net (fo=1, routed) 0.000 7.497 u_confreg/u_int_ctrl_n_7 SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.551 -2.277 u_confreg/sys_clk SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[24]/C Slack: inf Source: dip_sw[4] (input port) Destination: u_confreg/s_rdata_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.485ns (logic 1.736ns (23.197%) route 5.748ns (76.803%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.281ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.281ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P4 0.000 0.000 r dip_sw[4] (IN) net (fo=0) 0.000 0.000 dip_sw[4] P4 r dip_sw_IBUF[4]_inst/I P4 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[4]_inst/O net (fo=1, routed) 4.844 6.332 u_confreg/dip_sw_IBUF[4] SLICE_X63Y134 r u_confreg/s_rdata[4]_i_4/I4 SLICE_X63Y134 LUT5 (Prop_lut5_I4_O) 0.124 6.456 r u_confreg/s_rdata[4]_i_4/O net (fo=1, routed) 0.904 7.361 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 SLICE_X55Y135 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/I4 SLICE_X55Y135 LUT6 (Prop_lut6_I4_O) 0.124 7.485 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O net (fo=1, routed) 0.000 7.485 u_confreg/u_int_ctrl_n_27 SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.547 -2.281 u_confreg/sys_clk SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[4]/C Slack: inf Source: dip_sw[8] (input port) Destination: u_confreg/s_rdata_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.481ns (logic 1.724ns (23.040%) route 5.758ns (76.960%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.286ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M6 0.000 0.000 r dip_sw[8] (IN) net (fo=0) 0.000 0.000 dip_sw[8] M6 r dip_sw_IBUF[8]_inst/I M6 IBUF (Prop_ibuf_I_O) 1.476 1.476 r dip_sw_IBUF[8]_inst/O net (fo=1, routed) 4.998 6.474 u_confreg/dip_sw_IBUF[8] SLICE_X61Y135 r u_confreg/s_rdata[8]_i_4/I4 SLICE_X61Y135 LUT5 (Prop_lut5_I4_O) 0.124 6.598 r u_confreg/s_rdata[8]_i_4/O net (fo=1, routed) 0.760 7.357 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 SLICE_X59Y131 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/I4 SLICE_X59Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.481 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O net (fo=1, routed) 0.000 7.481 u_confreg/u_int_ctrl_n_23 SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk SLICE_X59Y131 FDRE r u_confreg/s_rdata_reg[8]/C Slack: inf Source: dip_sw[20] (input port) Destination: u_confreg/s_rdata_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.437ns (logic 1.723ns (23.170%) route 5.714ns (76.830%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M4 0.000 0.000 r dip_sw[20] (IN) net (fo=0) 0.000 0.000 dip_sw[20] M4 r dip_sw_IBUF[20]_inst/I M4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r dip_sw_IBUF[20]_inst/O net (fo=1, routed) 4.743 6.219 u_confreg/dip_sw_IBUF[20] SLICE_X54Y140 r u_confreg/s_rdata[20]_i_4/I4 SLICE_X54Y140 LUT5 (Prop_lut5_I4_O) 0.124 6.343 r u_confreg/s_rdata[20]_i_4/O net (fo=1, routed) 0.970 7.313 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 SLICE_X50Y138 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/I4 SLICE_X50Y138 LUT6 (Prop_lut6_I4_O) 0.124 7.437 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O net (fo=1, routed) 0.000 7.437 u_confreg/u_int_ctrl_n_11 SLICE_X50Y138 FDRE r u_confreg/s_rdata_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk SLICE_X50Y138 FDRE r u_confreg/s_rdata_reg[20]/C Slack: inf Source: dip_sw[6] (input port) Destination: u_confreg/s_rdata_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.429ns (logic 1.736ns (23.368%) route 5.693ns (76.632%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.284ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L3 0.000 0.000 r dip_sw[6] (IN) net (fo=0) 0.000 0.000 dip_sw[6] L3 r dip_sw_IBUF[6]_inst/I L3 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[6]_inst/O net (fo=1, routed) 4.696 6.184 u_confreg/dip_sw_IBUF[6] SLICE_X65Y134 r u_confreg/s_rdata[6]_i_4/I4 SLICE_X65Y134 LUT5 (Prop_lut5_I4_O) 0.124 6.308 r u_confreg/s_rdata[6]_i_4/O net (fo=1, routed) 0.997 7.305 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 SLICE_X57Y132 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/I4 SLICE_X57Y132 LUT6 (Prop_lut6_I4_O) 0.124 7.429 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O net (fo=1, routed) 0.000 7.429 u_confreg/u_int_ctrl_n_25 SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.544 -2.284 u_confreg/sys_clk SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[6]/C Slack: inf Source: dip_sw[13] (input port) Destination: u_confreg/s_rdata_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.400ns (logic 1.734ns (23.431%) route 5.666ns (76.569%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K3 0.000 0.000 r dip_sw[13] (IN) net (fo=0) 0.000 0.000 dip_sw[13] K3 r dip_sw_IBUF[13]_inst/I K3 IBUF (Prop_ibuf_I_O) 1.486 1.486 r dip_sw_IBUF[13]_inst/O net (fo=1, routed) 5.048 6.534 u_confreg/dip_sw_IBUF[13] SLICE_X58Y139 r u_confreg/s_rdata[13]_i_4/I4 SLICE_X58Y139 LUT5 (Prop_lut5_I4_O) 0.124 6.658 r u_confreg/s_rdata[13]_i_4/O net (fo=1, routed) 0.618 7.276 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 SLICE_X57Y133 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/I4 SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.124 7.400 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O net (fo=1, routed) 0.000 7.400 u_confreg/u_int_ctrl_n_18 SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.545 -2.283 u_confreg/sys_clk SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[13]/C Slack: inf Source: dip_sw[21] (input port) Destination: u_confreg/s_rdata_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.324ns (logic 1.736ns (23.706%) route 5.588ns (76.294%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.278ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N2 0.000 0.000 r dip_sw[21] (IN) net (fo=0) 0.000 0.000 dip_sw[21] N2 r dip_sw_IBUF[21]_inst/I N2 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[21]_inst/O net (fo=1, routed) 5.103 6.592 u_confreg/dip_sw_IBUF[21] SLICE_X57Y138 r u_confreg/s_rdata[21]_i_4/I4 SLICE_X57Y138 LUT5 (Prop_lut5_I4_O) 0.124 6.716 r u_confreg/s_rdata[21]_i_4/O net (fo=1, routed) 0.484 7.200 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 SLICE_X51Y138 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/I4 SLICE_X51Y138 LUT6 (Prop_lut6_I4_O) 0.124 7.324 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O net (fo=1, routed) 0.000 7.324 u_confreg/u_int_ctrl_n_10 SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.550 -2.278 u_confreg/sys_clk SLICE_X51Y138 FDRE r u_confreg/s_rdata_reg[21]/C Slack: inf Source: dip_sw[2] (input port) Destination: u_confreg/s_rdata_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.267ns (logic 1.743ns (23.989%) route 5.524ns (76.011%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.286ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.286ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M2 0.000 0.000 r dip_sw[2] (IN) net (fo=0) 0.000 0.000 dip_sw[2] M2 r dip_sw_IBUF[2]_inst/I M2 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[2]_inst/O net (fo=1, routed) 4.493 5.988 u_confreg/dip_sw_IBUF[2] SLICE_X66Y131 r u_confreg/s_rdata[2]_i_4/I4 SLICE_X66Y131 LUT5 (Prop_lut5_I4_O) 0.124 6.112 r u_confreg/s_rdata[2]_i_4/O net (fo=1, routed) 1.030 7.143 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 SLICE_X56Y131 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/I4 SLICE_X56Y131 LUT6 (Prop_lut6_I4_O) 0.124 7.267 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O net (fo=1, routed) 0.000 7.267 u_confreg/u_int_ctrl_n_29 SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.542 -2.286 u_confreg/sys_clk SLICE_X56Y131 FDRE r u_confreg/s_rdata_reg[2]/C Slack: inf Source: dip_sw[0] (input port) Destination: u_confreg/s_rdata_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.201ns (logic 1.743ns (24.206%) route 5.458ns (75.794%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.283ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T3 0.000 0.000 r dip_sw[0] (IN) net (fo=0) 0.000 0.000 dip_sw[0] T3 r dip_sw_IBUF[0]_inst/I T3 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[0]_inst/O net (fo=1, routed) 4.700 6.196 u_confreg/dip_sw_IBUF[0] SLICE_X62Y133 r u_confreg/s_rdata[0]_i_4/I4 SLICE_X62Y133 LUT5 (Prop_lut5_I4_O) 0.124 6.320 r u_confreg/s_rdata[0]_i_4/O net (fo=1, routed) 0.758 7.077 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 SLICE_X60Y133 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/I4 SLICE_X60Y133 LUT6 (Prop_lut6_I4_O) 0.124 7.201 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O net (fo=1, routed) 0.000 7.201 u_confreg/u_int_ctrl_n_31 SLICE_X60Y133 FDRE r u_confreg/s_rdata_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 1.545 -2.283 u_confreg/sys_clk SLICE_X60Y133 FDRE r u_confreg/s_rdata_reg[0]/C Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED (internal pin) Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Removal (Min at Fast Process Corner) Data Path Delay: 1.811ns (logic 0.045ns (2.485%) route 1.766ns (97.515%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED net (fo=1, routed) 1.592 1.592 pll_clk.u_rst_sys/locked SLICE_X22Y139 r pll_clk.u_rst_sys/delay[1]_i_1/I0 SLICE_X22Y139 LUT1 (Prop_lut1_I0_O) 0.045 1.637 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 0.174 1.811 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X22Y139 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.896 -0.412 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED (internal pin) Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Removal (Min at Fast Process Corner) Data Path Delay: 1.811ns (logic 0.045ns (2.485%) route 1.766ns (97.515%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.264ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.192ns Phase Error (PE): 0.165ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED net (fo=1, routed) 1.592 1.592 pll_clk.u_rst_sys/locked SLICE_X22Y139 r pll_clk.u_rst_sys/delay[1]_i_1/I0 SLICE_X22Y139 LUT1 (Prop_lut1_I0_O) 0.045 1.637 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 0.174 1.811 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X22Y139 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.896 -0.412 pll_clk.u_rst_sys/sys_clk SLICE_X22Y139 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C Slack: inf Source: dip_sw[31] (input port) Destination: u_confreg/s_rdata_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.161ns (logic 0.351ns (16.258%) route 1.810ns (83.742%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.454ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.454ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R2 0.000 0.000 r dip_sw[31] (IN) net (fo=0) 0.000 0.000 dip_sw[31] R2 r dip_sw_IBUF[31]_inst/I R2 IBUF (Prop_ibuf_I_O) 0.261 0.261 r dip_sw_IBUF[31]_inst/O net (fo=1, routed) 1.699 1.960 u_confreg/dip_sw_IBUF[31] SLICE_X59Y137 r u_confreg/s_rdata[31]_i_6/I4 SLICE_X59Y137 LUT5 (Prop_lut5_I4_O) 0.045 2.005 r u_confreg/s_rdata[31]_i_6/O net (fo=1, routed) 0.111 2.116 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 SLICE_X57Y137 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/I4 SLICE_X57Y137 LUT6 (Prop_lut6_I4_O) 0.045 2.161 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O net (fo=1, routed) 0.000 2.161 u_confreg/u_int_ctrl_n_0 SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[31]/C Slack: inf Source: dip_sw[23] (input port) Destination: u_confreg/s_rdata_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.220ns (logic 0.376ns (16.930%) route 1.845ns (83.070%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.452ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N1 0.000 0.000 r dip_sw[23] (IN) net (fo=0) 0.000 0.000 dip_sw[23] N1 r dip_sw_IBUF[23]_inst/I N1 IBUF (Prop_ibuf_I_O) 0.286 0.286 r dip_sw_IBUF[23]_inst/O net (fo=1, routed) 1.603 1.889 u_confreg/dip_sw_IBUF[23] SLICE_X51Y139 r u_confreg/s_rdata[23]_i_4/I4 SLICE_X51Y139 LUT5 (Prop_lut5_I4_O) 0.045 1.934 r u_confreg/s_rdata[23]_i_4/O net (fo=1, routed) 0.241 2.175 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 SLICE_X50Y139 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/I4 SLICE_X50Y139 LUT6 (Prop_lut6_I4_O) 0.045 2.220 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O net (fo=1, routed) 0.000 2.220 u_confreg/u_int_ctrl_n_8 SLICE_X50Y139 FDRE r u_confreg/s_rdata_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk SLICE_X50Y139 FDRE r u_confreg/s_rdata_reg[23]/C Slack: inf Source: touch_btn[1] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.242ns (logic 0.283ns (12.603%) route 1.959ns (87.397%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.465ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.465ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M1 0.000 0.000 r touch_btn[1] (IN) net (fo=0) 0.000 0.000 touch_btn[1] M1 r touch_btn_IBUF[1]_inst/I M1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r touch_btn_IBUF[1]_inst/O net (fo=1, routed) 1.959 2.242 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.843 -0.465 u_confreg/u_int_ctrl/sys_clk SLICE_X70Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.295ns (logic 0.287ns (12.514%) route 2.008ns (87.486%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -0.466ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.466ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 f UART_TX_IOBUF_inst/IBUF/I H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 2.008 2.250 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF SLICE_X77Y137 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/I2 SLICE_X77Y137 LUT5 (Prop_lut5_I2_O) 0.045 2.295 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O net (fo=1, routed) 0.000 2.295 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 SLICE_X77Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.842 -0.466 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X77Y137 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C Slack: inf Source: dip_sw[28] (input port) Destination: u_confreg/s_rdata_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.315ns (logic 0.326ns (14.065%) route 1.989ns (85.935%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.452ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.452ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R5 0.000 0.000 r dip_sw[28] (IN) net (fo=0) 0.000 0.000 dip_sw[28] R5 r dip_sw_IBUF[28]_inst/I R5 IBUF (Prop_ibuf_I_O) 0.236 0.236 r dip_sw_IBUF[28]_inst/O net (fo=1, routed) 1.643 1.878 u_confreg/dip_sw_IBUF[28] SLICE_X59Y139 r u_confreg/s_rdata[28]_i_4/I4 SLICE_X59Y139 LUT5 (Prop_lut5_I4_O) 0.045 1.923 r u_confreg/s_rdata[28]_i_4/O net (fo=1, routed) 0.346 2.270 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 SLICE_X52Y139 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/I4 SLICE_X52Y139 LUT6 (Prop_lut6_I4_O) 0.045 2.315 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O net (fo=1, routed) 0.000 2.315 u_confreg/u_int_ctrl_n_3 SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.856 -0.452 u_confreg/sys_clk SLICE_X52Y139 FDRE r u_confreg/s_rdata_reg[28]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.347ns (logic 0.287ns (12.237%) route 2.060ns (87.763%)) Logic Levels: 2 (IBUF=1 LUT4=1) Clock Path Skew: -0.466ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.466ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 r UART_TX_IOBUF_inst/IBUF/I H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 2.060 2.302 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_TX_IBUF SLICE_X77Y137 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/I2 SLICE_X77Y137 LUT4 (Prop_lut4_I2_O) 0.045 2.347 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O net (fo=1, routed) 0.000 2.347 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i SLICE_X77Y137 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.842 -0.466 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk SLICE_X77Y137 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C Slack: inf Source: dip_sw[17] (input port) Destination: u_confreg/s_rdata_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.367ns (logic 0.362ns (15.281%) route 2.005ns (84.719%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.455ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.455ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K1 0.000 0.000 r dip_sw[17] (IN) net (fo=0) 0.000 0.000 dip_sw[17] K1 r dip_sw_IBUF[17]_inst/I K1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[17]_inst/O net (fo=1, routed) 1.744 2.015 u_confreg/dip_sw_IBUF[17] SLICE_X56Y136 r u_confreg/s_rdata[17]_i_4/I4 SLICE_X56Y136 LUT5 (Prop_lut5_I4_O) 0.045 2.060 r u_confreg/s_rdata[17]_i_4/O net (fo=1, routed) 0.262 2.322 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 SLICE_X49Y136 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/I4 SLICE_X49Y136 LUT6 (Prop_lut6_I4_O) 0.045 2.367 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O net (fo=1, routed) 0.000 2.367 u_confreg/u_int_ctrl_n_14 SLICE_X49Y136 FDRE r u_confreg/s_rdata_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk SLICE_X49Y136 FDRE r u_confreg/s_rdata_reg[17]/C Slack: inf Source: touch_btn[2] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.371ns (logic 0.255ns (10.737%) route 2.117ns (89.263%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.462ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.462ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P3 0.000 0.000 r touch_btn[2] (IN) net (fo=0) 0.000 0.000 touch_btn[2] P3 r touch_btn_IBUF[2]_inst/I P3 IBUF (Prop_ibuf_I_O) 0.255 0.255 r touch_btn_IBUF[2]_inst/O net (fo=1, routed) 2.117 2.371 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.846 -0.462 u_confreg/u_int_ctrl/sys_clk SLICE_X65Y133 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C Slack: inf Source: dip_sw[11] (input port) Destination: u_confreg/s_rdata_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.379ns (logic 0.329ns (13.836%) route 2.050ns (86.164%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.457ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L7 0.000 0.000 r dip_sw[11] (IN) net (fo=0) 0.000 0.000 dip_sw[11] L7 r dip_sw_IBUF[11]_inst/I L7 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[11]_inst/O net (fo=1, routed) 1.819 2.059 u_confreg/dip_sw_IBUF[11] SLICE_X60Y139 r u_confreg/s_rdata[11]_i_4/I4 SLICE_X60Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.104 r u_confreg/s_rdata[11]_i_4/O net (fo=1, routed) 0.230 2.334 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 SLICE_X57Y133 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/I4 SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.045 2.379 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O net (fo=1, routed) 0.000 2.379 u_confreg/u_int_ctrl_n_20 SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.851 -0.457 u_confreg/sys_clk SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[11]/C Slack: inf Source: dip_sw[9] (input port) Destination: u_confreg/s_rdata_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.511ns (logic 0.328ns (13.048%) route 2.184ns (86.952%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.458ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N7 0.000 0.000 r dip_sw[9] (IN) net (fo=0) 0.000 0.000 dip_sw[9] N7 r dip_sw_IBUF[9]_inst/I N7 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[9]_inst/O net (fo=1, routed) 1.929 2.167 u_confreg/dip_sw_IBUF[9] SLICE_X58Y135 r u_confreg/s_rdata[9]_i_4/I4 SLICE_X58Y135 LUT5 (Prop_lut5_I4_O) 0.045 2.212 r u_confreg/s_rdata[9]_i_4/O net (fo=1, routed) 0.254 2.466 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 SLICE_X57Y132 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/I4 SLICE_X57Y132 LUT6 (Prop_lut6_I4_O) 0.045 2.511 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O net (fo=1, routed) 0.000 2.511 u_confreg/u_int_ctrl_n_22 SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.850 -0.458 u_confreg/sys_clk SLICE_X57Y132 FDRE r u_confreg/s_rdata_reg[9]/C Slack: inf Source: dip_sw[30] (input port) Destination: u_confreg/s_rdata_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.573ns (logic 0.317ns (12.327%) route 2.256ns (87.673%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.451ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.451ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R6 0.000 0.000 r dip_sw[30] (IN) net (fo=0) 0.000 0.000 dip_sw[30] R6 r dip_sw_IBUF[30]_inst/I R6 IBUF (Prop_ibuf_I_O) 0.227 0.227 r dip_sw_IBUF[30]_inst/O net (fo=1, routed) 2.205 2.432 u_confreg/dip_sw_IBUF[30] SLICE_X57Y140 r u_confreg/s_rdata[30]_i_4/I4 SLICE_X57Y140 LUT5 (Prop_lut5_I4_O) 0.045 2.477 r u_confreg/s_rdata[30]_i_4/O net (fo=1, routed) 0.050 2.528 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 SLICE_X57Y140 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/I4 SLICE_X57Y140 LUT6 (Prop_lut6_I4_O) 0.045 2.573 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O net (fo=1, routed) 0.000 2.573 u_confreg/u_int_ctrl_n_1 SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.857 -0.451 u_confreg/sys_clk SLICE_X57Y140 FDRE r u_confreg/s_rdata_reg[30]/C Slack: inf Source: dip_sw[26] (input port) Destination: u_confreg/s_rdata_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.588ns (logic 0.367ns (14.175%) route 2.221ns (85.825%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.454ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.454ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T4 0.000 0.000 r dip_sw[26] (IN) net (fo=0) 0.000 0.000 dip_sw[26] T4 r dip_sw_IBUF[26]_inst/I T4 IBUF (Prop_ibuf_I_O) 0.277 0.277 r dip_sw_IBUF[26]_inst/O net (fo=1, routed) 1.957 2.234 u_confreg/dip_sw_IBUF[26] SLICE_X52Y137 r u_confreg/s_rdata[26]_i_4/I4 SLICE_X52Y137 LUT5 (Prop_lut5_I4_O) 0.045 2.279 r u_confreg/s_rdata[26]_i_4/O net (fo=1, routed) 0.264 2.543 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 SLICE_X50Y137 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/I4 SLICE_X50Y137 LUT6 (Prop_lut6_I4_O) 0.045 2.588 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O net (fo=1, routed) 0.000 2.588 u_confreg/u_int_ctrl_n_5 SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk SLICE_X50Y137 FDRE r u_confreg/s_rdata_reg[26]/C Slack: inf Source: touch_btn[0] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.605ns (logic 0.267ns (10.235%) route 2.338ns (89.765%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.460ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.460ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T2 0.000 0.000 r touch_btn[0] (IN) net (fo=0) 0.000 0.000 touch_btn[0] T2 r touch_btn_IBUF[0]_inst/I T2 IBUF (Prop_ibuf_I_O) 0.267 0.267 r touch_btn_IBUF[0]_inst/O net (fo=1, routed) 2.338 2.605 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] SLICE_X60Y132 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.848 -0.460 u_confreg/u_int_ctrl/sys_clk SLICE_X60Y132 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C Slack: inf Source: dip_sw[10] (input port) Destination: u_confreg/s_rdata_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.611ns (logic 0.330ns (12.645%) route 2.281ns (87.355%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.455ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.455ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M7 0.000 0.000 r dip_sw[10] (IN) net (fo=0) 0.000 0.000 dip_sw[10] M7 r dip_sw_IBUF[10]_inst/I M7 IBUF (Prop_ibuf_I_O) 0.240 0.240 r dip_sw_IBUF[10]_inst/O net (fo=1, routed) 1.737 1.977 u_confreg/dip_sw_IBUF[10] SLICE_X62Y139 r u_confreg/s_rdata[10]_i_4/I4 SLICE_X62Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.022 r u_confreg/s_rdata[10]_i_4/O net (fo=1, routed) 0.543 2.566 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 SLICE_X55Y135 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/I4 SLICE_X55Y135 LUT6 (Prop_lut6_I4_O) 0.045 2.611 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O net (fo=1, routed) 0.000 2.611 u_confreg/u_int_ctrl_n_21 SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.853 -0.455 u_confreg/sys_clk SLICE_X55Y135 FDRE r u_confreg/s_rdata_reg[10]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.615ns (logic 0.287ns (10.986%) route 2.328ns (89.014%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -0.474ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.474ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 r UART_TX_IOBUF_inst/IBUF/I H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 2.328 2.570 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X79Y136 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/I0 SLICE_X79Y136 LUT5 (Prop_lut5_I0_O) 0.045 2.615 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O net (fo=1, routed) 0.000 2.615 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.834 -0.474 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X79Y136 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C Slack: inf Source: touch_btn[3] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.660ns (logic 0.280ns (10.536%) route 2.380ns (89.464%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.461ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.461ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- U2 0.000 0.000 r touch_btn[3] (IN) net (fo=0) 0.000 0.000 touch_btn[3] U2 r touch_btn_IBUF[3]_inst/I U2 IBUF (Prop_ibuf_I_O) 0.280 0.280 r touch_btn_IBUF[3]_inst/O net (fo=1, routed) 2.380 2.660 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] SLICE_X60Y131 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.847 -0.461 u_confreg/u_int_ctrl/sys_clk SLICE_X60Y131 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C Slack: inf Source: dip_sw[1] (input port) Destination: u_confreg/s_rdata_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.718ns (logic 0.355ns (13.080%) route 2.362ns (86.920%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.457ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J3 0.000 0.000 r dip_sw[1] (IN) net (fo=0) 0.000 0.000 dip_sw[1] J3 r dip_sw_IBUF[1]_inst/I J3 IBUF (Prop_ibuf_I_O) 0.265 0.265 r dip_sw_IBUF[1]_inst/O net (fo=1, routed) 1.935 2.201 u_confreg/dip_sw_IBUF[1] SLICE_X66Y141 r u_confreg/s_rdata[1]_i_4/I4 SLICE_X66Y141 LUT5 (Prop_lut5_I4_O) 0.045 2.246 r u_confreg/s_rdata[1]_i_4/O net (fo=1, routed) 0.427 2.673 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 SLICE_X57Y133 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/I4 SLICE_X57Y133 LUT6 (Prop_lut6_I4_O) 0.045 2.718 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O net (fo=1, routed) 0.000 2.718 u_confreg/u_int_ctrl_n_30 SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.851 -0.457 u_confreg/sys_clk SLICE_X57Y133 FDRE r u_confreg/s_rdata_reg[1]/C Slack: inf Source: dip_sw[5] (input port) Destination: u_confreg/s_rdata_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 2.769ns (logic 0.328ns (11.858%) route 2.441ns (88.142%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -0.454ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.454ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L5 0.000 0.000 r dip_sw[5] (IN) net (fo=0) 0.000 0.000 dip_sw[5] L5 r dip_sw_IBUF[5]_inst/I L5 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[5]_inst/O net (fo=1, routed) 2.069 2.307 u_confreg/dip_sw_IBUF[5] SLICE_X66Y139 r u_confreg/s_rdata[5]_i_4/I4 SLICE_X66Y139 LUT5 (Prop_lut5_I4_O) 0.045 2.352 r u_confreg/s_rdata[5]_i_4/O net (fo=1, routed) 0.372 2.724 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 SLICE_X57Y137 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/I4 SLICE_X57Y137 LUT6 (Prop_lut6_I4_O) 0.045 2.769 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O net (fo=1, routed) 0.000 2.769 u_confreg/u_int_ctrl_n_26 SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 r pll_clk.u_clk_pll/inst/clkout2_buf/I BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9971, routed) 0.854 -0.454 u_confreg/sys_clk SLICE_X57Y137 FDRE r u_confreg/s_rdata_reg[5]/C