Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
| Date         : Wed Jul  8 03:34:29 2026
| Host         : fedora running 64-bit unknown
| Command      : report_design_analysis -timing -file /home/fallensigh/vivado_reports_nodsp/design_analysis_timing.rpt
| Design       : soc_top
| Device       : xc7a200t
| Design State : Routed
-----------------------------------------------------------------------------------------------------------------------

Report Design Analysis

Table of Contents
-----------------
1. Setup Path Characteristics 1-1

1. Setup Path Characteristics 1-1
---------------------------------

+---------------------------+------------------------------------------------------+
|      Characteristics      |                        Path #1                       |
+---------------------------+------------------------------------------------------+
| Requirement               |                                               20.000 |
| Path Delay                |                                               15.605 |
| Logic Delay               | 5.343(35%)                                           |
| Net Delay                 | 10.263(65%)                                          |
| Clock Skew                |                                               -3.858 |
| Slack                     |                                                0.167 |
| Clock Relationship        | Safely Timed                                         |
| Logic Levels              |                                                    9 |
| Routes                    |                                                    9 |
| Logical Path              | FDRE LUT4 LUT6 LUT5 LUT6 RAMD32 LUT6 LUT5 LUT3 OBUFT |
| Start Point Clock         | sys_clk                                              |
| End Point Clock           | sys_clk                                              |
| DSP Block                 | None                                                 |
| BRAM                      | None                                                 |
| IO Crossings              |                                                    3 |
| Config Crossings          |                                                    0 |
| SLR Crossings             |                                                    0 |
| PBlocks                   |                                                    0 |
| High Fanout               |                                                  130 |
| Dont Touch                |                                                    0 |
| Mark Debug                |                                                    0 |
| Start Point Pin Primitive | FDRE/C                                               |
| End Point Pin Primitive   | ext_ram_data[18]                                     |
| Start Point Pin           | FSM_sequential_ext_wr_state_reg[1]/C                 |
| End Point Pin             | ext_ram_data[18]                                     |
+---------------------------+------------------------------------------------------+
* Bounding box calculated as % of dimensions for the target device (436, 500)