#pragma once

typedef unsigned int u32;

typedef struct {
    volatile u32 SRC_ADDR;  // 0x00: source address
    volatile u32 DST_ADDR;  // 0x04: destination address
    volatile u32 LENGTH;    // 0x08: transfer byte count
    volatile u32 TAG;       // 0x0C: software tag (ignored by HW)
    volatile u32 CTRL;      // 0x10: control (burst config + start)
    volatile u32 STATUS;    // 0x14: status (busy, done)
    volatile u32 MODE;      // 0x18: 0=mem2mem, 1=mem2ep, 2=ep2mem
    volatile u32 EP_CFG;    // 0x1C: [3:0]=bank, [15:8]=word offset, [19:16]=endpoint id
    volatile u32 RESV[8];   // 0x20 ~ 0x3C: padding to 0x40 bytes
} dma_ch_regs_t;

// DMA 控制器基地址
#define CDMA_MUX_BASE 0xbf300000
#define DMA_CH(i)     ((volatile dma_ch_regs_t*)(CDMA_MUX_BASE + (i) * 0x40))

typedef struct {
    volatile u32 CTRL;       // 0x200: bit0 start
    volatile u32 STATUS;     // 0x204: bit0 busy, bit1 done (W1C)
    volatile u32 SRC_BASE;   // 0x208
    volatile u32 DST_BASE;   // 0x20C
    volatile u32 GROUPS;     // 0x210
    volatile u32 MAT_BASE;   // 0x214: reserved for compatibility
    volatile u32 SRC_STRIDE; // 0x218
    volatile u32 DST_STRIDE; // 0x21C
} dma_seq_regs_t;

#define DMA_SEQ ((volatile dma_seq_regs_t*)(CDMA_MUX_BASE + 0x200))

// CTRL 寄存器位定义
#define CTRL_START_BIT       (1 << 0)
#define CTRL_BURST_SIZE(x)   (((x) & 0x7) << 3)  // Bits [5:3]: AXI AxSIZE (0=1B, 1=2B, 2=4B, 3=8B)
#define CTRL_BURST_LEN(x)    (((x) & 0xFF) << 6) // Bits [13:6]: AXI AxLEN (0=1 beat, 15=16 beats)

#define DMA_MODE_MEM2MEM     0
#define DMA_MODE_MEM2EP      1
#define DMA_MODE_EP2MEM      2
#define DMA_EP_CFG(id, bank, word_off) \
    ((((id) & 0xF) << 16) | (((word_off) & 0xFF) << 8) | ((bank) & 0xF))

// STATUS 寄存器位定义
#define STATUS_BUSY_BIT      (1 << 0)
#define STATUS_DONE_BIT      (1 << 1)

#define SEQ_START_BIT        (1 << 0)
#define SEQ_BUSY_BIT         (1 << 0)
#define SEQ_DONE_BIT         (1 << 1)

void dma_start_transfer(int ch_id, u32 src, u32 dst, u32 bytes, u32 tag);
void dma_wait_polling(int ch_id);