Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 | Date : Wed Jul 15 05:09:36 2026 | Host : Roc_Wang running 64-bit major release (build 9200) | Command : report_cdc -details -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/cdc.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ------------------------------------------------------------------------------------------------------------------------ CDC Report ID Severity Count Description ------ -------- ----- ------------------------------------------------------- CDC-3 Info 1 1-bit synchronized with ASYNC_REG property CDC-6 Warning 20 Multi-bit synchronized with ASYNC_REG property CDC-7 Critical 1 Asynchronous reset unknown CDC circuitry CDC-9 Info 3 Asynchronous reset synchronized with ASYNC_REG property CDC-11 Critical 2 Fan-out from launch flop to destination clock CDC-15 Warning 313 Clock enable controlled CDC structure detected Source Clock: sys_clk Destination Clock: cpu_clk CDC Type: User Ignored Row ID Severity Description Depth Exception Source (From) Destination (To) --- ------ -------- ---------------------------------------------- ----- ------------------- ---------------------------------------------- ------------------------------------------------------------ 1 CDC-11 Critical Fan-out from launch flop to destination clock 2 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C pll_clk.u_rst_cpu/delay_reg[0]/CLR 2 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2:0]/C u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D 3 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2:0]/C u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D 4 CDC-11 Critical Fan-out from launch flop to destination clock 2 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR 5 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2:0]/C u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D 6 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D 7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D 8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D 10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D 11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D 12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D 13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D 14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D 15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D 16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D 17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D 18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D 19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D 20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D 21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D 22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D 23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D 24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D 25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D 26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D 27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D 28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D 29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D 30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D 31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D 32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D 33 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D 34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D 35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D 36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D 37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D 38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D 39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D 40 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3:0]/C u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D 41 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3:0]/C u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D 42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_confreg/int_out_or_q2_reg/C u_cpu/u_csr/csr_estat_reg[2]/D 43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_cdma_matmul_bridge/seq_done_flag_reg/C u_cpu/u_csr/csr_estat_reg[3]/D 44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_matmul_axi_slave/done_reg/C u_cpu/u_csr/csr_estat_reg[4]/D 45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C u_cpu/u_csr/csr_estat_reg[5]/D Source Clock: sys_clk Destination Clock: mlkem_clk CDC Type: User Ignored Row ID Severity Description Depth Exception Source (From) Destination (To) --- ------ -------- ------------------------------------------------------- ----- ------------------- -------------------------------------------------------------------------- ---------------------------------------------------------------------------------------- 1 CDC-7 Critical Asynchronous reset unknown CDC circuitry 0 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C pll_clk.u_rst_mlkem/delay_reg[0]/CLR 2 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D 3 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D 4 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D 5 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D 6 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D 7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D 8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D 10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D 11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D 12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D 13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[11]/D 14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D 15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D 16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D 17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D 18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D 19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D 20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D 21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D 22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D 23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D 24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D 25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D 26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D 27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D 28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D 29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D 30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D 31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D 32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D 33 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D 34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D 35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D 36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D 37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D 38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D 39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[5]/D 40 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D 41 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D 42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D 43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D 44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D 45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D 46 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[12]/D 47 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D 48 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D 49 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D 50 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D 51 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D 52 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D 53 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D 54 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D 55 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D 56 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D 57 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 Asynch Clock Groups pll_clk.u_rst_sys/delay_reg[1]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR 58 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D 59 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D 60 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D 61 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D 62 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D 63 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D 64 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/D 65 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D 66 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D 67 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D 68 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D 69 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/D 70 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D 71 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/D 72 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D 73 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D 74 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D 75 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D 76 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D 77 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D 78 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/D 79 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D 80 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D 81 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D 82 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D 83 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D 84 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D 85 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D 86 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D 87 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D 88 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D 89 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D 90 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D 91 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D 92 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D 93 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32]/D 94 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D 95 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D 96 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D 97 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D 98 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D Source Clock: cpu_clk Destination Clock: sys_clk CDC Type: User Ignored Row ID Severity Description Depth Exception Source (From) Destination (To) --- ------ -------- ------------------------------------------------------- ----- ------------------- ---------------------------------------------- ------------------------------------------------------------ 1 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D 2 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[1]/D 3 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D 4 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D 5 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D 6 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D 7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D 8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D 10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D 11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D 12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/D 13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D 14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D 15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[14]/D 16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D 17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/D 18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/D 19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D 20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D 21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/D 22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D 23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D 24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D 25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D 26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D 27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/D 28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[27]/D 29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[28]/D 30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D 31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D 32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D 33 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D 34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/D 35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/D 36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D 37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D 38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[38]/D 39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/D 40 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[40]/D 41 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D 42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D 43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[43]/D 44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D 45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D 46 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D 47 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[47]/D 48 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D 49 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D 50 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[50]/D 51 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/D 52 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/D 53 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/D 54 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2:0]/C u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D 55 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D 56 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D 57 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D 58 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D 59 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[4]/D 60 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D 61 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D 62 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D 63 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D 64 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[9]/D 65 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[10]/D 66 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[11]/D 67 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D 68 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D 69 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[14]/D 70 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[15]/D 71 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[16]/D 72 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/D 73 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D 74 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D 75 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[20]/D 76 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D 77 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D 78 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/D 79 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D 80 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D 81 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[26]/D 82 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/D 83 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/D 84 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/D 85 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D 86 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D 87 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D 88 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D 89 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/D 90 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D 91 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D 92 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[38]/D 93 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D 94 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/D 95 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D 96 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D 97 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D 98 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D 99 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D 100 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/D 101 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D 102 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D 103 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D 104 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/D 105 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D 106 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/D 107 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D 108 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 Asynch Clock Groups pll_clk.u_rst_cpu/delay_reg[1]/C u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR 109 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2:0]/C u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D 110 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2:0]/C u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D 111 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3:0]/C u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D 112 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D 113 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D 114 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D 115 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[3]/D 116 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[4]/D 117 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/D 118 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D 119 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D 120 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D 121 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/D 122 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D 123 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[11]/D 124 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D 125 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D 126 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D 127 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[15]/D 128 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D 129 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/D 130 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D 131 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D 132 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[20]/D 133 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/D 134 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D 135 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D 136 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D 137 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D 138 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[26]/D 139 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/D 140 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D 141 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D 142 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D 143 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D 144 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[32]/D 145 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[33]/D 146 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D 147 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/D 148 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D 149 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3:0]/C u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D Source Clock: mlkem_clk Destination Clock: sys_clk CDC Type: User Ignored Row ID Severity Description Depth Exception Source (From) Destination (To) --- ------ -------- ------------------------------------------------------- ----- ------------------- ------------------------------------------------------------------------- ---------------------------------------------------------------------------------------- 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D 2 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D 3 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2:0]/D 4 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D 5 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 Asynch Clock Groups pll_clk.u_rst_mlkem/delay_reg[1]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR 6 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2:0]/D 7 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D 8 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D 10 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D 11 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D 12 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D 13 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D 14 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D 15 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D 16 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D 17 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D 18 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D 19 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D 20 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D 21 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D 22 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D 23 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D 24 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D 25 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D 26 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D 27 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D 28 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D 29 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D 30 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D 31 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D 32 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D 33 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D 34 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D 35 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D 36 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D 37 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D 38 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D 39 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D 40 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D 41 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D 42 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D 43 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D 44 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D 45 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D 46 CDC-15 Warning Clock enable controlled CDC structure detected 0 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D 47 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3:0]/D 48 CDC-6 Warning Multi-bit synchronized with ASYNC_REG property 2 Asynch Clock Groups u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3:0]/C u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3:0]/D