Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
| Date             : Sun Jul  5 23:46:05 2026
| Host             : fedora running 64-bit unknown
| Command          : report_power -file ./vivado_reports_impl/routed_power.rpt
| Design           : soc_top
| Device           : xc7a200tfbg676-1
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 0.918        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 0.777        |
| Device Static (W)        | 0.142        |
| Effective TJA (C/W)      | 1.9          |
| Max Ambient (C)          | 83.3         |
| Junction Temperature (C) | 26.7         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     0.028 |        6 |       --- |             --- |
| Slice Logic              |     0.200 |   137329 |       --- |             --- |
|   LUT as Logic           |     0.193 |    79570 |    133800 |           59.47 |
|   CARRY4                 |     0.003 |     3590 |     33450 |           10.73 |
|   Register               |     0.002 |    38619 |    267600 |           14.43 |
|   LUT as Distributed RAM |     0.001 |      628 |     46200 |            1.36 |
|   LUT as Shift Register  |    <0.001 |     1094 |     46200 |            2.37 |
|   F7/F8 Muxes            |    <0.001 |     5664 |    133800 |            4.23 |
|   BUFG                   |    <0.001 |        2 |        32 |            6.25 |
|   Others                 |     0.000 |      302 |       --- |             --- |
| Signals                  |     0.368 |    99001 |       --- |             --- |
| Block RAM                |     0.016 |     25.5 |       365 |            6.99 |
| PLL                      |     0.137 |        1 |        10 |           10.00 |
| I/O                      |     0.028 |      202 |       400 |           50.50 |
| Static Power             |     0.142 |          |           |                 |
| Total                    |     0.918 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     0.657 |       0.624 |      0.033 |
| Vccaux    |       1.800 |     0.101 |       0.070 |      0.031 |
| Vcco33    |       3.300 |     0.013 |       0.008 |      0.005 |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.002 |       0.001 |      0.001 |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                             |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                                    |
| Clock nodes activity        | Low        | User specified less than 75% of clocks                 | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view           |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views         |
| Device models               | High       | Device models are Production                           |                                                                                                                    |
|                             |            |                                                        |                                                                                                                    |
| Overall confidence level    | Low        |                                                        |                                                                                                                    |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 1.9                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 3.4                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+------------------+-----------------------------------------+-----------------+
| Clock            | Domain                                  | Constraint (ns) |
+------------------+-----------------------------------------+-----------------+
| clk              | clk                                     |            20.0 |
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll |            20.0 |
| cpu_clk          | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll  |            30.3 |
| sys_clk          | pll_clk.u_clk_pll/inst/sys_clk_clk_pll  |            20.0 |
+------------------+-----------------------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+------------------------------+-----------+
| Name                         | Power (W) |
+------------------------------+-----------+
| soc_top                      |     0.777 |
|   pll_clk.u_clk_pll          |     0.138 |
|     inst                     |     0.138 |
|   u_Axi_CDC                  |     0.003 |
|   u_axi_axil_adapter         |     0.002 |
|     axi_axil_adapter_wr_inst |     0.001 |
|   u_axi_uart_controller      |     0.002 |
|     uart0                    |     0.001 |
|       regs                   |     0.001 |
|   u_cdma_matmul_bridge       |     0.001 |
|   u_confreg                  |     0.001 |
|   u_cpu                      |     0.027 |
|     addr_trans               |     0.002 |
|       tlb_entry              |     0.002 |
|     btb                      |     0.003 |
|     dcache                   |     0.004 |
|     icache                   |     0.005 |
|     u_csr                    |     0.001 |
|     u_mul                    |     0.007 |
|     wb_stage                 |     0.001 |
|   u_fft_mlkem_axi_slave      |     0.467 |
|     u_fft_controller         |     0.027 |
|       u_FFT                  |     0.024 |
|       u_out0                 |     0.001 |
|       u_out1                 |     0.001 |
|     u_mlkem_axi_slave        |     0.436 |
|       u_mlkem                |     0.411 |
|     u_prng_axi_slave         |     0.004 |
|   u_matmul_axi_slave         |     0.081 |
|     mult_inst[0].u_mult      |     0.003 |
|     mult_inst[1].u_mult      |     0.003 |
|     mult_inst[2].u_mult      |     0.003 |
|     mult_inst[3].u_mult      |     0.003 |
|   u_snix_axil_cdma_mux_8ch   |     0.011 |
|     u_core_engine            |     0.006 |
|       axis_fifo_u0           |     0.005 |
+------------------------------+-----------+