Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 | Date : Sun Jul 5 23:34:34 2026 | Host : fedora running 64-bit unknown | Command : report_timing_summary -file ./vivado_reports/synth_timing_summary.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 --------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 23490 register/latch pins with no clock driven by root clock pin: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg/Q (HIGH) 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 69061 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 38 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 40 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 2.111 0.000 0 43229 0.011 0.000 0 43229 7.000 0.000 0 17485 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk {0.000 10.000} 20.000 50.000 clkfbout_clk_pll {0.000 10.000} 20.000 50.000 cpu_clk {0.000 15.161} 30.323 32.979 sys_clk {0.000 10.000} 20.000 50.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk 7.000 0.000 0 1 clkfbout_clk_pll 17.845 0.000 0 3 cpu_clk 6.897 0.000 0 17197 0.011 0.000 0 17197 13.911 0.000 0 6486 sys_clk 2.111 0.000 0 23819 0.011 0.000 0 23819 8.750 0.000 0 10995 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** cpu_clk cpu_clk 27.780 0.000 0 67 0.676 0.000 0 67 **async_default** sys_clk sys_clk 17.299 0.000 0 2146 0.679 0.000 0 2146 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk To Clock: clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { clk } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_pll To Clock: clkfbout_clk_pll Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_pll Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 20.000 17.845 pll_clk.u_clk_pll/inst/clkf_buf/I Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: cpu_clk To Clock: cpu_clk Setup : 0 Failing Endpoints, Worst Slack 6.897ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 6.897ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[25]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 23.236ns (logic 6.978ns (30.031%) route 16.258ns (69.969%)) Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=5 LUT5=7 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.918ns = ( 27.404 - 30.323 ) Source Clock Delay (SCD): -3.241ns Clock Pessimism Removal (CPR): -0.468ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, unplaced) 0.584 -3.241 u_cpu/addr_trans/cpu_clk FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[25]/C ------------------------------------------------------------------- ------------------- FDRE (Prop_fdre_C_Q) 0.456 -2.785 r u_cpu/addr_trans/data_vaddr_buffer_reg[25]/Q net (fo=65, unplaced) 1.054 -1.731 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[13] LUT6 (Prop_lut6_I0_O) 0.295 -1.436 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_105/O net (fo=1, unplaced) 0.000 -1.436 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_105_n_0 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 -0.886 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_30/CO[3] net (fo=1, unplaced) 0.900 0.014 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_30_n_0 LUT6 (Prop_lut6_I3_O) 0.124 0.138 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_8/O net (fo=4, unplaced) 0.926 1.064 u_cpu/addr_trans/tlb_entry/match1[31] LUT4 (Prop_lut4_I1_O) 0.150 1.214 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, unplaced) 0.460 1.674 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 LUT5 (Prop_lut5_I0_O) 0.118 1.792 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, unplaced) 0.460 2.252 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 LUT6 (Prop_lut6_I0_O) 0.124 2.376 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, unplaced) 0.571 2.947 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] MUXF7 (Prop_muxf7_S_O) 0.296 3.243 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O net (fo=1, unplaced) 0.000 3.243 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 MUXF8 (Prop_muxf8_I0_O) 0.104 3.347 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O net (fo=1, unplaced) 0.717 4.064 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 LUT5 (Prop_lut5_I0_O) 0.319 4.383 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O net (fo=1, unplaced) 0.449 4.832 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 LUT6 (Prop_lut6_I5_O) 0.124 4.956 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, unplaced) 0.449 5.405 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 LUT6 (Prop_lut6_I5_O) 0.124 5.529 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, unplaced) 0.492 6.021 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 LUT6 (Prop_lut6_I3_O) 0.124 6.145 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[4]_i_1__0/O net (fo=6, unplaced) 0.934 7.079 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[16] LUT6 (Prop_lut6_I0_O) 0.124 7.203 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, unplaced) 0.000 7.203 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 7.753 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, unplaced) 0.009 7.762 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 CARRY4 (Prop_carry4_CI_CO[2]) 0.250 8.012 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, unplaced) 0.480 8.492 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] LUT3 (Prop_lut3_I0_O) 0.310 8.802 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, unplaced) 0.520 9.322 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 LUT6 (Prop_lut6_I5_O) 0.124 9.446 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[55]_i_15/O net (fo=3, unplaced) 0.920 10.366 u_cpu/dcache/tagv_ram_way[0].u/_zz_ram_port1_reg[31][22] LUT6 (Prop_lut6_I1_O) 0.124 10.490 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O net (fo=3, unplaced) 0.467 10.957 u_cpu/mem_stage/p_5_in6_in[0] LUT4 (Prop_lut4_I0_O) 0.118 11.075 r u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_6/O net (fo=8, unplaced) 0.487 11.562 u_cpu/u_div/ms_to_ws_bus_r_reg[40] LUT5 (Prop_lut5_I4_O) 0.124 11.686 r u_cpu/u_div/ms_to_ws_bus_r[40]_i_2/O net (fo=1, unplaced) 0.449 12.135 u_cpu/mem_stage/ms_to_ws_bus_r_reg[40] LUT4 (Prop_lut4_I2_O) 0.124 12.259 r u_cpu/mem_stage/ms_to_ws_bus_r[40]_i_1/O net (fo=4, unplaced) 0.473 12.732 u_cpu/id_stage/ms_to_ds_forward_bus[8] LUT5 (Prop_lut5_I2_O) 0.124 12.856 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_20/O net (fo=1, unplaced) 0.000 12.856 u_cpu/id_stage/ds_to_es_bus_r[192]_i_20_n_0 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 13.406 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] net (fo=1, unplaced) 0.000 13.406 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 CARRY4 (Prop_carry4_CI_O[1]) 0.348 13.754 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] net (fo=1, unplaced) 0.611 14.365 u_cpu/id_stage/rd_csr_addr0[12] LUT5 (Prop_lut5_I0_O) 0.332 14.697 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O net (fo=1, unplaced) 0.449 15.146 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 LUT5 (Prop_lut5_I1_O) 0.124 15.270 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, unplaced) 0.467 15.737 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 LUT4 (Prop_lut4_I3_O) 0.124 15.861 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, unplaced) 0.484 16.345 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 LUT6 (Prop_lut6_I5_O) 0.124 16.469 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, unplaced) 0.508 16.977 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 LUT5 (Prop_lut5_I4_O) 0.124 17.101 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_24/O net (fo=20, unplaced) 0.509 17.610 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_10 LUT4 (Prop_lut4_I2_O) 0.124 17.734 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_7/O net (fo=1, unplaced) 1.111 18.845 u_cpu/id_stage/ds_to_es_bus_r[180]_i_7_n_0 LUT6 (Prop_lut6_I0_O) 0.124 18.969 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_2/O net (fo=1, unplaced) 0.902 19.871 u_cpu/id_stage/ds_to_es_bus_r[180]_i_2_n_0 LUT6 (Prop_lut6_I1_O) 0.124 19.995 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O net (fo=1, unplaced) 0.000 19.995 u_cpu/exe_stage/ds_to_es_bus[130] FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.439 32.154 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -6.040 26.114 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, unplaced) 0.760 26.874 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFG (Prop_bufg_I_O) 0.091 26.965 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, unplaced) 0.439 27.404 u_cpu/exe_stage/cpu_clk FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C clock pessimism -0.468 26.936 clock uncertainty -0.074 26.862 FDRE (Setup_fdre_C_D) 0.029 26.891 u_cpu/exe_stage/ds_to_es_bus_r_reg[180] ------------------------------------------------------------------- required time 26.891 arrival time -19.995 ------------------------------------------------------------------- slack 6.897 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.011ns (arrival time - required time) Source: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%)) Logic Levels: 0 Clock Path Skew: 0.145ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.650ns Source Clock Delay (SCD): -0.978ns Clock Pessimism Removal (CPR): 0.183ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, unplaced) 0.085 -0.752 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0[0] FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.183 -0.833 FDCE (Hold_fdce_C_D) 0.070 -0.763 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.763 arrival time -0.752 ------------------------------------------------------------------- slack 0.011 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: cpu_clk Waveform(ns): { 0.000 15.161 } Period(ns): 30.323 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_12_17/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: sys_clk To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 2.111ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.011ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.111ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[18]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 17.702ns (logic 4.444ns (25.105%) route 13.258ns (74.895%)) Logic Levels: 18 (CARRY4=3 LUT2=2 LUT5=5 LUT6=8) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 ) Source Clock Delay (SCD): -3.025ns Clock Pessimism Removal (CPR): -0.468ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C ------------------------------------------------------------------- ------------------- FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1] LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3] net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0 CARRY4 (Prop_carry4_CI_O[1]) 0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1] net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5] LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0 CARRY4 (Prop_carry4_S[1]_O[3]) 0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3] net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4 LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0 LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0 LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3] LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1] LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5] LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7] LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5] LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7] LUT5 (Prop_lut5_I1_O) 0.150 9.989 r u_matmul_axi_slave/crc_reg[30]_i_10/O net (fo=1, unplaced) 1.111 11.100 u_matmul_axi_slave/crc32_word_next0_return0[22] LUT5 (Prop_lut5_I0_O) 0.152 11.252 r u_matmul_axi_slave/crc_reg[30]_i_4/O net (fo=1, unplaced) 0.902 12.154 u_matmul_axi_slave/p_0_in0_in[8] LUT5 (Prop_lut5_I2_O) 0.124 12.278 r u_matmul_axi_slave/crc_reg[30]_i_2/O net (fo=9, unplaced) 1.005 13.283 u_matmul_axi_slave/crc32_word_next1_return1[0] LUT6 (Prop_lut6_I0_O) 0.124 13.407 r u_matmul_axi_slave/crc_reg[28]_i_2/O net (fo=7, unplaced) 1.146 14.553 u_matmul_axi_slave/crc_reg[28]_i_2_n_0 LUT6 (Prop_lut6_I1_O) 0.124 14.677 r u_matmul_axi_slave/crc_reg[18]_i_1/O net (fo=1, unplaced) 0.000 14.677 u_matmul_axi_slave/crc32_word_next1_return[18] FDSE r u_matmul_axi_slave/crc_reg_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk FDSE r u_matmul_axi_slave/crc_reg_reg[18]/C clock pessimism -0.468 16.830 clock uncertainty -0.071 16.759 FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[18] ------------------------------------------------------------------- required time 16.788 arrival time -14.677 ------------------------------------------------------------------- slack 2.111 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.011ns (arrival time - required time) Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.226ns (logic 0.141ns (62.465%) route 0.085ns (37.535%)) Logic Levels: 0 Clock Path Skew: 0.145ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.555ns Source Clock Delay (SCD): -0.882ns Clock Pessimism Removal (CPR): 0.183ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, unplaced) 0.085 -0.657 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0] FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.183 -0.737 FDCE (Hold_fdce_C_D) 0.070 -0.667 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.667 arrival time -0.657 ------------------------------------------------------------------- slack 0.011 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: cpu_clk To Clock: cpu_clk Setup : 0 Failing Endpoints, Worst Slack 27.780ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.676ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 27.780ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 1.915ns (logic 0.751ns (39.217%) route 1.164ns (60.783%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.918ns = ( 27.404 - 30.323 ) Source Clock Delay (SCD): -3.241ns Clock Pessimism Removal (CPR): -0.468ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, unplaced) 0.584 -3.241 pll_clk.u_rst_cpu/cpu_clk FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- FDCE (Prop_fdce_C_Q) 0.456 -2.785 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, unplaced) 0.311 -2.474 pll_clk.u_rst_cpu/cpu_resetn LUT1 (Prop_lut1_I0_O) 0.295 -2.179 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, unplaced) 0.853 -1.326 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.439 32.154 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -6.040 26.114 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, unplaced) 0.760 26.874 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFG (Prop_bufg_I_O) 0.091 26.965 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, unplaced) 0.439 27.404 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.468 26.936 clock uncertainty -0.074 26.862 FDCE (Recov_fdce_C_CLR) -0.409 26.453 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 26.453 arrival time 1.326 ------------------------------------------------------------------- slack 27.780 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.676ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.727ns (logic 0.239ns (32.888%) route 0.488ns (67.112%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.145ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.650ns Source Clock Delay (SCD): -0.978ns Clock Pessimism Removal (CPR): 0.183ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, unplaced) 0.114 -0.978 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- FDCE (Prop_fdce_C_Q) 0.141 -0.837 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, unplaced) 0.131 -0.706 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 LUT1 (Prop_lut1_I0_O) 0.098 -0.608 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, unplaced) 0.357 -0.251 u_Axi_CDC/bFifo/buffers_1_reg FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, unplaced) 0.259 -0.650 u_Axi_CDC/bFifo/cpu_clk FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.183 -0.833 FDCE (Remov_fdce_C_CLR) -0.094 -0.927 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.927 arrival time -0.251 ------------------------------------------------------------------- slack 0.676 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 17.299ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.679ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 17.299ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 2.076ns (logic 0.745ns (35.886%) route 1.331ns (64.114%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 ) Source Clock Delay (SCD): -3.025ns Clock Pessimism Removal (CPR): -0.468ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10994, unplaced) 0.800 -3.025 pll_clk.u_rst_sys/sys_clk FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- FDCE (Prop_fdce_C_Q) 0.456 -2.569 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=119, unplaced) 0.415 -2.154 pll_clk.u_rst_sys/Q[0] LUT1 (Prop_lut1_I0_O) 0.289 -1.865 f pll_clk.u_rst_sys/r_wb[7]_i_4/O net (fo=28767, unplaced) 0.916 -0.949 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/p_0_in FDCE f u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10994, unplaced) 0.655 17.297 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/sys_clk FDCE r u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg/C clock pessimism -0.468 16.830 clock uncertainty -0.071 16.759 FDCE (Recov_fdce_C_CLR) -0.409 16.350 u_AxiCrossbar_2x8/axi4ReadOnlyArbiter_4/cmdArbiter/locked_reg ------------------------------------------------------------------- required time 16.350 arrival time 0.949 ------------------------------------------------------------------- slack 17.299 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.679ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.730ns (logic 0.239ns (32.718%) route 0.491ns (67.282%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.145ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.555ns Source Clock Delay (SCD): -0.882ns Clock Pessimism Removal (CPR): 0.183ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.114 0.345 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.800 -1.455 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, unplaced) 0.337 -1.118 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFG (Prop_bufg_I_O) 0.026 -1.092 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10994, unplaced) 0.210 -0.882 u_Axi_CDC/awFifo/bufferCC_12/sys_clk FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- FDCE (Prop_fdce_C_Q) 0.141 -0.741 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, unplaced) 0.131 -0.610 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 LUT1 (Prop_lut1_I0_O) 0.098 -0.512 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=43, unplaced) 0.360 -0.152 u_Axi_CDC/arFifo/buffers_0_reg[2] FDCE f u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, unplaced) 0.259 0.678 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.971 -1.293 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, unplaced) 0.355 -0.938 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFG (Prop_bufg_I_O) 0.029 -0.909 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=10994, unplaced) 0.355 -0.555 u_Axi_CDC/arFifo/sys_clk FDCE r u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.183 -0.737 FDCE (Remov_fdce_C_CLR) -0.094 -0.831 u_Axi_CDC/arFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.831 arrival time -0.152 ------------------------------------------------------------------- slack 0.679