Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
| Date         : Sun Jul  5 23:38:45 2026
| Host         : fedora running 64-bit unknown
| Command      : report_design_analysis -timing -logic_level_distribution -file ./vivado_reports/impl_design_analysis.rpt
| Design       : soc_top
| Device       : xc7a200t
| Design State : Synthesized
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Report Design Analysis

Table of Contents
-----------------
1. Setup Path Characteristics 1-1
2. Logic Level Distribution

1. Setup Path Characteristics 1-1
---------------------------------

+---------------------------+-----------------------------------------------------------------------------------------------------------+
|      Characteristics      |                                                  Path #1                                                  |
+---------------------------+-----------------------------------------------------------------------------------------------------------+
| Requirement               |                                                                                                    20.000 |
| Path Delay                |                                                                                                    17.702 |
| Logic Delay               | 4.444(26%)                                                                                                |
| Net Delay                 | 13.258(74%)                                                                                               |
| Clock Skew                |                                                                                                    -0.145 |
| Slack                     |                                                                                                     2.111 |
| Clock Relationship        | Safely Timed                                                                                              |
| Logic Levels              |                                                                                                        18 |
| Routes                    |                                                                                                         0 |
| Logical Path              | FDRE LUT2 CARRY4 CARRY4 LUT2 CARRY4 LUT6 LUT6 LUT6 LUT6 LUT6 LUT5 LUT6 LUT5 LUT5 LUT5 LUT5 LUT6 LUT6 FDSE |
| Start Point Clock         | sys_clk                                                                                                   |
| End Point Clock           | sys_clk                                                                                                   |
| DSP Block                 | None                                                                                                      |
| BRAM                      | None                                                                                                      |
| IO Crossings              |                                                                                                         0 |
| Config Crossings          |                                                                                                         0 |
| SLR Crossings             |                                                                                                         0 |
| PBlocks                   |                                                                                                         0 |
| High Fanout               |                                                                                                        16 |
| Dont Touch                |                                                                                                         0 |
| Mark Debug                |                                                                                                         0 |
| Start Point Pin Primitive | FDRE/C                                                                                                    |
| End Point Pin Primitive   | FDSE/D                                                                                                    |
| Start Point Pin           | p_reg[1]/C                                                                                                |
| End Point Pin             | crc_reg_reg[18]/D                                                                                         |
+---------------------------+-----------------------------------------------------------------------------------------------------------+
* Bounding box calculated as % of dimensions for the target device (436, 500)


2. Logic Level Distribution
---------------------------

+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
| End Point Clock | Requirement | 10 |  12 | 13 |  14 |  15 | 16 | 17 | 18 | 19 | 20 | 29 | 30 | 31 | 32 |
+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
| cpu_clk         | 30.323ns    |  0 |   0 |  0 |   0 |   0 |  0 |  0 |  0 |  0 |  0 | 65 | 40 | 34 | 62 |
| sys_clk         | 20.000ns    |  2 | 120 | 72 | 122 | 348 | 89 |  7 | 37 |  1 |  1 |  0 |  0 |  0 |  0 |
+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
* Columns represent the logic levels per end point clock
** Distribution is for top worst 1000 paths