Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 | Date : Fri Jul 10 04:14:51 2026 | Host : fedora running 64-bit unknown | Command : report_timing_summary -delay_type max -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_summary_full.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 38 input ports with no input delay specified. (HIGH) UART_RX UART_TX dip_sw[0] dip_sw[10] dip_sw[11] dip_sw[12] dip_sw[13] dip_sw[14] dip_sw[15] dip_sw[16] dip_sw[17] dip_sw[18] dip_sw[19] dip_sw[1] dip_sw[20] dip_sw[21] dip_sw[22] dip_sw[23] dip_sw[24] dip_sw[25] dip_sw[26] dip_sw[27] dip_sw[28] dip_sw[29] dip_sw[2] dip_sw[30] dip_sw[31] dip_sw[3] dip_sw[4] dip_sw[5] dip_sw[6] dip_sw[7] dip_sw[8] dip_sw[9] touch_btn[0] touch_btn[1] touch_btn[2] touch_btn[3] There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 40 ports with no output delay specified. (HIGH) UART_RX UART_TX dpy0[0] dpy0[1] dpy0[2] dpy0[3] dpy0[4] dpy0[5] dpy0[6] dpy0[7] dpy1[0] dpy1[1] dpy1[2] dpy1[3] dpy1[4] dpy1[5] dpy1[6] dpy1[7] leds[0] leds[10] leds[11] leds[12] leds[13] leds[14] leds[15] leds[1] leds[2] leds[3] leds[4] leds[5] leds[6] leds[7] leds[8] leds[9] video_de video_hsync video_red[0] video_red[1] video_red[2] video_vsync There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.146 0.000 0 113333 7.000 0.000 0 42143 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk {0.000 10.000} 20.000 50.000 clkfbout_clk_pll {0.000 10.000} 20.000 50.000 cpu_clk {0.000 15.161} 30.323 32.979 sys_clk {0.000 10.000} 20.000 50.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk 7.000 0.000 0 1 clkfbout_clk_pll 17.845 0.000 0 3 cpu_clk 1.509 0.000 0 17197 13.911 0.000 0 6486 sys_clk 0.146 0.000 0 69558 8.750 0.000 0 35653 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- **async_default** cpu_clk cpu_clk 26.490 0.000 0 67 **async_default** sys_clk sys_clk 8.003 0.000 0 26511 ------------------------------------------------------------------------------------------------ | User Ignored Path Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) sys_clk cpu_clk (none) cpu_clk sys_clk ------------------------------------------------------------------------------------------------ | Unconstrained Path Table | ------------------------ ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) clkfbout_clk_pll (none) sys_clk (none) sys_clk ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk To Clock: clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { clk } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_pll To Clock: clkfbout_clk_pll Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_pll Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkf_buf/I Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: cpu_clk To Clock: cpu_clk Setup : 0 Failing Endpoints, Worst Slack 1.509ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.509ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.014ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.036 28.530 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/cpu_clk RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK clock pessimism -0.418 28.112 clock uncertainty -0.074 28.038 RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) -0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg ------------------------------------------------------------------- required time 27.472 arrival time -25.963 ------------------------------------------------------------------- slack 1.509 Slack (MET) : 1.512ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: 0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.037 28.531 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/cpu_clk RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK clock pessimism -0.418 28.113 clock uncertainty -0.074 28.039 RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) -0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg ------------------------------------------------------------------- required time 27.473 arrival time -25.962 ------------------------------------------------------------------- slack 1.512 Slack (MET) : 1.855ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.087ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.935 28.429 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/cpu_clk RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK clock pessimism -0.418 28.011 clock uncertainty -0.074 27.937 RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg ------------------------------------------------------------------- required time 27.371 arrival time -25.516 ------------------------------------------------------------------- slack 1.855 Slack (MET) : 1.855ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.087ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.935 28.429 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/cpu_clk RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK clock pessimism -0.418 28.011 clock uncertainty -0.074 27.937 RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg ------------------------------------------------------------------- required time 27.371 arrival time -25.516 ------------------------------------------------------------------- slack 1.855 Slack (MET) : 1.856ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.936 28.430 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/cpu_clk RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK clock pessimism -0.418 28.012 clock uncertainty -0.074 27.938 RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg ------------------------------------------------------------------- required time 27.372 arrival time -25.516 ------------------------------------------------------------------- slack 1.856 Slack (MET) : 1.856ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.936 28.430 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/cpu_clk RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK clock pessimism -0.418 28.012 clock uncertainty -0.074 27.938 RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg ------------------------------------------------------------------- required time 27.372 arrival time -25.516 ------------------------------------------------------------------- slack 1.856 Slack (MET) : 1.916ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.931 28.425 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/cpu_clk RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK clock pessimism -0.418 28.007 clock uncertainty -0.074 27.933 RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) -0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg ------------------------------------------------------------------- required time 27.367 arrival time -25.451 ------------------------------------------------------------------- slack 1.916 Slack (MET) : 1.916ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.931 28.425 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/cpu_clk RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK clock pessimism -0.418 28.007 clock uncertainty -0.074 27.933 RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) -0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg ------------------------------------------------------------------- required time 27.367 arrival time -25.451 ------------------------------------------------------------------- slack 1.916 Slack (MET) : 1.920ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.933 28.427 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/cpu_clk RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK clock pessimism -0.418 28.009 clock uncertainty -0.074 27.935 RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) -0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg ------------------------------------------------------------------- required time 27.369 arrival time -25.450 ------------------------------------------------------------------- slack 1.920 Slack (MET) : 1.920ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.933 28.427 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/cpu_clk RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK clock pessimism -0.418 28.009 clock uncertainty -0.074 27.935 RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) -0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg ------------------------------------------------------------------- required time 27.369 arrival time -25.450 ------------------------------------------------------------------- slack 1.920 Slack (MET) : 1.988ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.905ns (logic 7.157ns (25.647%) route 20.748ns (74.353%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.384ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.110ns = ( 28.212 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.017 22.650 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X40Y23 LUT6 (Prop_lut6_I1_O) 0.124 22.774 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O net (fo=29, routed) 1.565 24.339 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 SLICE_X50Y37 LUT6 (Prop_lut6_I4_O) 0.124 24.463 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O net (fo=1, routed) 1.094 25.557 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 SLICE_X58Y50 LUT6 (Prop_lut6_I4_O) 0.124 25.681 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O net (fo=1, routed) 0.000 25.681 u_cpu/exe_stage/ds_to_es_bus[117] SLICE_X58Y50 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.718 28.212 u_cpu/exe_stage/cpu_clk SLICE_X58Y50 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/C clock pessimism -0.498 27.714 clock uncertainty -0.074 27.640 SLICE_X58Y50 FDRE (Setup_fdre_C_D) 0.029 27.669 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- required time 27.669 arrival time -25.681 ------------------------------------------------------------------- slack 1.988 Slack (MET) : 1.995ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.595ns (logic 5.333ns (19.326%) route 22.262ns (80.674%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.093ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.899ns = ( 28.423 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.331 25.370 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/ADDRBWRADDR[2] RAMB18_X2Y6 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.929 28.423 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/cpu_clk RAMB18_X2Y6 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK clock pessimism -0.418 28.005 clock uncertainty -0.074 27.931 RAMB18_X2Y6 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) -0.566 27.365 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg ------------------------------------------------------------------- required time 27.365 arrival time -25.370 ------------------------------------------------------------------- slack 1.995 Slack (MET) : 1.995ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.595ns (logic 5.333ns (19.326%) route 22.262ns (80.674%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.093ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.899ns = ( 28.423 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.331 25.370 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/ADDRBWRADDR[2] RAMB18_X2Y7 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.929 28.423 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/cpu_clk RAMB18_X2Y7 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK clock pessimism -0.418 28.005 clock uncertainty -0.074 27.931 RAMB18_X2Y7 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) -0.566 27.365 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg ------------------------------------------------------------------- required time 27.365 arrival time -25.370 ------------------------------------------------------------------- slack 1.995 Slack (MET) : 2.008ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.579ns (logic 5.333ns (19.337%) route 22.246ns (80.663%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.902ns = ( 28.420 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.315 25.354 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/ADDRBWRADDR[2] RAMB18_X2Y6 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.926 28.420 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/cpu_clk RAMB18_X2Y6 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK clock pessimism -0.418 28.002 clock uncertainty -0.074 27.928 RAMB18_X2Y6 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) -0.566 27.362 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg ------------------------------------------------------------------- required time 27.362 arrival time -25.354 ------------------------------------------------------------------- slack 2.008 Slack (MET) : 2.008ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.579ns (logic 5.333ns (19.337%) route 22.246ns (80.663%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.902ns = ( 28.420 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.315 25.354 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/ADDRBWRADDR[2] RAMB18_X2Y7 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.926 28.420 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/cpu_clk RAMB18_X2Y7 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK clock pessimism -0.418 28.002 clock uncertainty -0.074 27.928 RAMB18_X2Y7 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) -0.566 27.362 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg ------------------------------------------------------------------- required time 27.362 arrival time -25.354 ------------------------------------------------------------------- slack 2.008 Slack (MET) : 2.064ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.521ns (logic 5.333ns (19.378%) route 22.188ns (80.622%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.098ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.904ns = ( 28.418 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.257 25.297 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/ADDRBWRADDR[2] RAMB18_X2Y8 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.924 28.418 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/cpu_clk RAMB18_X2Y8 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK clock pessimism -0.418 28.000 clock uncertainty -0.074 27.926 RAMB18_X2Y8 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) -0.566 27.360 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg ------------------------------------------------------------------- required time 27.360 arrival time -25.297 ------------------------------------------------------------------- slack 2.064 Slack (MET) : 2.198ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.384ns (logic 5.333ns (19.475%) route 22.051ns (80.525%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.907ns = ( 28.415 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O net (fo=16, routed) 1.120 25.159 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/ADDRBWRADDR[2] RAMB18_X2Y8 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.921 28.415 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/cpu_clk RAMB18_X2Y8 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK clock pessimism -0.418 27.997 clock uncertainty -0.074 27.923 RAMB18_X2Y8 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) -0.566 27.357 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg ------------------------------------------------------------------- required time 27.357 arrival time -25.159 ------------------------------------------------------------------- slack 2.198 Slack (MET) : 2.528ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.715ns (logic 7.360ns (26.556%) route 20.355ns (73.444%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.403ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.836 21.828 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y23 LUT5 (Prop_lut5_I2_O) 0.119 21.947 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 1.248 23.194 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_3 SLICE_X48Y28 LUT6 (Prop_lut6_I5_O) 0.332 23.526 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O net (fo=1, routed) 0.598 24.125 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 SLICE_X48Y26 LUT5 (Prop_lut5_I0_O) 0.124 24.249 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O net (fo=1, routed) 1.118 25.366 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 SLICE_X35Y26 LUT6 (Prop_lut6_I2_O) 0.124 25.490 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O net (fo=1, routed) 0.000 25.490 u_cpu/exe_stage/ds_to_es_bus[124] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.972 28.466 u_cpu/exe_stage/cpu_clk SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/C clock pessimism -0.403 28.063 clock uncertainty -0.074 27.989 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.018 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- required time 28.018 arrival time -25.490 ------------------------------------------------------------------- slack 2.528 Slack (MET) : 2.548ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.673ns (logic 7.157ns (25.862%) route 20.516ns (74.138%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.865ns = ( 28.458 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.017 22.650 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X40Y23 LUT6 (Prop_lut6_I1_O) 0.124 22.774 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O net (fo=29, routed) 1.305 24.078 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 SLICE_X28Y26 LUT5 (Prop_lut5_I2_O) 0.124 24.202 r u_cpu/id_stage/ds_to_es_bus_r[183]_i_5/O net (fo=1, routed) 1.122 25.325 u_cpu/id_stage/ds_to_es_bus_r[183]_i_5_n_0 SLICE_X38Y25 LUT6 (Prop_lut6_I4_O) 0.124 25.449 r u_cpu/id_stage/ds_to_es_bus_r[183]_i_1/O net (fo=1, routed) 0.000 25.449 u_cpu/exe_stage/ds_to_es_bus[133] SLICE_X38Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.964 28.458 u_cpu/exe_stage/cpu_clk SLICE_X38Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/C clock pessimism -0.418 28.040 clock uncertainty -0.074 27.966 SLICE_X38Y25 FDRE (Setup_fdre_C_D) 0.031 27.997 u_cpu/exe_stage/ds_to_es_bus_r_reg[183] ------------------------------------------------------------------- required time 27.997 arrival time -25.449 ------------------------------------------------------------------- slack 2.548 Slack (MET) : 2.597ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.541ns (logic 7.157ns (25.987%) route 20.384ns (74.013%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.949ns = ( 28.374 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.836 21.828 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y23 LUT5 (Prop_lut5_I4_O) 0.124 21.952 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_24/O net (fo=20, routed) 1.394 23.346 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_10 SLICE_X48Y27 LUT6 (Prop_lut6_I3_O) 0.124 23.470 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O net (fo=1, routed) 0.660 24.129 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 SLICE_X48Y24 LUT6 (Prop_lut6_I0_O) 0.124 24.253 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O net (fo=1, routed) 0.939 25.192 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 SLICE_X43Y27 LUT6 (Prop_lut6_I3_O) 0.124 25.316 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O net (fo=1, routed) 0.000 25.316 u_cpu/exe_stage/ds_to_es_bus[131] SLICE_X43Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.880 28.374 u_cpu/exe_stage/cpu_clk SLICE_X43Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/C clock pessimism -0.418 27.956 clock uncertainty -0.074 27.882 SLICE_X43Y27 FDRE (Setup_fdre_C_D) 0.031 27.913 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] ------------------------------------------------------------------- required time 27.913 arrival time -25.316 ------------------------------------------------------------------- slack 2.597 Slack (MET) : 2.616ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/ADDRBWRADDR[6] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.721ns (logic 5.333ns (19.958%) route 21.388ns (80.042%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=1 LUT6=16 MUXF7=1 MUXF8=1) Clock Path Skew: -0.346ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.072ns = ( 28.251 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 2.868 23.534 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X60Y50 LUT6 (Prop_lut6_I5_O) 0.124 23.658 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_7__0/O net (fo=4, routed) 0.838 24.496 u_cpu/icache/tagv_ram_way[0].u/ADDRARDADDR[2] RAMB18_X3Y20 RAMB18E1 r u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/ADDRBWRADDR[6] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.756 28.251 u_cpu/icache/tagv_ram_way[0].u/cpu_clk RAMB18_X3Y20 RAMB18E1 r u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK clock pessimism -0.498 27.752 clock uncertainty -0.074 27.678 RAMB18_X3Y20 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[6]) -0.566 27.112 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg ------------------------------------------------------------------- required time 27.112 arrival time -24.496 ------------------------------------------------------------------- slack 2.616 Slack (MET) : 2.616ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/ADDRBWRADDR[6] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.721ns (logic 5.333ns (19.958%) route 21.388ns (80.042%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=1 LUT6=16 MUXF7=1 MUXF8=1) Clock Path Skew: -0.346ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.072ns = ( 28.251 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 2.868 23.534 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X60Y50 LUT6 (Prop_lut6_I5_O) 0.124 23.658 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_7__0/O net (fo=4, routed) 0.838 24.496 u_cpu/icache/tagv_ram_way[1].u/ADDRARDADDR[2] RAMB18_X3Y21 RAMB18E1 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/ADDRBWRADDR[6] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.756 28.251 u_cpu/icache/tagv_ram_way[1].u/cpu_clk RAMB18_X3Y21 RAMB18E1 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK clock pessimism -0.498 27.752 clock uncertainty -0.074 27.678 RAMB18_X3Y21 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[6]) -0.566 27.112 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg ------------------------------------------------------------------- required time 27.112 arrival time -24.496 ------------------------------------------------------------------- slack 2.616 Slack (MET) : 2.621ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/if_stage/flush_inst_req_buffer_reg[18]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.237ns (logic 5.705ns (20.946%) route 21.532ns (79.054%)) Logic Levels: 29 (CARRY4=4 LUT3=1 LUT4=1 LUT5=5 LUT6=16 MUXF7=1 MUXF8=1) Clock Path Skew: -0.186ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.921ns = ( 28.402 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 r u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 r u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 r u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 f u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 f u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 f u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.893 18.334 u_cpu/exe_stage/data_addr_ok SLICE_X44Y26 LUT6 (Prop_lut6_I1_O) 0.124 18.458 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11/O net (fo=1, routed) 0.460 18.919 u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11_n_0 SLICE_X44Y24 LUT6 (Prop_lut6_I2_O) 0.124 19.043 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_9/O net (fo=1, routed) 0.465 19.507 u_cpu/id_stage/es_allowin SLICE_X46Y23 LUT5 (Prop_lut5_I2_O) 0.124 19.631 f u_cpu/id_stage/request_buffer_cacop_op_mode[1]_i_7/O net (fo=2, routed) 0.495 20.126 u_cpu/if_stage/fs_allowin SLICE_X47Y23 LUT6 (Prop_lut6_I4_O) 0.124 20.250 f u_cpu/if_stage/btb_lock_buffer[37]_i_4/O net (fo=7, routed) 0.831 21.081 u_cpu/if_stage/pfs_ready_go SLICE_X49Y26 LUT6 (Prop_lut6_I1_O) 0.124 21.205 r u_cpu/if_stage/flush_inst_req_buffer[31]_i_1/O net (fo=32, routed) 3.808 25.012 u_cpu/if_stage/flush_inst_req_buffer SLICE_X115Y16 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[18]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.908 28.402 u_cpu/if_stage/cpu_clk SLICE_X115Y16 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[18]/C clock pessimism -0.490 27.912 clock uncertainty -0.074 27.838 SLICE_X115Y16 FDRE (Setup_fdre_C_CE) -0.205 27.633 u_cpu/if_stage/flush_inst_req_buffer_reg[18] ------------------------------------------------------------------- required time 27.633 arrival time -25.012 ------------------------------------------------------------------- slack 2.621 Slack (MET) : 2.748ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/ADDRARDADDR[6] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.588ns (logic 5.333ns (20.058%) route 21.255ns (79.942%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=1 LUT6=16 MUXF7=1 MUXF8=1) Clock Path Skew: -0.347ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.073ns = ( 28.250 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 2.868 23.534 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X60Y50 LUT6 (Prop_lut6_I5_O) 0.124 23.658 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_7__0/O net (fo=4, routed) 0.705 24.363 u_cpu/icache/tagv_ram_way[0].u/ADDRARDADDR[2] RAMB18_X3Y20 RAMB18E1 r u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/ADDRARDADDR[6] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.755 28.250 u_cpu/icache/tagv_ram_way[0].u/cpu_clk RAMB18_X3Y20 RAMB18E1 r u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK clock pessimism -0.498 27.751 clock uncertainty -0.074 27.677 RAMB18_X3Y20 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) -0.566 27.111 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg ------------------------------------------------------------------- required time 27.111 arrival time -24.363 ------------------------------------------------------------------- slack 2.748 Slack (MET) : 2.748ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/ADDRARDADDR[6] (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.588ns (logic 5.333ns (20.058%) route 21.255ns (79.942%)) Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=1 LUT6=16 MUXF7=1 MUXF8=1) Clock Path Skew: -0.347ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.073ns = ( 28.250 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O net (fo=6, routed) 2.868 23.534 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] SLICE_X60Y50 LUT6 (Prop_lut6_I5_O) 0.124 23.658 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_7__0/O net (fo=4, routed) 0.705 24.363 u_cpu/icache/tagv_ram_way[1].u/ADDRARDADDR[2] RAMB18_X3Y21 RAMB18E1 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/ADDRARDADDR[6] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.755 28.250 u_cpu/icache/tagv_ram_way[1].u/cpu_clk RAMB18_X3Y21 RAMB18E1 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK clock pessimism -0.498 27.751 clock uncertainty -0.074 27.677 RAMB18_X3Y21 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) -0.566 27.111 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg ------------------------------------------------------------------- required time 27.111 arrival time -24.363 ------------------------------------------------------------------- slack 2.748 Slack (MET) : 2.850ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.342ns (logic 7.157ns (26.176%) route 20.185ns (73.824%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.945ns = ( 28.378 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.887 21.879 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X45Y20 LUT6 (Prop_lut6_I0_O) 0.124 22.003 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.241 23.244 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X50Y27 LUT6 (Prop_lut6_I3_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_9/O net (fo=1, routed) 1.040 24.408 u_cpu/id_stage/ds_to_es_bus_r[179]_i_9_n_0 SLICE_X48Y28 LUT6 (Prop_lut6_I3_O) 0.124 24.532 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_3/O net (fo=1, routed) 0.462 24.993 u_cpu/id_stage/ds_to_es_bus_r[179]_i_3_n_0 SLICE_X44Y28 LUT5 (Prop_lut5_I2_O) 0.124 25.117 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_1/O net (fo=1, routed) 0.000 25.117 u_cpu/exe_stage/ds_to_es_bus[129] SLICE_X44Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.884 28.378 u_cpu/exe_stage/cpu_clk SLICE_X44Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/C clock pessimism -0.418 27.960 clock uncertainty -0.074 27.886 SLICE_X44Y28 FDRE (Setup_fdre_C_D) 0.081 27.967 u_cpu/exe_stage/ds_to_es_bus_r_reg[179] ------------------------------------------------------------------- required time 27.967 arrival time -25.117 ------------------------------------------------------------------- slack 2.850 Slack (MET) : 2.850ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.335ns (logic 7.157ns (26.183%) route 20.178ns (73.817%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=12 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.836 21.828 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y23 LUT5 (Prop_lut5_I4_O) 0.124 21.952 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_24/O net (fo=20, routed) 1.178 23.130 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_10 SLICE_X49Y28 LUT4 (Prop_lut4_I0_O) 0.124 23.254 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_8/O net (fo=1, routed) 0.659 23.913 u_cpu/id_stage/ds_to_es_bus_r[177]_i_8_n_0 SLICE_X48Y29 LUT4 (Prop_lut4_I3_O) 0.124 24.037 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_3/O net (fo=1, routed) 0.949 24.986 u_cpu/id_stage/ds_to_es_bus_r[177]_i_3_n_0 SLICE_X44Y25 LUT6 (Prop_lut6_I2_O) 0.124 25.110 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O net (fo=1, routed) 0.000 25.110 u_cpu/exe_stage/ds_to_es_bus[127] SLICE_X44Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk SLICE_X44Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/C clock pessimism -0.418 27.955 clock uncertainty -0.074 27.881 SLICE_X44Y25 FDRE (Setup_fdre_C_D) 0.079 27.960 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] ------------------------------------------------------------------- required time 27.960 arrival time -25.110 ------------------------------------------------------------------- slack 2.850 Slack (MET) : 2.883ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/inst_vaddr_buffer_reg[20]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.236ns (logic 5.209ns (19.126%) route 22.027ns (80.874%)) Logic Levels: 25 (CARRY4=4 LUT3=2 LUT4=1 LUT5=1 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 3.828 20.091 u_cpu/if_stage/nextpc5 SLICE_X114Y16 LUT6 (Prop_lut6_I2_O) 0.124 20.215 r u_cpu/if_stage/flush_inst_req_buffer[20]_i_4/O net (fo=1, routed) 0.280 20.495 u_cpu/if_stage/flush_inst_req_buffer[20]_i_4_n_0 SLICE_X114Y16 LUT6 (Prop_lut6_I2_O) 0.124 20.619 r u_cpu/if_stage/flush_inst_req_buffer[20]_i_2/O net (fo=1, routed) 0.159 20.777 u_cpu/if_stage/flush_inst_req_buffer[20]_i_2_n_0 SLICE_X114Y16 LUT6 (Prop_lut6_I2_O) 0.124 20.901 r u_cpu/if_stage/flush_inst_req_buffer[20]_i_1/O net (fo=3, routed) 4.110 25.011 u_cpu/addr_trans/D[8] SLICE_X38Y32 FDRE r u_cpu/addr_trans/inst_vaddr_buffer_reg[20]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.973 28.467 u_cpu/addr_trans/cpu_clk SLICE_X38Y32 FDRE r u_cpu/addr_trans/inst_vaddr_buffer_reg[20]/C clock pessimism -0.418 28.049 clock uncertainty -0.074 27.975 SLICE_X38Y32 FDRE (Setup_fdre_C_D) -0.081 27.894 u_cpu/addr_trans/inst_vaddr_buffer_reg[20] ------------------------------------------------------------------- required time 27.894 arrival time -25.011 ------------------------------------------------------------------- slack 2.883 Slack (MET) : 2.901ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.282ns (logic 7.157ns (26.234%) route 20.125ns (73.766%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.952ns = ( 28.371 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.017 22.650 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X40Y23 LUT6 (Prop_lut6_I1_O) 0.124 22.774 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O net (fo=29, routed) 1.330 24.103 u_cpu/u_csr/ds_to_es_bus_r_reg[184]_0 SLICE_X43Y25 LUT6 (Prop_lut6_I5_O) 0.124 24.227 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O net (fo=1, routed) 0.706 24.933 u_cpu/id_stage/ds_to_es_bus_r_reg[184] SLICE_X42Y25 LUT6 (Prop_lut6_I3_O) 0.124 25.057 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O net (fo=1, routed) 0.000 25.057 u_cpu/exe_stage/ds_to_es_bus[134] SLICE_X42Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.877 28.371 u_cpu/exe_stage/cpu_clk SLICE_X42Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/C clock pessimism -0.418 27.953 clock uncertainty -0.074 27.879 SLICE_X42Y25 FDRE (Setup_fdre_C_D) 0.079 27.958 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- required time 27.958 arrival time -25.057 ------------------------------------------------------------------- slack 2.901 Slack (MET) : 2.901ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/if_stage/flush_inst_req_buffer_reg[20]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.953ns (logic 5.705ns (21.167%) route 21.248ns (78.833%)) Logic Levels: 29 (CARRY4=4 LUT3=1 LUT4=1 LUT5=5 LUT6=16 MUXF7=1 MUXF8=1) Clock Path Skew: -0.190ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.925ns = ( 28.398 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 r u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 r u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 r u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 f u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 f u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 f u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.893 18.334 u_cpu/exe_stage/data_addr_ok SLICE_X44Y26 LUT6 (Prop_lut6_I1_O) 0.124 18.458 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11/O net (fo=1, routed) 0.460 18.919 u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11_n_0 SLICE_X44Y24 LUT6 (Prop_lut6_I2_O) 0.124 19.043 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_9/O net (fo=1, routed) 0.465 19.507 u_cpu/id_stage/es_allowin SLICE_X46Y23 LUT5 (Prop_lut5_I2_O) 0.124 19.631 f u_cpu/id_stage/request_buffer_cacop_op_mode[1]_i_7/O net (fo=2, routed) 0.495 20.126 u_cpu/if_stage/fs_allowin SLICE_X47Y23 LUT6 (Prop_lut6_I4_O) 0.124 20.250 f u_cpu/if_stage/btb_lock_buffer[37]_i_4/O net (fo=7, routed) 0.831 21.081 u_cpu/if_stage/pfs_ready_go SLICE_X49Y26 LUT6 (Prop_lut6_I1_O) 0.124 21.205 r u_cpu/if_stage/flush_inst_req_buffer[31]_i_1/O net (fo=32, routed) 3.524 24.728 u_cpu/if_stage/flush_inst_req_buffer SLICE_X114Y19 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[20]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.904 28.398 u_cpu/if_stage/cpu_clk SLICE_X114Y19 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[20]/C clock pessimism -0.490 27.908 clock uncertainty -0.074 27.834 SLICE_X114Y19 FDRE (Setup_fdre_C_CE) -0.205 27.629 u_cpu/if_stage/flush_inst_req_buffer_reg[20] ------------------------------------------------------------------- required time 27.629 arrival time -24.728 ------------------------------------------------------------------- slack 2.901 Slack (MET) : 2.901ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/if_stage/flush_inst_req_buffer_reg[22]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.953ns (logic 5.705ns (21.167%) route 21.248ns (78.833%)) Logic Levels: 29 (CARRY4=4 LUT3=1 LUT4=1 LUT5=5 LUT6=16 MUXF7=1 MUXF8=1) Clock Path Skew: -0.190ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.925ns = ( 28.398 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 r u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 r u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 r u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 f u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 f u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 f u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.893 18.334 u_cpu/exe_stage/data_addr_ok SLICE_X44Y26 LUT6 (Prop_lut6_I1_O) 0.124 18.458 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11/O net (fo=1, routed) 0.460 18.919 u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11_n_0 SLICE_X44Y24 LUT6 (Prop_lut6_I2_O) 0.124 19.043 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_9/O net (fo=1, routed) 0.465 19.507 u_cpu/id_stage/es_allowin SLICE_X46Y23 LUT5 (Prop_lut5_I2_O) 0.124 19.631 f u_cpu/id_stage/request_buffer_cacop_op_mode[1]_i_7/O net (fo=2, routed) 0.495 20.126 u_cpu/if_stage/fs_allowin SLICE_X47Y23 LUT6 (Prop_lut6_I4_O) 0.124 20.250 f u_cpu/if_stage/btb_lock_buffer[37]_i_4/O net (fo=7, routed) 0.831 21.081 u_cpu/if_stage/pfs_ready_go SLICE_X49Y26 LUT6 (Prop_lut6_I1_O) 0.124 21.205 r u_cpu/if_stage/flush_inst_req_buffer[31]_i_1/O net (fo=32, routed) 3.524 24.728 u_cpu/if_stage/flush_inst_req_buffer SLICE_X114Y19 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[22]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.904 28.398 u_cpu/if_stage/cpu_clk SLICE_X114Y19 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[22]/C clock pessimism -0.490 27.908 clock uncertainty -0.074 27.834 SLICE_X114Y19 FDRE (Setup_fdre_C_CE) -0.205 27.629 u_cpu/if_stage/flush_inst_req_buffer_reg[22] ------------------------------------------------------------------- required time 27.629 arrival time -24.728 ------------------------------------------------------------------- slack 2.901 Slack (MET) : 2.901ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/if_stage/flush_inst_req_buffer_reg[28]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.953ns (logic 5.705ns (21.167%) route 21.248ns (78.833%)) Logic Levels: 29 (CARRY4=4 LUT3=1 LUT4=1 LUT5=5 LUT6=16 MUXF7=1 MUXF8=1) Clock Path Skew: -0.190ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.925ns = ( 28.398 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 r u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 r u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 r u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 f u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 f u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 f u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.893 18.334 u_cpu/exe_stage/data_addr_ok SLICE_X44Y26 LUT6 (Prop_lut6_I1_O) 0.124 18.458 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11/O net (fo=1, routed) 0.460 18.919 u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11_n_0 SLICE_X44Y24 LUT6 (Prop_lut6_I2_O) 0.124 19.043 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_9/O net (fo=1, routed) 0.465 19.507 u_cpu/id_stage/es_allowin SLICE_X46Y23 LUT5 (Prop_lut5_I2_O) 0.124 19.631 f u_cpu/id_stage/request_buffer_cacop_op_mode[1]_i_7/O net (fo=2, routed) 0.495 20.126 u_cpu/if_stage/fs_allowin SLICE_X47Y23 LUT6 (Prop_lut6_I4_O) 0.124 20.250 f u_cpu/if_stage/btb_lock_buffer[37]_i_4/O net (fo=7, routed) 0.831 21.081 u_cpu/if_stage/pfs_ready_go SLICE_X49Y26 LUT6 (Prop_lut6_I1_O) 0.124 21.205 r u_cpu/if_stage/flush_inst_req_buffer[31]_i_1/O net (fo=32, routed) 3.524 24.728 u_cpu/if_stage/flush_inst_req_buffer SLICE_X114Y19 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[28]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.904 28.398 u_cpu/if_stage/cpu_clk SLICE_X114Y19 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[28]/C clock pessimism -0.490 27.908 clock uncertainty -0.074 27.834 SLICE_X114Y19 FDRE (Setup_fdre_C_CE) -0.205 27.629 u_cpu/if_stage/flush_inst_req_buffer_reg[28] ------------------------------------------------------------------- required time 27.629 arrival time -24.728 ------------------------------------------------------------------- slack 2.901 Slack (MET) : 2.912ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.310ns (logic 7.157ns (26.206%) route 20.153ns (73.794%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.017 22.650 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X40Y23 LUT6 (Prop_lut6_I1_O) 0.124 22.774 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O net (fo=29, routed) 1.082 23.855 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 SLICE_X31Y27 LUT5 (Prop_lut5_I2_O) 0.124 23.979 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_5/O net (fo=1, routed) 0.982 24.962 u_cpu/id_stage/ds_to_es_bus_r[186]_i_5_n_0 SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 25.086 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O net (fo=1, routed) 0.000 25.086 u_cpu/exe_stage/ds_to_es_bus[136] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.967 28.461 u_cpu/exe_stage/cpu_clk SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/C clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.029 27.998 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] ------------------------------------------------------------------- required time 27.998 arrival time -25.086 ------------------------------------------------------------------- slack 2.912 Slack (MET) : 2.943ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.301ns (logic 7.360ns (26.959%) route 19.941ns (73.041%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.403ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.836 21.828 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y23 LUT5 (Prop_lut5_I2_O) 0.119 21.947 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 1.128 23.074 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X46Y26 LUT4 (Prop_lut4_I3_O) 0.332 23.406 r u_cpu/u_csr/ds_to_es_bus_r[188]_i_12/O net (fo=1, routed) 0.670 24.076 u_cpu/id_stage/ds_to_es_bus_r_reg[188] SLICE_X46Y26 LUT6 (Prop_lut6_I1_O) 0.124 24.200 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_5/O net (fo=1, routed) 0.752 24.953 u_cpu/id_stage/ds_to_es_bus_r[188]_i_5_n_0 SLICE_X35Y26 LUT6 (Prop_lut6_I4_O) 0.124 25.077 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_1/O net (fo=1, routed) 0.000 25.077 u_cpu/exe_stage/ds_to_es_bus[138] SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.972 28.466 u_cpu/exe_stage/cpu_clk SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/C clock pessimism -0.403 28.063 clock uncertainty -0.074 27.989 SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.031 28.020 u_cpu/exe_stage/ds_to_es_bus_r_reg[188] ------------------------------------------------------------------- required time 28.020 arrival time -25.077 ------------------------------------------------------------------- slack 2.943 Slack (MET) : 2.979ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.248ns (logic 7.360ns (27.011%) route 19.888ns (72.989%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.836 21.828 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y23 LUT5 (Prop_lut5_I2_O) 0.119 21.947 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O net (fo=20, routed) 1.140 23.086 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 SLICE_X46Y28 LUT6 (Prop_lut6_I0_O) 0.332 23.418 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O net (fo=1, routed) 0.699 24.117 u_cpu/id_stage/ds_to_es_bus_r_reg[190] SLICE_X41Y27 LUT6 (Prop_lut6_I2_O) 0.124 24.241 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O net (fo=1, routed) 0.659 24.900 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 SLICE_X35Y24 LUT5 (Prop_lut5_I1_O) 0.124 25.024 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O net (fo=1, routed) 0.000 25.024 u_cpu/exe_stage/ds_to_es_bus[140] SLICE_X35Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.970 28.464 u_cpu/exe_stage/cpu_clk SLICE_X35Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/C clock pessimism -0.418 28.046 clock uncertainty -0.074 27.972 SLICE_X35Y24 FDRE (Setup_fdre_C_D) 0.031 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- required time 28.003 arrival time -25.024 ------------------------------------------------------------------- slack 2.979 Slack (MET) : 2.983ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/if_stage/flush_inst_req_buffer_reg[27]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.868ns (logic 5.705ns (21.233%) route 21.163ns (78.767%)) Logic Levels: 29 (CARRY4=4 LUT3=1 LUT4=1 LUT5=5 LUT6=16 MUXF7=1 MUXF8=1) Clock Path Skew: -0.193ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.928ns = ( 28.395 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 r u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 r u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 r u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 f u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 f u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 f u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.893 18.334 u_cpu/exe_stage/data_addr_ok SLICE_X44Y26 LUT6 (Prop_lut6_I1_O) 0.124 18.458 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11/O net (fo=1, routed) 0.460 18.919 u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11_n_0 SLICE_X44Y24 LUT6 (Prop_lut6_I2_O) 0.124 19.043 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_9/O net (fo=1, routed) 0.465 19.507 u_cpu/id_stage/es_allowin SLICE_X46Y23 LUT5 (Prop_lut5_I2_O) 0.124 19.631 f u_cpu/id_stage/request_buffer_cacop_op_mode[1]_i_7/O net (fo=2, routed) 0.495 20.126 u_cpu/if_stage/fs_allowin SLICE_X47Y23 LUT6 (Prop_lut6_I4_O) 0.124 20.250 f u_cpu/if_stage/btb_lock_buffer[37]_i_4/O net (fo=7, routed) 0.831 21.081 u_cpu/if_stage/pfs_ready_go SLICE_X49Y26 LUT6 (Prop_lut6_I1_O) 0.124 21.205 r u_cpu/if_stage/flush_inst_req_buffer[31]_i_1/O net (fo=32, routed) 3.439 24.643 u_cpu/if_stage/flush_inst_req_buffer SLICE_X114Y27 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[27]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.901 28.395 u_cpu/if_stage/cpu_clk SLICE_X114Y27 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[27]/C clock pessimism -0.490 27.905 clock uncertainty -0.074 27.831 SLICE_X114Y27 FDRE (Setup_fdre_C_CE) -0.205 27.626 u_cpu/if_stage/flush_inst_req_buffer_reg[27] ------------------------------------------------------------------- required time 27.626 arrival time -24.643 ------------------------------------------------------------------- slack 2.983 Slack (MET) : 2.983ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/if_stage/flush_inst_req_buffer_reg[6]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.868ns (logic 5.705ns (21.233%) route 21.163ns (78.767%)) Logic Levels: 29 (CARRY4=4 LUT3=1 LUT4=1 LUT5=5 LUT6=16 MUXF7=1 MUXF8=1) Clock Path Skew: -0.193ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.928ns = ( 28.395 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 r u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 r u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 r u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 f u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 f u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 f u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.893 18.334 u_cpu/exe_stage/data_addr_ok SLICE_X44Y26 LUT6 (Prop_lut6_I1_O) 0.124 18.458 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11/O net (fo=1, routed) 0.460 18.919 u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11_n_0 SLICE_X44Y24 LUT6 (Prop_lut6_I2_O) 0.124 19.043 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_9/O net (fo=1, routed) 0.465 19.507 u_cpu/id_stage/es_allowin SLICE_X46Y23 LUT5 (Prop_lut5_I2_O) 0.124 19.631 f u_cpu/id_stage/request_buffer_cacop_op_mode[1]_i_7/O net (fo=2, routed) 0.495 20.126 u_cpu/if_stage/fs_allowin SLICE_X47Y23 LUT6 (Prop_lut6_I4_O) 0.124 20.250 f u_cpu/if_stage/btb_lock_buffer[37]_i_4/O net (fo=7, routed) 0.831 21.081 u_cpu/if_stage/pfs_ready_go SLICE_X49Y26 LUT6 (Prop_lut6_I1_O) 0.124 21.205 r u_cpu/if_stage/flush_inst_req_buffer[31]_i_1/O net (fo=32, routed) 3.439 24.643 u_cpu/if_stage/flush_inst_req_buffer SLICE_X114Y27 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.901 28.395 u_cpu/if_stage/cpu_clk SLICE_X114Y27 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[6]/C clock pessimism -0.490 27.905 clock uncertainty -0.074 27.831 SLICE_X114Y27 FDRE (Setup_fdre_C_CE) -0.205 27.626 u_cpu/if_stage/flush_inst_req_buffer_reg[6] ------------------------------------------------------------------- required time 27.626 arrival time -24.643 ------------------------------------------------------------------- slack 2.983 Slack (MET) : 2.984ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.241ns (logic 7.157ns (26.273%) route 20.084ns (73.727%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.017 22.650 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X40Y23 LUT6 (Prop_lut6_I1_O) 0.124 22.774 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O net (fo=29, routed) 1.085 23.859 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 SLICE_X31Y26 LUT5 (Prop_lut5_I3_O) 0.124 23.983 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_6/O net (fo=1, routed) 0.910 24.892 u_cpu/id_stage/ds_to_es_bus_r[189]_i_6_n_0 SLICE_X38Y27 LUT6 (Prop_lut6_I5_O) 0.124 25.016 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O net (fo=1, routed) 0.000 25.016 u_cpu/exe_stage/ds_to_es_bus[139] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.967 28.461 u_cpu/exe_stage/cpu_clk SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/C clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] ------------------------------------------------------------------- required time 28.000 arrival time -25.016 ------------------------------------------------------------------- slack 2.984 Slack (MET) : 2.985ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.196ns (logic 7.157ns (26.317%) route 20.039ns (73.683%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.952ns = ( 28.371 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.157 22.789 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X41Y25 LUT6 (Prop_lut6_I1_O) 0.124 22.913 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_7/O net (fo=9, routed) 1.073 23.986 u_cpu/id_stage/ds_to_es_bus_r[193]_i_7_n_0 SLICE_X43Y28 LUT6 (Prop_lut6_I3_O) 0.124 24.110 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_2/O net (fo=1, routed) 0.737 24.847 u_cpu/id_stage/ds_to_es_bus_r[165]_i_2_n_0 SLICE_X42Y25 LUT6 (Prop_lut6_I1_O) 0.124 24.971 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O net (fo=1, routed) 0.000 24.971 u_cpu/exe_stage/ds_to_es_bus[115] SLICE_X42Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.877 28.371 u_cpu/exe_stage/cpu_clk SLICE_X42Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/C clock pessimism -0.418 27.953 clock uncertainty -0.074 27.879 SLICE_X42Y25 FDRE (Setup_fdre_C_D) 0.077 27.956 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- required time 27.956 arrival time -24.971 ------------------------------------------------------------------- slack 2.985 Slack (MET) : 2.992ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.194ns (logic 7.157ns (26.318%) route 20.037ns (73.682%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=3 LUT5=6 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.000 22.633 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X40Y23 LUT6 (Prop_lut6_I0_O) 0.124 22.757 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O net (fo=15, routed) 0.959 23.716 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 SLICE_X44Y27 LUT4 (Prop_lut4_I2_O) 0.124 23.840 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_2/O net (fo=1, routed) 1.006 24.845 u_cpu/id_stage/ds_to_es_bus_r[176]_i_2_n_0 SLICE_X44Y25 LUT6 (Prop_lut6_I1_O) 0.124 24.969 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O net (fo=1, routed) 0.000 24.969 u_cpu/exe_stage/ds_to_es_bus[126] SLICE_X44Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk SLICE_X44Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/C clock pessimism -0.418 27.955 clock uncertainty -0.074 27.881 SLICE_X44Y25 FDRE (Setup_fdre_C_D) 0.081 27.962 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- required time 27.962 arrival time -24.969 ------------------------------------------------------------------- slack 2.992 Slack (MET) : 2.994ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.252ns (logic 7.157ns (26.263%) route 20.095ns (73.737%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.403ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.887 21.879 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X45Y20 LUT6 (Prop_lut6_I0_O) 0.124 22.003 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O net (fo=26, routed) 1.128 23.131 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 SLICE_X46Y29 LUT6 (Prop_lut6_I0_O) 0.124 23.255 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_11/O net (fo=1, routed) 0.459 23.713 u_cpu/id_stage/ds_to_es_bus_r[191]_i_11_n_0 SLICE_X44Y28 LUT6 (Prop_lut6_I5_O) 0.124 23.837 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_3/O net (fo=1, routed) 1.066 24.903 u_cpu/id_stage/ds_to_es_bus_r[191]_i_3_n_0 SLICE_X34Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.027 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_1/O net (fo=1, routed) 0.000 25.027 u_cpu/exe_stage/ds_to_es_bus[141] SLICE_X34Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.975 28.469 u_cpu/exe_stage/cpu_clk SLICE_X34Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/C clock pessimism -0.403 28.066 clock uncertainty -0.074 27.992 SLICE_X34Y28 FDRE (Setup_fdre_C_D) 0.029 28.021 u_cpu/exe_stage/ds_to_es_bus_r_reg[191] ------------------------------------------------------------------- required time 28.021 arrival time -25.027 ------------------------------------------------------------------- slack 2.994 Slack (MET) : 2.999ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.222ns (logic 7.391ns (27.150%) route 19.831ns (72.850%)) Logic Levels: 32 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.748 22.380 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X45Y24 LUT6 (Prop_lut6_I0_O) 0.124 22.504 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O net (fo=27, routed) 0.913 23.418 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 SLICE_X45Y26 LUT2 (Prop_lut2_I1_O) 0.150 23.568 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O net (fo=1, routed) 1.098 24.666 u_cpu/id_stage/ds_to_es_bus_r_reg[171] SLICE_X38Y23 LUT6 (Prop_lut6_I2_O) 0.332 24.998 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O net (fo=1, routed) 0.000 24.998 u_cpu/exe_stage/ds_to_es_bus[121] SLICE_X38Y23 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.966 28.460 u_cpu/exe_stage/cpu_clk SLICE_X38Y23 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/C clock pessimism -0.418 28.042 clock uncertainty -0.074 27.968 SLICE_X38Y23 FDRE (Setup_fdre_C_D) 0.029 27.997 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] ------------------------------------------------------------------- required time 27.997 arrival time -24.998 ------------------------------------------------------------------- slack 2.999 Slack (MET) : 3.036ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.147ns (logic 7.157ns (26.364%) route 19.990ns (73.636%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.892 21.883 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X38Y24 LUT6 (Prop_lut6_I2_O) 0.124 22.007 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 0.978 22.985 u_cpu/id_stage/fs_to_ds_bus_r_reg[46]_1 SLICE_X34Y23 LUT6 (Prop_lut6_I0_O) 0.124 23.109 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_11/O net (fo=1, routed) 0.702 23.811 u_cpu/id_stage/ds_to_es_bus_r[173]_i_11_n_0 SLICE_X41Y23 LUT6 (Prop_lut6_I0_O) 0.124 23.935 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_4/O net (fo=1, routed) 0.863 24.798 u_cpu/id_stage/ds_to_es_bus_r[173]_i_4_n_0 SLICE_X44Y25 LUT6 (Prop_lut6_I4_O) 0.124 24.922 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_1/O net (fo=1, routed) 0.000 24.922 u_cpu/exe_stage/ds_to_es_bus[123] SLICE_X44Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk SLICE_X44Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/C clock pessimism -0.418 27.955 clock uncertainty -0.074 27.881 SLICE_X44Y25 FDRE (Setup_fdre_C_D) 0.077 27.958 u_cpu/exe_stage/ds_to_es_bus_r_reg[173] ------------------------------------------------------------------- required time 27.958 arrival time -24.922 ------------------------------------------------------------------- slack 3.036 Slack (MET) : 3.048ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.135ns (logic 7.157ns (26.376%) route 19.978ns (73.624%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 1.157 22.789 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X41Y25 LUT6 (Prop_lut6_I1_O) 0.124 22.913 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_7/O net (fo=9, routed) 1.129 24.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_7_n_0 SLICE_X46Y28 LUT6 (Prop_lut6_I3_O) 0.124 24.166 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_2/O net (fo=1, routed) 0.620 24.786 u_cpu/id_stage/ds_to_es_bus_r[166]_i_2_n_0 SLICE_X46Y24 LUT6 (Prop_lut6_I1_O) 0.124 24.910 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_1/O net (fo=1, routed) 0.000 24.910 u_cpu/exe_stage/ds_to_es_bus[116] SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/C clock pessimism -0.418 27.955 clock uncertainty -0.074 27.881 SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.958 u_cpu/exe_stage/ds_to_es_bus_r_reg[166] ------------------------------------------------------------------- required time 27.958 arrival time -24.910 ------------------------------------------------------------------- slack 3.048 Slack (MET) : 3.062ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.163ns (logic 7.157ns (26.349%) route 20.006ns (73.651%)) Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) Clock Path Skew: -0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.892 21.883 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X38Y24 LUT6 (Prop_lut6_I2_O) 0.124 22.007 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O net (fo=32, routed) 1.164 23.172 u_cpu/id_stage/fs_to_ds_bus_r_reg[46]_1 SLICE_X29Y27 LUT4 (Prop_lut4_I2_O) 0.124 23.296 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_13/O net (fo=1, routed) 0.424 23.720 u_cpu/id_stage/ds_to_es_bus_r[187]_i_13_n_0 SLICE_X31Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.844 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_6/O net (fo=1, routed) 0.970 24.814 u_cpu/id_stage/ds_to_es_bus_r[187]_i_6_n_0 SLICE_X38Y27 LUT6 (Prop_lut6_I5_O) 0.124 24.938 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O net (fo=1, routed) 0.000 24.938 u_cpu/exe_stage/ds_to_es_bus[137] SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.967 28.461 u_cpu/exe_stage/cpu_clk SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/C clock pessimism -0.418 28.043 clock uncertainty -0.074 27.969 SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] ------------------------------------------------------------------- required time 28.000 arrival time -24.938 ------------------------------------------------------------------- slack 3.062 Slack (MET) : 3.068ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 27.117ns (logic 7.374ns (27.193%) route 19.743ns (72.807%)) Logic Levels: 32 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.952ns = ( 28.371 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O net (fo=20, routed) 0.893 22.525 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 SLICE_X44Y24 LUT6 (Prop_lut6_I0_O) 0.124 22.649 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O net (fo=22, routed) 0.750 23.399 u_cpu/u_csr/ds_to_es_bus_r_reg[172] SLICE_X46Y25 LUT2 (Prop_lut2_I1_O) 0.117 23.516 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O net (fo=1, routed) 1.028 24.544 u_cpu/id_stage/ds_to_es_bus_r_reg[172] SLICE_X42Y24 LUT6 (Prop_lut6_I2_O) 0.348 24.892 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O net (fo=1, routed) 0.000 24.892 u_cpu/exe_stage/ds_to_es_bus[122] SLICE_X42Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.877 28.371 u_cpu/exe_stage/cpu_clk SLICE_X42Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/C clock pessimism -0.418 27.953 clock uncertainty -0.074 27.879 SLICE_X42Y24 FDRE (Setup_fdre_C_D) 0.081 27.960 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] ------------------------------------------------------------------- required time 27.960 arrival time -24.892 ------------------------------------------------------------------- slack 3.068 Slack (MET) : 3.072ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/if_stage/fs_pc_reg[20]/D (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.964ns (logic 5.209ns (19.318%) route 21.755ns (80.682%)) Logic Levels: 25 (CARRY4=4 LUT3=2 LUT4=1 LUT5=1 LUT6=15 MUXF7=1 MUXF8=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.952ns = ( 28.371 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O net (fo=32, routed) 3.828 20.091 u_cpu/if_stage/nextpc5 SLICE_X114Y16 LUT6 (Prop_lut6_I2_O) 0.124 20.215 r u_cpu/if_stage/flush_inst_req_buffer[20]_i_4/O net (fo=1, routed) 0.280 20.495 u_cpu/if_stage/flush_inst_req_buffer[20]_i_4_n_0 SLICE_X114Y16 LUT6 (Prop_lut6_I2_O) 0.124 20.619 r u_cpu/if_stage/flush_inst_req_buffer[20]_i_2/O net (fo=1, routed) 0.159 20.777 u_cpu/if_stage/flush_inst_req_buffer[20]_i_2_n_0 SLICE_X114Y16 LUT6 (Prop_lut6_I2_O) 0.124 20.901 r u_cpu/if_stage/flush_inst_req_buffer[20]_i_1/O net (fo=3, routed) 3.838 24.740 u_cpu/if_stage/D[20] SLICE_X51Y24 FDSE r u_cpu/if_stage/fs_pc_reg[20]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.877 28.371 u_cpu/if_stage/cpu_clk SLICE_X51Y24 FDSE r u_cpu/if_stage/fs_pc_reg[20]/C clock pessimism -0.418 27.953 clock uncertainty -0.074 27.879 SLICE_X51Y24 FDSE (Setup_fdse_C_D) -0.067 27.812 u_cpu/if_stage/fs_pc_reg[20] ------------------------------------------------------------------- required time 27.812 arrival time -24.740 ------------------------------------------------------------------- slack 3.072 Slack (MET) : 3.074ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[23][10]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.786ns (logic 5.581ns (20.835%) route 21.205ns (79.165%)) Logic Levels: 28 (CARRY4=4 LUT3=1 LUT4=2 LUT5=5 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.183ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.918ns = ( 28.405 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.890 18.331 u_cpu/exe_stage/data_addr_ok SLICE_X42Y24 LUT6 (Prop_lut6_I2_O) 0.124 18.455 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.503 18.958 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X44Y21 LUT6 (Prop_lut6_I2_O) 0.124 19.082 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.485 19.567 u_cpu/btb/btb_operate_en SLICE_X45Y19 LUT5 (Prop_lut5_I3_O) 0.124 19.691 f u_cpu/btb/btb_counter[23][1]_i_4/O net (fo=26, routed) 3.899 23.590 u_cpu/btb/btb_counter[23][1]_i_4_n_0 SLICE_X114Y6 LUT4 (Prop_lut4_I0_O) 0.124 23.714 r u_cpu/btb/btb_pc[23][29]_i_1/O net (fo=30, routed) 0.848 24.562 u_cpu/btb/btb_pc[23][29]_i_1_n_0 SLICE_X114Y12 FDRE r u_cpu/btb/btb_pc_reg[23][10]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.911 28.405 u_cpu/btb/cpu_clk SLICE_X114Y12 FDRE r u_cpu/btb/btb_pc_reg[23][10]/C clock pessimism -0.490 27.915 clock uncertainty -0.074 27.841 SLICE_X114Y12 FDRE (Setup_fdre_C_CE) -0.205 27.636 u_cpu/btb/btb_pc_reg[23][10] ------------------------------------------------------------------- required time 27.636 arrival time -24.562 ------------------------------------------------------------------- slack 3.074 Slack (MET) : 3.074ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[23][13]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.786ns (logic 5.581ns (20.835%) route 21.205ns (79.165%)) Logic Levels: 28 (CARRY4=4 LUT3=1 LUT4=2 LUT5=5 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.183ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.918ns = ( 28.405 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.890 18.331 u_cpu/exe_stage/data_addr_ok SLICE_X42Y24 LUT6 (Prop_lut6_I2_O) 0.124 18.455 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.503 18.958 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X44Y21 LUT6 (Prop_lut6_I2_O) 0.124 19.082 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.485 19.567 u_cpu/btb/btb_operate_en SLICE_X45Y19 LUT5 (Prop_lut5_I3_O) 0.124 19.691 f u_cpu/btb/btb_counter[23][1]_i_4/O net (fo=26, routed) 3.899 23.590 u_cpu/btb/btb_counter[23][1]_i_4_n_0 SLICE_X114Y6 LUT4 (Prop_lut4_I0_O) 0.124 23.714 r u_cpu/btb/btb_pc[23][29]_i_1/O net (fo=30, routed) 0.848 24.562 u_cpu/btb/btb_pc[23][29]_i_1_n_0 SLICE_X114Y12 FDRE r u_cpu/btb/btb_pc_reg[23][13]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.911 28.405 u_cpu/btb/cpu_clk SLICE_X114Y12 FDRE r u_cpu/btb/btb_pc_reg[23][13]/C clock pessimism -0.490 27.915 clock uncertainty -0.074 27.841 SLICE_X114Y12 FDRE (Setup_fdre_C_CE) -0.205 27.636 u_cpu/btb/btb_pc_reg[23][13] ------------------------------------------------------------------- required time 27.636 arrival time -24.562 ------------------------------------------------------------------- slack 3.074 Slack (MET) : 3.074ns (required time - arrival time) Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/btb_pc_reg[23][1]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 26.786ns (logic 5.581ns (20.835%) route 21.205ns (79.165%)) Logic Levels: 28 (CARRY4=4 LUT3=1 LUT4=2 LUT5=5 LUT6=14 MUXF7=1 MUXF8=1) Clock Path Skew: -0.183ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.918ns = ( 28.405 - 30.323 ) Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 f u_cpu/mem_stage/request_buffer_icacop_i_2/O net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O net (fo=11, routed) 0.890 18.331 u_cpu/exe_stage/data_addr_ok SLICE_X42Y24 LUT6 (Prop_lut6_I2_O) 0.124 18.455 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O net (fo=6, routed) 0.503 18.958 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 SLICE_X44Y21 LUT6 (Prop_lut6_I2_O) 0.124 19.082 r u_cpu/exe_stage/btb_add_entry_r_i_3/O net (fo=18, routed) 0.485 19.567 u_cpu/btb/btb_operate_en SLICE_X45Y19 LUT5 (Prop_lut5_I3_O) 0.124 19.691 f u_cpu/btb/btb_counter[23][1]_i_4/O net (fo=26, routed) 3.899 23.590 u_cpu/btb/btb_counter[23][1]_i_4_n_0 SLICE_X114Y6 LUT4 (Prop_lut4_I0_O) 0.124 23.714 r u_cpu/btb/btb_pc[23][29]_i_1/O net (fo=30, routed) 0.848 24.562 u_cpu/btb/btb_pc[23][29]_i_1_n_0 SLICE_X114Y12 FDRE r u_cpu/btb/btb_pc_reg[23][1]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.911 28.405 u_cpu/btb/cpu_clk SLICE_X114Y12 FDRE r u_cpu/btb/btb_pc_reg[23][1]/C clock pessimism -0.490 27.915 clock uncertainty -0.074 27.841 SLICE_X114Y12 FDRE (Setup_fdre_C_CE) -0.205 27.636 u_cpu/btb/btb_pc_reg[23][1] ------------------------------------------------------------------- required time 27.636 arrival time -24.562 ------------------------------------------------------------------- slack 3.074 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: cpu_clk Waveform(ns): { 0.000 15.161 } Period(ns): 30.323 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y4 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y4 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y6 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y6 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y7 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y7 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y5 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y5 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y8 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y8 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y20 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y20 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y18 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y18 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X3Y20 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X3Y20 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X3Y21 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X3Y21 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.323 29.074 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y1 u_cpu/btb/btb_add_entry_index_r_reg[0]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X41Y3 u_cpu/btb/btb_add_entry_index_r_reg[1]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X47Y0 u_cpu/btb/btb_add_entry_index_r_reg[2]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y6 u_cpu/btb/btb_add_entry_index_r_reg[3]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y6 u_cpu/btb/btb_add_entry_index_r_reg[4]/C Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X41Y6 u_cpu/btb/btb_add_entry_r_reg/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X5Y45 pll_clk.u_rst_cpu/delay_reg[0]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X5Y45 pll_clk.u_rst_cpu/delay_reg[1]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y57 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y57 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y8 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y8 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- From Clock: sys_clk To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 0.146ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.146ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O net (fo=0) 0.000 13.208 base_ram_be_n[3] K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -13.208 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.243ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.313ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.535 17.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/C clock pessimism -0.507 17.200 clock uncertainty -0.071 17.130 SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] ------------------------------------------------------------------- required time 17.194 arrival time -16.951 ------------------------------------------------------------------- slack 0.243 Slack (MET) : 0.272ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.313ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.535 17.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/C clock pessimism -0.507 17.200 clock uncertainty -0.071 17.130 SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] ------------------------------------------------------------------- required time 17.194 arrival time -16.922 ------------------------------------------------------------------- slack 0.272 Slack (MET) : 0.275ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[23] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T AA15 OBUFT (TriStatE_obuft_T_O) 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O net (fo=1, unset) 0.000 13.079 ext_ram_data[23] AA15 r ext_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -13.079 ------------------------------------------------------------------- slack 0.275 Slack (MET) : 0.280ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T L25 OBUFT (TriStatE_obuft_T_O) 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O net (fo=1, unset) 0.000 13.074 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -13.074 ------------------------------------------------------------------- slack 0.280 Slack (MET) : 0.281ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T AC16 OBUFT (TriStatE_obuft_T_O) 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O net (fo=1, unset) 0.000 13.073 ext_ram_data[21] AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -13.073 ------------------------------------------------------------------- slack 0.281 Slack (MET) : 0.287ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T M24 OBUFT (TriStatE_obuft_T_O) 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O net (fo=1, unset) 0.000 13.067 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -13.067 ------------------------------------------------------------------- slack 0.287 Slack (MET) : 0.311ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T AD17 OBUFT (TriStatE_obuft_T_O) 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O net (fo=1, unset) 0.000 13.043 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -13.043 ------------------------------------------------------------------- slack 0.311 Slack (MET) : 0.324ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O net (fo=0) 0.000 13.030 base_ram_be_n[1] L22 r base_ram_be_n[1] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -13.030 ------------------------------------------------------------------- slack 0.324 Slack (MET) : 0.328ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T AB16 OBUFT (TriStatE_obuft_T_O) 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 13.026 ext_ram_data[16] AB16 r ext_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -13.026 ------------------------------------------------------------------- slack 0.328 Slack (MET) : 0.329ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.314ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.534 17.706 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/C clock pessimism -0.507 17.199 clock uncertainty -0.071 17.129 SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] ------------------------------------------------------------------- required time 17.242 arrival time -16.913 ------------------------------------------------------------------- slack 0.329 Slack (MET) : 0.332ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.321ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.527 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/C clock pessimism -0.507 17.192 clock uncertainty -0.071 17.122 SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] ------------------------------------------------------------------- required time 17.186 arrival time -16.854 ------------------------------------------------------------------- slack 0.332 Slack (MET) : 0.344ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T L24 OBUFT (TriStatE_obuft_T_O) 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O net (fo=1, unset) 0.000 13.010 base_ram_data[0] L24 r base_ram_data[0] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -13.010 ------------------------------------------------------------------- slack 0.344 Slack (MET) : 0.344ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[619]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.387ns (logic 0.821ns (4.235%) route 18.566ns (95.765%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.291ns = ( 17.709 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.566 16.535 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X74Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.659 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[619]_i_2/O net (fo=1, routed) 0.000 16.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[619]_i_2_n_0 SLICE_X74Y142 MUXF7 (Prop_muxf7_I0_O) 0.241 16.900 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[619]_i_1/O net (fo=1, routed) 0.000 16.900 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_498 SLICE_X74Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[619]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.537 17.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X74Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[619]/C clock pessimism -0.507 17.202 clock uncertainty -0.071 17.132 SLICE_X74Y142 FDCE (Setup_fdce_C_D) 0.113 17.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[619] ------------------------------------------------------------------- required time 17.245 arrival time -16.900 ------------------------------------------------------------------- slack 0.344 Slack (MET) : 0.353ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[18] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.322ns (logic 6.859ns (44.764%) route 8.463ns (55.236%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.189 9.460 ext_ram_data_IOBUF[18]_inst/T AB17 OBUFT (TriStatE_obuft_T_O) 3.542 13.002 r ext_ram_data_IOBUF[18]_inst/OBUFT/O net (fo=1, unset) 0.000 13.002 ext_ram_data[18] AB17 r ext_ram_data[18] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -13.002 ------------------------------------------------------------------- slack 0.353 Slack (MET) : 0.357ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[520]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.324ns (logic 0.792ns (4.099%) route 18.532ns (95.901%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.313ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.532 16.501 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X77Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.625 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[520]_i_2/O net (fo=1, routed) 0.000 16.625 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[520]_i_2_n_0 SLICE_X77Y145 MUXF7 (Prop_muxf7_I0_O) 0.212 16.837 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[520]_i_1/O net (fo=1, routed) 0.000 16.837 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_597 SLICE_X77Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[520]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.535 17.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X77Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[520]/C clock pessimism -0.507 17.200 clock uncertainty -0.071 17.130 SLICE_X77Y145 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[520] ------------------------------------------------------------------- required time 17.194 arrival time -16.837 ------------------------------------------------------------------- slack 0.357 Slack (MET) : 0.359ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[17] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.316ns (logic 6.863ns (44.810%) route 8.453ns (55.190%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.071 9.449 base_ram_data_IOBUF[17]_inst/T M21 OBUFT (TriStatE_obuft_T_O) 3.546 12.995 r base_ram_data_IOBUF[17]_inst/OBUFT/O net (fo=1, unset) 0.000 12.995 base_ram_data[17] M21 r base_ram_data[17] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.995 ------------------------------------------------------------------- slack 0.359 Slack (MET) : 0.360ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.315ns (logic 6.861ns (44.798%) route 8.454ns (55.202%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[21]_inst/T M20 OBUFT (TriStatE_obuft_T_O) 3.544 12.994 r base_ram_data_IOBUF[21]_inst/OBUFT/O net (fo=1, unset) 0.000 12.994 base_ram_data[21] M20 r base_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.994 ------------------------------------------------------------------- slack 0.360 Slack (MET) : 0.371ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[937]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.302ns (logic 0.792ns (4.103%) route 18.510ns (95.897%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.321ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.510 16.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X78Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.603 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[937]_i_2/O net (fo=1, routed) 0.000 16.603 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[937]_i_2_n_0 SLICE_X78Y145 MUXF7 (Prop_muxf7_I0_O) 0.212 16.815 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[937]_i_1/O net (fo=1, routed) 0.000 16.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_180 SLICE_X78Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[937]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.527 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X78Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[937]/C clock pessimism -0.507 17.192 clock uncertainty -0.071 17.122 SLICE_X78Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[937] ------------------------------------------------------------------- required time 17.186 arrival time -16.815 ------------------------------------------------------------------- slack 0.371 Slack (MET) : 0.399ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.276ns (logic 6.887ns (45.082%) route 8.389ns (54.918%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.007 9.386 base_ram_data_IOBUF[3]_inst/T M25 OBUFT (TriStatE_obuft_T_O) 3.570 12.955 r base_ram_data_IOBUF[3]_inst/OBUFT/O net (fo=1, unset) 0.000 12.955 base_ram_data[3] M25 r base_ram_data[3] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.955 ------------------------------------------------------------------- slack 0.399 Slack (MET) : 0.422ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[0] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.253ns (logic 6.848ns (44.897%) route 8.405ns (55.103%)) Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.219 7.595 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] SLICE_X5Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.719 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O net (fo=1, routed) 1.682 9.401 base_ram_be_n_OBUF[0] L20 OBUF (Prop_obuf_I_O) 3.531 12.932 r base_ram_be_n_OBUF[0]_inst/O net (fo=0) 0.000 12.932 base_ram_be_n[0] L20 r base_ram_be_n[0] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.932 ------------------------------------------------------------------- slack 0.422 Slack (MET) : 0.427ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.248ns (logic 6.860ns (44.990%) route 8.388ns (55.010%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.113 9.384 ext_ram_data_IOBUF[22]_inst/T Y15 OBUFT (TriStatE_obuft_T_O) 3.543 12.927 r ext_ram_data_IOBUF[22]_inst/OBUFT/O net (fo=1, unset) 0.000 12.927 ext_ram_data[22] Y15 r ext_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.927 ------------------------------------------------------------------- slack 0.427 Slack (MET) : 0.428ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[617]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.253ns (logic 0.792ns (4.114%) route 18.461ns (95.886%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.313ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.461 16.430 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X77Y143 LUT4 (Prop_lut4_I2_O) 0.124 16.554 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[617]_i_2/O net (fo=1, routed) 0.000 16.554 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[617]_i_2_n_0 SLICE_X77Y143 MUXF7 (Prop_muxf7_I0_O) 0.212 16.766 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[617]_i_1/O net (fo=1, routed) 0.000 16.766 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_500 SLICE_X77Y143 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[617]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.535 17.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X77Y143 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[617]/C clock pessimism -0.507 17.200 clock uncertainty -0.071 17.130 SLICE_X77Y143 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[617] ------------------------------------------------------------------- required time 17.194 arrival time -16.766 ------------------------------------------------------------------- slack 0.428 Slack (MET) : 0.429ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[16] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.245ns (logic 6.844ns (44.894%) route 8.401ns (55.106%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 3.019 9.398 base_ram_data_IOBUF[16]_inst/T P21 OBUFT (TriStatE_obuft_T_O) 3.527 12.925 r base_ram_data_IOBUF[16]_inst/OBUFT/O net (fo=1, unset) 0.000 12.925 base_ram_data[16] P21 r base_ram_data[16] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.925 ------------------------------------------------------------------- slack 0.429 Slack (MET) : 0.432ns (required time - arrival time) Source: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/crc_reg_reg[19]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.243ns (logic 5.206ns (27.054%) route 14.037ns (72.946%)) Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=6 LUT6=6) Clock Path Skew: -0.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.180ns = ( 17.820 - 20.000 ) Source Clock Delay (SCD): -2.403ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.939 -2.403 u_matmul_axi_slave/mult_inst[3].u_mult/sys_clk SLICE_X24Y91 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y91 FDRE (Prop_fdre_C_Q) 0.419 -1.984 r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[3]/Q net (fo=1, routed) 0.845 -1.138 u_matmul_axi_slave/mult_inst[2].u_mult/Q[3] SLICE_X22Y91 LUT2 (Prop_lut2_I1_O) 0.297 -0.841 r u_matmul_axi_slave/mult_inst[2].u_mult/b1_c_reg_r1_0_15_0_5_i_28/O net (fo=1, routed) 0.000 -0.841 u_matmul_axi_slave/mult_inst[2].u_mult/b1_c_reg_r1_0_15_0_5_i_28_n_0 SLICE_X22Y91 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 -0.465 r u_matmul_axi_slave/mult_inst[2].u_mult/b1_c_reg_r1_0_15_0_5_i_22/CO[3] net (fo=1, routed) 0.000 -0.465 u_matmul_axi_slave/mult_inst[2].u_mult/b1_c_reg_r1_0_15_0_5_i_22_n_0 SLICE_X22Y92 CARRY4 (Prop_carry4_CI_O[0]) 0.219 -0.246 r u_matmul_axi_slave/mult_inst[2].u_mult/b1_c_reg_r1_0_15_0_5_i_27/O[0] net (fo=1, routed) 1.005 0.758 u_matmul_axi_slave/calc_c_result0[4] SLICE_X21Y90 LUT2 (Prop_lut2_I1_O) 0.295 1.053 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_17/O net (fo=1, routed) 0.000 1.053 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_17_n_0 SLICE_X21Y90 CARRY4 (Prop_carry4_S[0]_O[1]) 0.424 1.477 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] net (fo=8, routed) 0.827 2.304 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 SLICE_X24Y92 LUT4 (Prop_lut4_I1_O) 0.298 2.602 r u_matmul_axi_slave/crc_reg[23]_i_43/O net (fo=7, routed) 0.630 3.232 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 SLICE_X24Y93 LUT5 (Prop_lut5_I1_O) 0.358 3.590 r u_matmul_axi_slave/crc_reg[27]_i_17/O net (fo=10, routed) 0.892 4.482 u_matmul_axi_slave/crc32_word_next_return7[3] SLICE_X27Y92 LUT6 (Prop_lut6_I1_O) 0.332 4.814 r u_matmul_axi_slave/crc_reg[23]_i_34/O net (fo=10, routed) 1.132 5.946 u_matmul_axi_slave/crc32_word_next_return4[5] SLICE_X30Y94 LUT5 (Prop_lut5_I2_O) 0.152 6.098 r u_matmul_axi_slave/crc_reg[27]_i_13/O net (fo=11, routed) 0.848 6.946 u_matmul_axi_slave/crc32_word_next_return1[3] SLICE_X27Y95 LUT6 (Prop_lut6_I3_O) 0.326 7.272 r u_matmul_axi_slave/crc_reg[12]_i_49/O net (fo=9, routed) 0.681 7.953 u_matmul_axi_slave/crc32_word_next0_return10[4] SLICE_X29Y96 LUT5 (Prop_lut5_I1_O) 0.152 8.105 r u_matmul_axi_slave/crc_reg[23]_i_21/O net (fo=12, routed) 0.729 8.833 u_matmul_axi_slave/crc32_word_next0_return7[2] SLICE_X30Y98 LUT6 (Prop_lut6_I3_O) 0.332 9.165 r u_matmul_axi_slave/crc_reg[12]_i_20/O net (fo=11, routed) 1.049 10.214 u_matmul_axi_slave/crc32_word_next0_return4[3] SLICE_X25Y95 LUT6 (Prop_lut6_I3_O) 0.124 10.338 r u_matmul_axi_slave/crc_reg[20]_i_20/O net (fo=10, routed) 1.041 11.380 u_matmul_axi_slave/crc32_word_next0_return1[4] SLICE_X24Y97 LUT5 (Prop_lut5_I2_O) 0.124 11.504 r u_matmul_axi_slave/crc_reg[12]_i_10/O net (fo=10, routed) 0.872 12.375 u_matmul_axi_slave/crc_reg[12]_i_10_n_0 SLICE_X20Y97 LUT6 (Prop_lut6_I5_O) 0.124 12.499 r u_matmul_axi_slave/crc_reg[31]_i_10/O net (fo=14, routed) 1.275 13.775 u_matmul_axi_slave/crc32_word_next1_return7[7] SLICE_X20Y103 LUT5 (Prop_lut5_I3_O) 0.150 13.925 r u_matmul_axi_slave/crc_reg[20]_i_3/O net (fo=13, routed) 1.383 15.308 u_matmul_axi_slave/crc32_word_next1_return4[5] SLICE_X22Y111 LUT5 (Prop_lut5_I4_O) 0.356 15.664 r u_matmul_axi_slave/crc_reg[19]_i_2/O net (fo=1, routed) 0.828 16.492 u_matmul_axi_slave/crc32_word_next1_return3[25] SLICE_X23Y111 LUT6 (Prop_lut6_I0_O) 0.348 16.840 r u_matmul_axi_slave/crc_reg[19]_i_1/O net (fo=1, routed) 0.000 16.840 u_matmul_axi_slave/crc32_word_next1_return[19] SLICE_X23Y111 FDSE r u_matmul_axi_slave/crc_reg_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.648 17.820 u_matmul_axi_slave/sys_clk SLICE_X23Y111 FDSE r u_matmul_axi_slave/crc_reg_reg[19]/C clock pessimism -0.507 17.313 clock uncertainty -0.071 17.243 SLICE_X23Y111 FDSE (Setup_fdse_C_D) 0.029 17.272 u_matmul_axi_slave/crc_reg_reg[19] ------------------------------------------------------------------- required time 17.272 arrival time -16.840 ------------------------------------------------------------------- slack 0.432 Slack (MET) : 0.433ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[682]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.235ns (logic 0.792ns (4.118%) route 18.442ns (95.882%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.326ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.306ns = ( 17.694 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.442 16.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X82Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.536 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[682]_i_2/O net (fo=1, routed) 0.000 16.536 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[682]_i_2_n_0 SLICE_X82Y145 MUXF7 (Prop_muxf7_I0_O) 0.212 16.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[682]_i_1/O net (fo=1, routed) 0.000 16.748 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_435 SLICE_X82Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[682]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.522 17.694 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X82Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[682]/C clock pessimism -0.507 17.187 clock uncertainty -0.071 17.117 SLICE_X82Y145 FDCE (Setup_fdce_C_D) 0.064 17.181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[682] ------------------------------------------------------------------- required time 17.181 arrival time -16.748 ------------------------------------------------------------------- slack 0.433 Slack (MET) : 0.444ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[989]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.252ns (logic 0.580ns (3.013%) route 18.672ns (96.987%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.672 16.642 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X74Y139 LUT5 (Prop_lut5_I3_O) 0.124 16.766 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[989]_i_1/O net (fo=1, routed) 0.000 16.766 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_128 SLICE_X74Y139 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[989]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.536 17.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X74Y139 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[989]/C clock pessimism -0.507 17.201 clock uncertainty -0.071 17.131 SLICE_X74Y139 FDCE (Setup_fdce_C_D) 0.079 17.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[989] ------------------------------------------------------------------- required time 17.210 arrival time -16.766 ------------------------------------------------------------------- slack 0.444 Slack (MET) : 0.446ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.284ns (logic 0.821ns (4.257%) route 18.463ns (95.742%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.313ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.463 16.432 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X76Y143 LUT4 (Prop_lut4_I2_O) 0.124 16.556 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[812]_i_2/O net (fo=1, routed) 0.000 16.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[812]_i_2_n_0 SLICE_X76Y143 MUXF7 (Prop_muxf7_I0_O) 0.241 16.797 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O net (fo=1, routed) 0.000 16.797 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_305 SLICE_X76Y143 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.535 17.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X76Y143 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/C clock pessimism -0.507 17.200 clock uncertainty -0.071 17.130 SLICE_X76Y143 FDCE (Setup_fdce_C_D) 0.113 17.243 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] ------------------------------------------------------------------- required time 17.243 arrival time -16.797 ------------------------------------------------------------------- slack 0.446 Slack (MET) : 0.453ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[25] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.222ns (logic 6.870ns (45.135%) route 8.352ns (54.865%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 3.077 9.348 ext_ram_data_IOBUF[25]_inst/T AC17 OBUFT (TriStatE_obuft_T_O) 3.553 12.902 r ext_ram_data_IOBUF[25]_inst/OBUFT/O net (fo=1, unset) 0.000 12.902 ext_ram_data[25] AC17 r ext_ram_data[25] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.902 ------------------------------------------------------------------- slack 0.453 Slack (MET) : 0.495ns (required time - arrival time) Source: u_snix_axil_cdma_mux_8ch/ext_wr_word_addr_r_reg[5]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[23] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.281ns (logic 5.106ns (33.413%) route 10.175ns (66.586%)) Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1 RAMD32=1) Output Delay: 0.300ns Clock Path Skew: -3.854ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.422ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.920 -2.422 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X25Y75 FDRE r u_snix_axil_cdma_mux_8ch/ext_wr_word_addr_r_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y75 FDRE (Prop_fdre_C_Q) 0.419 -2.003 r u_snix_axil_cdma_mux_8ch/ext_wr_word_addr_r_reg[5]/Q net (fo=3, routed) 0.821 -1.182 u_snix_axil_cdma_mux_8ch/ext_wr_word_addr_r_reg_n_0_[5] SLICE_X25Y74 LUT4 (Prop_lut4_I3_O) 0.299 -0.883 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O net (fo=4, routed) 1.108 0.226 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] SLICE_X23Y75 LUT6 (Prop_lut6_I4_O) 0.124 0.350 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O net (fo=136, routed) 0.574 0.923 u_snix_axil_cdma_mux_8ch/ADDRA[2] SLICE_X23Y75 LUT6 (Prop_lut6_I3_O) 0.124 1.047 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O net (fo=167, routed) 1.350 2.397 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 SLICE_X18Y74 RAMD32 (Prop_ramd32_RADR0_O) 0.124 2.521 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC_D1/O net (fo=1, routed) 0.947 3.468 u_snix_axil_cdma_mux_8ch/ep_rd_c1[23] SLICE_X20Y78 LUT6 (Prop_lut6_I0_O) 0.124 3.592 r u_snix_axil_cdma_mux_8ch/stream_wdata[23]_i_4/O net (fo=1, routed) 0.298 3.890 u_snix_axil_cdma_mux_8ch/stream_wdata[23]_i_4_n_0 SLICE_X21Y76 LUT5 (Prop_lut5_I4_O) 0.124 4.014 r u_snix_axil_cdma_mux_8ch/stream_wdata[23]_i_3/O net (fo=1, routed) 0.529 4.543 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[21] SLICE_X24Y76 LUT6 (Prop_lut6_I0_O) 0.124 4.667 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/stream_wdata[23]_i_2/O net (fo=3, routed) 1.225 5.892 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[23] SLICE_X7Y73 LUT3 (Prop_lut3_I0_O) 0.124 6.016 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[23]_inst_i_1/O net (fo=2, routed) 3.323 9.340 base_ram_data_IOBUF[23]_inst/I N21 OBUFT (Prop_obuft_I_O) 3.520 12.859 r base_ram_data_IOBUF[23]_inst/OBUFT/O net (fo=1, unset) 0.000 12.859 base_ram_data[23] N21 r base_ram_data[23] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.859 ------------------------------------------------------------------- slack 0.495 Slack (MET) : 0.499ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[31] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.176ns (logic 6.863ns (45.225%) route 8.313ns (54.775%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 2.931 9.309 base_ram_data_IOBUF[31]_inst/T M22 OBUFT (TriStatE_obuft_T_O) 3.546 12.855 r base_ram_data_IOBUF[31]_inst/OBUFT/O net (fo=1, unset) 0.000 12.855 base_ram_data[31] M22 r base_ram_data[31] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.855 ------------------------------------------------------------------- slack 0.499 Slack (MET) : 0.518ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[28] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.157ns (logic 6.853ns (45.212%) route 8.304ns (54.788%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 2.922 9.301 base_ram_data_IOBUF[28]_inst/T N22 OBUFT (TriStatE_obuft_T_O) 3.536 12.837 r base_ram_data_IOBUF[28]_inst/OBUFT/O net (fo=1, unset) 0.000 12.837 base_ram_data[28] N22 r base_ram_data[28] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.837 ------------------------------------------------------------------- slack 0.518 Slack (MET) : 0.530ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1068]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.200ns (logic 0.789ns (4.109%) route 18.411ns (95.891%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.313ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.411 16.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X76Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.504 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1068]_i_2/O net (fo=1, routed) 0.000 16.504 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1068]_i_2_n_0 SLICE_X76Y144 MUXF7 (Prop_muxf7_I0_O) 0.209 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1068]_i_1/O net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_49 SLICE_X76Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1068]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.535 17.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X76Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1068]/C clock pessimism -0.507 17.200 clock uncertainty -0.071 17.130 SLICE_X76Y144 FDCE (Setup_fdce_C_D) 0.113 17.243 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1068] ------------------------------------------------------------------- required time 17.243 arrival time -16.713 ------------------------------------------------------------------- slack 0.530 Slack (MET) : 0.532ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[20] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.143ns (logic 6.877ns (45.411%) route 8.267ns (54.589%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 2.992 9.263 ext_ram_data_IOBUF[20]_inst/T AD18 OBUFT (TriStatE_obuft_T_O) 3.560 12.823 r ext_ram_data_IOBUF[20]_inst/OBUFT/O net (fo=1, unset) 0.000 12.823 ext_ram_data[20] AD18 r ext_ram_data[20] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.823 ------------------------------------------------------------------- slack 0.532 Slack (MET) : 0.544ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1084]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.189ns (logic 0.789ns (4.112%) route 18.400ns (95.888%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.310ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.290ns = ( 17.710 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.400 16.369 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X74Y143 LUT4 (Prop_lut4_I2_O) 0.124 16.493 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1084]_i_2/O net (fo=1, routed) 0.000 16.493 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1084]_i_2_n_0 SLICE_X74Y143 MUXF7 (Prop_muxf7_I0_O) 0.209 16.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1084]_i_1/O net (fo=1, routed) 0.000 16.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_33 SLICE_X74Y143 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1084]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.538 17.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X74Y143 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1084]/C clock pessimism -0.507 17.203 clock uncertainty -0.071 17.133 SLICE_X74Y143 FDCE (Setup_fdce_C_D) 0.113 17.246 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1084] ------------------------------------------------------------------- required time 17.246 arrival time -16.702 ------------------------------------------------------------------- slack 0.544 Slack (MET) : 0.547ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[22] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.128ns (logic 6.869ns (45.407%) route 8.259ns (54.593%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 2.877 9.255 base_ram_data_IOBUF[22]_inst/T N24 OBUFT (TriStatE_obuft_T_O) 3.552 12.808 r base_ram_data_IOBUF[22]_inst/OBUFT/O net (fo=1, unset) 0.000 12.808 base_ram_data[22] N24 r base_ram_data[22] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.808 ------------------------------------------------------------------- slack 0.547 Slack (MET) : 0.551ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[10] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.124ns (logic 6.900ns (45.622%) route 8.224ns (54.378%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 2.950 9.220 ext_ram_data_IOBUF[10]_inst/T W26 OBUFT (TriStatE_obuft_T_O) 3.583 12.803 r ext_ram_data_IOBUF[10]_inst/OBUFT/O net (fo=1, unset) 0.000 12.803 ext_ram_data[10] W26 r ext_ram_data[10] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.803 ------------------------------------------------------------------- slack 0.551 Slack (MET) : 0.556ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[27] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.118ns (logic 6.840ns (45.240%) route 8.279ns (54.760%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 2.897 9.275 base_ram_data_IOBUF[27]_inst/T P20 OBUFT (TriStatE_obuft_T_O) 3.523 12.798 r base_ram_data_IOBUF[27]_inst/OBUFT/O net (fo=1, unset) 0.000 12.798 base_ram_data[27] P20 r base_ram_data[27] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.798 ------------------------------------------------------------------- slack 0.556 Slack (MET) : 0.561ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[13] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.113ns (logic 6.896ns (45.630%) route 8.217ns (54.370%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 2.943 9.214 ext_ram_data_IOBUF[13]_inst/T U25 OBUFT (TriStatE_obuft_T_O) 3.579 12.793 r ext_ram_data_IOBUF[13]_inst/OBUFT/O net (fo=1, unset) 0.000 12.793 ext_ram_data[13] U25 r ext_ram_data[13] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.793 ------------------------------------------------------------------- slack 0.561 Slack (MET) : 0.563ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_be_n[2] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.112ns (logic 6.852ns (45.343%) route 8.260ns (54.657%)) Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 2.074 7.450 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] SLICE_X5Y127 LUT6 (Prop_lut6_I5_O) 0.124 7.574 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[2]_inst_i_1/O net (fo=1, routed) 1.682 9.256 base_ram_be_n_OBUF[2] L23 OBUF (Prop_obuf_I_O) 3.535 12.791 r base_ram_be_n_OBUF[2]_inst/O net (fo=0) 0.000 12.791 base_ram_be_n[2] L23 r base_ram_be_n[2] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.791 ------------------------------------------------------------------- slack 0.563 Slack (MET) : 0.563ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[14] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.112ns (logic 6.897ns (45.638%) route 8.215ns (54.362%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 2.941 9.211 ext_ram_data_IOBUF[14]_inst/T U26 OBUFT (TriStatE_obuft_T_O) 3.580 12.791 r ext_ram_data_IOBUF[14]_inst/OBUFT/O net (fo=1, unset) 0.000 12.791 ext_ram_data[14] U26 r ext_ram_data[14] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.791 ------------------------------------------------------------------- slack 0.563 Slack (MET) : 0.564ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[15] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.111ns (logic 6.875ns (45.500%) route 8.235ns (54.500%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 2.961 9.232 ext_ram_data_IOBUF[15]_inst/T U24 OBUFT (TriStatE_obuft_T_O) 3.558 12.790 r ext_ram_data_IOBUF[15]_inst/OBUFT/O net (fo=1, unset) 0.000 12.790 ext_ram_data[15] U24 r ext_ram_data[15] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.790 ------------------------------------------------------------------- slack 0.564 Slack (MET) : 0.572ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[29] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.102ns (logic 6.880ns (45.554%) route 8.223ns (54.446%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 2.948 9.219 ext_ram_data_IOBUF[29]_inst/T AC21 OBUFT (TriStatE_obuft_T_O) 3.563 12.782 r ext_ram_data_IOBUF[29]_inst/OBUFT/O net (fo=1, unset) 0.000 12.782 ext_ram_data[29] AC21 r ext_ram_data[29] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.782 ------------------------------------------------------------------- slack 0.572 Slack (MET) : 0.574ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[680]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.093ns (logic 0.792ns (4.148%) route 18.301ns (95.852%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.326ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.306ns = ( 17.694 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.301 16.271 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X82Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.395 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[680]_i_2/O net (fo=1, routed) 0.000 16.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[680]_i_2_n_0 SLICE_X82Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.607 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[680]_i_1/O net (fo=1, routed) 0.000 16.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_437 SLICE_X82Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[680]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.522 17.694 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X82Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[680]/C clock pessimism -0.507 17.187 clock uncertainty -0.071 17.117 SLICE_X82Y144 FDCE (Setup_fdce_C_D) 0.064 17.181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[680] ------------------------------------------------------------------- required time 17.181 arrival time -16.607 ------------------------------------------------------------------- slack 0.574 Slack (MET) : 0.576ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[19] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.099ns (logic 6.874ns (45.528%) route 8.225ns (54.472%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 2.950 9.221 ext_ram_data_IOBUF[19]_inst/T AC18 OBUFT (TriStatE_obuft_T_O) 3.557 12.778 r ext_ram_data_IOBUF[19]_inst/OBUFT/O net (fo=1, unset) 0.000 12.778 ext_ram_data[19] AC18 r ext_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.778 ------------------------------------------------------------------- slack 0.576 Slack (MET) : 0.582ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[29] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.093ns (logic 6.868ns (45.504%) route 8.225ns (54.496%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 2.843 9.221 base_ram_data_IOBUF[29]_inst/T N23 OBUFT (TriStatE_obuft_T_O) 3.551 12.772 r base_ram_data_IOBUF[29]_inst/OBUFT/O net (fo=1, unset) 0.000 12.772 base_ram_data[29] N23 r base_ram_data[29] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.772 ------------------------------------------------------------------- slack 0.582 Slack (MET) : 0.585ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[19] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.090ns (logic 6.835ns (45.291%) route 8.256ns (54.709%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 2.874 9.252 base_ram_data_IOBUF[19]_inst/T P19 OBUFT (TriStatE_obuft_T_O) 3.518 12.770 r base_ram_data_IOBUF[19]_inst/OBUFT/O net (fo=1, unset) 0.000 12.770 base_ram_data[19] P19 r base_ram_data[19] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.770 ------------------------------------------------------------------- slack 0.585 Slack (MET) : 0.585ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[4] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.090ns (logic 6.909ns (45.786%) route 8.181ns (54.214%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O net (fo=32, routed) 2.906 9.177 ext_ram_data_IOBUF[4]_inst/T AF22 OBUFT (TriStatE_obuft_T_O) 3.592 12.769 r ext_ram_data_IOBUF[4]_inst/OBUFT/O net (fo=1, unset) 0.000 12.769 ext_ram_data[4] AF22 r ext_ram_data[4] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.769 ------------------------------------------------------------------- slack 0.585 Slack (MET) : 0.587ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[938]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 19.085ns (logic 0.818ns (4.286%) route 18.267ns (95.714%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: -0.321ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q net (fo=1088, routed) 18.267 16.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 SLICE_X78Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.361 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[938]_i_2/O net (fo=1, routed) 0.000 16.361 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[938]_i_2_n_0 SLICE_X78Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.599 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[938]_i_1/O net (fo=1, routed) 0.000 16.599 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_179 SLICE_X78Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[938]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.527 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk SLICE_X78Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[938]/C clock pessimism -0.507 17.192 clock uncertainty -0.071 17.122 SLICE_X78Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[938] ------------------------------------------------------------------- required time 17.186 arrival time -16.599 ------------------------------------------------------------------- slack 0.587 Slack (MET) : 0.596ns (required time - arrival time) Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[7] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 15.079ns (logic 6.877ns (45.604%) route 8.202ns (54.396%)) Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O net (fo=32, routed) 2.821 9.199 base_ram_data_IOBUF[7]_inst/T P25 OBUFT (TriStatE_obuft_T_O) 3.560 12.758 r base_ram_data_IOBUF[7]_inst/OBUFT/O net (fo=1, unset) 0.000 12.758 base_ram_data[7] P25 r base_ram_data[7] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 clock pessimism -0.601 13.725 clock uncertainty -0.071 13.654 output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 arrival time -12.758 ------------------------------------------------------------------- slack 0.596 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X5Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X5Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y28 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y28 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB36_X7Y18 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X5Y11 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X5Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y7 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X5Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X5Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X7Y18 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[13]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[14]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[15]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[16]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[17]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[18]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[19]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y63 u_cdma_matmul_bridge/load_next_idx_reg[1]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[20]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[21]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[22]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[23]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y69 u_cdma_matmul_bridge/load_next_idx_reg[24]/C Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X141Y157 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[105][11]/C Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y61 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y61 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: cpu_clk To Clock: cpu_clk Setup : 0 Failing Endpoints, Worst Slack 26.490ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 26.490ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.236ns (logic 0.580ns (17.922%) route 2.656ns (82.078%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.769 1.105 u_Axi_CDC/arFifo/p_0_in SLICE_X17Y47 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X17Y47 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 27.595 arrival time -1.105 ------------------------------------------------------------------- slack 26.490 Slack (MET) : 26.490ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.236ns (logic 0.580ns (17.922%) route 2.656ns (82.078%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.769 1.105 u_Axi_CDC/arFifo/p_0_in SLICE_X17Y47 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X17Y47 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 27.595 arrival time -1.105 ------------------------------------------------------------------- slack 26.490 Slack (MET) : 26.490ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.236ns (logic 0.580ns (17.922%) route 2.656ns (82.078%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.769 1.105 u_Axi_CDC/arFifo/p_0_in SLICE_X17Y47 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X17Y47 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 27.595 arrival time -1.105 ------------------------------------------------------------------- slack 26.490 Slack (MET) : 26.490ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.236ns (logic 0.580ns (17.922%) route 2.656ns (82.078%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.769 1.105 u_Axi_CDC/arFifo/p_0_in SLICE_X17Y47 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X17Y47 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 27.595 arrival time -1.105 ------------------------------------------------------------------- slack 26.490 Slack (MET) : 26.490ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.236ns (logic 0.580ns (17.922%) route 2.656ns (82.078%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.769 1.105 u_Axi_CDC/arFifo/p_0_in SLICE_X17Y47 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/arFifo/cpu_clk SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X17Y47 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 27.595 arrival time -1.105 ------------------------------------------------------------------- slack 26.490 Slack (MET) : 26.685ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.085ns (logic 0.580ns (18.801%) route 2.505ns (81.199%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.617 0.953 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y45 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X16Y45 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 27.638 arrival time -0.953 ------------------------------------------------------------------- slack 26.685 Slack (MET) : 26.685ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.085ns (logic 0.580ns (18.801%) route 2.505ns (81.199%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.617 0.953 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y45 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X16Y45 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 27.638 arrival time -0.953 ------------------------------------------------------------------- slack 26.685 Slack (MET) : 26.685ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.085ns (logic 0.580ns (18.801%) route 2.505ns (81.199%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.617 0.953 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y45 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X16Y45 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 27.638 arrival time -0.953 ------------------------------------------------------------------- slack 26.685 Slack (MET) : 26.727ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.085ns (logic 0.580ns (18.801%) route 2.505ns (81.199%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.617 0.953 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y45 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X16Y45 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 27.680 arrival time -0.953 ------------------------------------------------------------------- slack 26.727 Slack (MET) : 26.727ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.085ns (logic 0.580ns (18.801%) route 2.505ns (81.199%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.617 0.953 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y45 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X16Y45 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 27.680 arrival time -0.953 ------------------------------------------------------------------- slack 26.727 Slack (MET) : 26.727ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 3.085ns (logic 0.580ns (18.801%) route 2.505ns (81.199%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.617 0.953 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y45 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X16Y45 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 27.680 arrival time -0.953 ------------------------------------------------------------------- slack 26.727 Slack (MET) : 26.870ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.901ns (logic 0.580ns (19.994%) route 2.321ns (80.006%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.433 0.769 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y45 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X10Y45 FDCE (Recov_fdce_C_CLR) -0.361 27.639 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 27.639 arrival time -0.769 ------------------------------------------------------------------- slack 26.870 Slack (MET) : 26.870ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.901ns (logic 0.580ns (19.994%) route 2.321ns (80.006%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.433 0.769 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y45 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X10Y45 FDCE (Recov_fdce_C_CLR) -0.361 27.639 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 27.639 arrival time -0.769 ------------------------------------------------------------------- slack 26.870 Slack (MET) : 26.870ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.901ns (logic 0.580ns (19.994%) route 2.321ns (80.006%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.433 0.769 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y45 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X10Y45 FDCE (Recov_fdce_C_CLR) -0.361 27.639 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 27.639 arrival time -0.769 ------------------------------------------------------------------- slack 26.870 Slack (MET) : 26.912ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.901ns (logic 0.580ns (19.994%) route 2.321ns (80.006%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.433 0.769 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y45 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X10Y45 FDCE (Recov_fdce_C_CLR) -0.319 27.681 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 27.681 arrival time -0.769 ------------------------------------------------------------------- slack 26.912 Slack (MET) : 26.912ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.901ns (logic 0.580ns (19.994%) route 2.321ns (80.006%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.433 0.769 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y45 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X10Y45 FDCE (Recov_fdce_C_CLR) -0.319 27.681 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 27.681 arrival time -0.769 ------------------------------------------------------------------- slack 26.912 Slack (MET) : 26.912ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.901ns (logic 0.580ns (19.994%) route 2.321ns (80.006%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.433 0.769 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y45 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X10Y45 FDCE (Recov_fdce_C_CLR) -0.319 27.681 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 27.681 arrival time -0.769 ------------------------------------------------------------------- slack 26.912 Slack (MET) : 27.000ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 27.594 arrival time -0.594 ------------------------------------------------------------------- slack 27.000 Slack (MET) : 27.000ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 27.594 arrival time -0.594 ------------------------------------------------------------------- slack 27.000 Slack (MET) : 27.000ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 27.594 arrival time -0.594 ------------------------------------------------------------------- slack 27.000 Slack (MET) : 27.000ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] ------------------------------------------------------------------- required time 27.594 arrival time -0.594 ------------------------------------------------------------------- slack 27.000 Slack (MET) : 27.000ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 27.594 arrival time -0.594 ------------------------------------------------------------------- slack 27.000 Slack (MET) : 27.000ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 27.594 arrival time -0.594 ------------------------------------------------------------------- slack 27.000 Slack (MET) : 27.000ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] ------------------------------------------------------------------- required time 27.594 arrival time -0.594 ------------------------------------------------------------------- slack 27.000 Slack (MET) : 27.162ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.688ns (logic 0.718ns (26.710%) route 1.970ns (73.290%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 1.155 0.477 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X14Y43 FDCE (Recov_fdce_C_CLR) -0.361 27.639 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 27.639 arrival time -0.477 ------------------------------------------------------------------- slack 27.162 Slack (MET) : 27.204ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.688ns (logic 0.718ns (26.710%) route 1.970ns (73.290%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 1.155 0.477 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X14Y43 FDCE (Recov_fdce_C_CLR) -0.319 27.681 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 27.681 arrival time -0.477 ------------------------------------------------------------------- slack 27.204 Slack (MET) : 27.204ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.688ns (logic 0.718ns (26.710%) route 1.970ns (73.290%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 1.155 0.477 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X14Y43 FDCE (Recov_fdce_C_CLR) -0.319 27.681 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 27.681 arrival time -0.477 ------------------------------------------------------------------- slack 27.204 Slack (MET) : 27.204ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.688ns (logic 0.718ns (26.710%) route 1.970ns (73.290%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 1.155 0.477 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X14Y43 FDCE (Recov_fdce_C_CLR) -0.319 27.681 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 27.681 arrival time -0.477 ------------------------------------------------------------------- slack 27.204 Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 27.595 arrival time -0.295 ------------------------------------------------------------------- slack 27.300 Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 27.595 arrival time -0.295 ------------------------------------------------------------------- slack 27.300 Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 27.595 arrival time -0.295 ------------------------------------------------------------------- slack 27.300 Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 27.595 arrival time -0.295 ------------------------------------------------------------------- slack 27.300 Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 27.595 arrival time -0.295 ------------------------------------------------------------------- slack 27.300 Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 27.595 arrival time -0.295 ------------------------------------------------------------------- slack 27.300 Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 27.595 arrival time -0.295 ------------------------------------------------------------------- slack 27.300 Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 27.595 arrival time -0.295 ------------------------------------------------------------------- slack 27.300 Slack (MET) : 27.439ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.368ns (logic 0.718ns (30.323%) route 1.650ns (69.677%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.835 0.156 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X13Y43 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 27.595 arrival time -0.156 ------------------------------------------------------------------- slack 27.439 Slack (MET) : 27.439ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.368ns (logic 0.718ns (30.323%) route 1.650ns (69.677%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.835 0.156 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X13Y43 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 27.595 arrival time -0.156 ------------------------------------------------------------------- slack 27.439 Slack (MET) : 27.439ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.368ns (logic 0.718ns (30.323%) route 1.650ns (69.677%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.835 0.156 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X13Y43 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 27.595 arrival time -0.156 ------------------------------------------------------------------- slack 27.439 Slack (MET) : 27.439ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.368ns (logic 0.718ns (30.323%) route 1.650ns (69.677%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.212ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=30, routed) 0.835 0.156 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X13Y43 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 27.595 arrival time -0.156 ------------------------------------------------------------------- slack 27.439 Slack (MET) : 27.470ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 27.638 arrival time -0.168 ------------------------------------------------------------------- slack 27.470 Slack (MET) : 27.470ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 27.638 arrival time -0.168 ------------------------------------------------------------------- slack 27.470 Slack (MET) : 27.470ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 27.638 arrival time -0.168 ------------------------------------------------------------------- slack 27.470 Slack (MET) : 27.470ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 27.638 arrival time -0.168 ------------------------------------------------------------------- slack 27.470 Slack (MET) : 27.512ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 27.680 arrival time -0.168 ------------------------------------------------------------------- slack 27.512 Slack (MET) : 27.512ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 27.680 arrival time -0.168 ------------------------------------------------------------------- slack 27.512 Slack (MET) : 27.512ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 27.680 arrival time -0.168 ------------------------------------------------------------------- slack 27.512 Slack (MET) : 27.512ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.418 28.073 clock uncertainty -0.074 27.999 SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 27.680 arrival time -0.168 ------------------------------------------------------------------- slack 27.512 Slack (MET) : 27.560ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.211ns (logic 0.580ns (26.238%) route 1.631ns (73.762%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.743 0.079 u_Axi_CDC/awFifo/p_0_in SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/cpu_clk SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X10Y44 FDCE (Recov_fdce_C_CLR) -0.361 27.639 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 27.639 arrival time -0.079 ------------------------------------------------------------------- slack 27.560 Slack (MET) : 27.560ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) Data Path Delay: 2.211ns (logic 0.580ns (26.238%) route 1.631ns (73.762%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.117ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) Source Clock Delay (SCD): -2.132ns Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.743 0.079 u_Axi_CDC/awFifo/p_0_in SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r K21 0.000 30.323 r clk (IN) net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/cpu_clk SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.418 28.074 clock uncertainty -0.074 28.000 SLICE_X10Y44 FDCE (Recov_fdce_C_CLR) -0.361 27.639 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 27.639 arrival time -0.079 ------------------------------------------------------------------- slack 27.560 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk To Clock: sys_clk Setup : 0 Failing Endpoints, Worst Slack 8.003ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 8.003ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.331ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X63Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.524 17.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X63Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/C clock pessimism -0.514 17.182 clock uncertainty -0.071 17.111 SLICE_X63Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0] ------------------------------------------------------------------- required time 16.482 arrival time -8.480 ------------------------------------------------------------------- slack 8.003 Slack (MET) : 8.089ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.331ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.524 17.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X62Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/C clock pessimism -0.514 17.182 clock uncertainty -0.071 17.111 SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10] ------------------------------------------------------------------- required time 16.568 arrival time -8.480 ------------------------------------------------------------------- slack 8.089 Slack (MET) : 8.089ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.331ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.524 17.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X62Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/C clock pessimism -0.514 17.182 clock uncertainty -0.071 17.111 SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0] ------------------------------------------------------------------- required time 16.568 arrival time -8.480 ------------------------------------------------------------------- slack 8.089 Slack (MET) : 8.089ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.331ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.524 17.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X62Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/C clock pessimism -0.514 17.182 clock uncertainty -0.071 17.111 SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11] ------------------------------------------------------------------- required time 16.568 arrival time -8.480 ------------------------------------------------------------------- slack 8.089 Slack (MET) : 8.372ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X61Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/C clock pessimism -0.514 17.186 clock uncertainty -0.071 17.115 SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2] ------------------------------------------------------------------- required time 16.486 arrival time -8.114 ------------------------------------------------------------------- slack 8.372 Slack (MET) : 8.372ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X61Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/C clock pessimism -0.514 17.186 clock uncertainty -0.071 17.115 SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9] ------------------------------------------------------------------- required time 16.486 arrival time -8.114 ------------------------------------------------------------------- slack 8.372 Slack (MET) : 8.372ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X61Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/C clock pessimism -0.514 17.186 clock uncertainty -0.071 17.115 SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0] ------------------------------------------------------------------- required time 16.486 arrival time -8.114 ------------------------------------------------------------------- slack 8.372 Slack (MET) : 8.372ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X61Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/C clock pessimism -0.514 17.186 clock uncertainty -0.071 17.115 SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11] ------------------------------------------------------------------- required time 16.486 arrival time -8.114 ------------------------------------------------------------------- slack 8.372 Slack (MET) : 8.372ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X61Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/C clock pessimism -0.514 17.186 clock uncertainty -0.071 17.115 SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4] ------------------------------------------------------------------- required time 16.486 arrival time -8.114 ------------------------------------------------------------------- slack 8.372 Slack (MET) : 8.458ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X60Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/C clock pessimism -0.514 17.186 clock uncertainty -0.071 17.115 SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2] ------------------------------------------------------------------- required time 16.572 arrival time -8.114 ------------------------------------------------------------------- slack 8.458 Slack (MET) : 8.458ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X60Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/C clock pessimism -0.514 17.186 clock uncertainty -0.071 17.115 SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4] ------------------------------------------------------------------- required time 16.572 arrival time -8.114 ------------------------------------------------------------------- slack 8.458 Slack (MET) : 8.458ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X60Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/C clock pessimism -0.514 17.186 clock uncertainty -0.071 17.115 SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5] ------------------------------------------------------------------- required time 16.572 arrival time -8.114 ------------------------------------------------------------------- slack 8.458 Slack (MET) : 8.458ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X60Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/C clock pessimism -0.514 17.186 clock uncertainty -0.071 17.115 SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9] ------------------------------------------------------------------- required time 16.572 arrival time -8.114 ------------------------------------------------------------------- slack 8.458 Slack (MET) : 8.665ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.309ns (logic 0.668ns (6.480%) route 9.641ns (93.520%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.589 7.821 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X57Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X57Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/C clock pessimism -0.514 17.186 clock uncertainty -0.071 17.115 SLICE_X57Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4] ------------------------------------------------------------------- required time 16.486 arrival time -7.821 ------------------------------------------------------------------- slack 8.665 Slack (MET) : 8.751ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.309ns (logic 0.668ns (6.480%) route 9.641ns (93.520%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.589 7.821 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X56Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X56Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/C clock pessimism -0.514 17.186 clock uncertainty -0.071 17.115 SLICE_X56Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9] ------------------------------------------------------------------- required time 16.572 arrival time -7.821 ------------------------------------------------------------------- slack 8.751 Slack (MET) : 8.856ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.329ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.526 17.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X53Y169 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/C clock pessimism -0.514 17.184 clock uncertainty -0.071 17.113 SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10] ------------------------------------------------------------------- required time 16.484 arrival time -7.628 ------------------------------------------------------------------- slack 8.856 Slack (MET) : 8.856ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.329ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.526 17.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X53Y169 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/C clock pessimism -0.514 17.184 clock uncertainty -0.071 17.113 SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3] ------------------------------------------------------------------- required time 16.484 arrival time -7.628 ------------------------------------------------------------------- slack 8.856 Slack (MET) : 8.856ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.329ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.526 17.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X53Y169 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/C clock pessimism -0.514 17.184 clock uncertainty -0.071 17.113 SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8] ------------------------------------------------------------------- required time 16.484 arrival time -7.628 ------------------------------------------------------------------- slack 8.856 Slack (MET) : 8.896ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.696 17.867 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X159Y190 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/C clock pessimism -0.514 17.354 clock uncertainty -0.071 17.283 SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1] ------------------------------------------------------------------- required time 16.654 arrival time -7.758 ------------------------------------------------------------------- slack 8.896 Slack (MET) : 8.896ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.696 17.867 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X159Y190 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/C clock pessimism -0.514 17.354 clock uncertainty -0.071 17.283 SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2] ------------------------------------------------------------------- required time 16.654 arrival time -7.758 ------------------------------------------------------------------- slack 8.896 Slack (MET) : 8.896ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.696 17.867 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X159Y190 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/C clock pessimism -0.514 17.354 clock uncertainty -0.071 17.283 SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4] ------------------------------------------------------------------- required time 16.654 arrival time -7.758 ------------------------------------------------------------------- slack 8.896 Slack (MET) : 8.896ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.696 17.867 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X159Y190 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/C clock pessimism -0.514 17.354 clock uncertainty -0.071 17.283 SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5] ------------------------------------------------------------------- required time 16.654 arrival time -7.758 ------------------------------------------------------------------- slack 8.896 Slack (MET) : 8.923ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.040ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X149Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.814 17.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X149Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0]/C clock pessimism -0.514 17.472 clock uncertainty -0.071 17.402 SLICE_X149Y205 FDCE (Recov_fdce_C_CLR) -0.629 16.773 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0] ------------------------------------------------------------------- required time 16.773 arrival time -7.850 ------------------------------------------------------------------- slack 8.923 Slack (MET) : 8.923ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.040ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X149Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.814 17.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X149Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2]/C clock pessimism -0.514 17.472 clock uncertainty -0.071 17.402 SLICE_X149Y205 FDCE (Recov_fdce_C_CLR) -0.629 16.773 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2] ------------------------------------------------------------------- required time 16.773 arrival time -7.850 ------------------------------------------------------------------- slack 8.923 Slack (MET) : 8.923ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.040ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X149Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.814 17.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X149Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5]/C clock pessimism -0.514 17.472 clock uncertainty -0.071 17.402 SLICE_X149Y205 FDCE (Recov_fdce_C_CLR) -0.629 16.773 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5] ------------------------------------------------------------------- required time 16.773 arrival time -7.850 ------------------------------------------------------------------- slack 8.923 Slack (MET) : 8.942ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.329ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X52Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.526 17.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X52Y169 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8]/C clock pessimism -0.514 17.184 clock uncertainty -0.071 17.113 SLICE_X52Y169 FDCE (Recov_fdce_C_CLR) -0.543 16.570 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8] ------------------------------------------------------------------- required time 16.570 arrival time -7.628 ------------------------------------------------------------------- slack 8.942 Slack (MET) : 8.944ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.392ns (logic 0.668ns (6.428%) route 9.724ns (93.572%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.938ns = ( 18.062 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.672 7.904 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X156Y206 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.890 18.062 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X156Y206 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1/C clock pessimism -0.514 17.548 clock uncertainty -0.071 17.478 SLICE_X156Y206 FDCE (Recov_fdce_C_CLR) -0.629 16.849 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1 ------------------------------------------------------------------- required time 16.849 arrival time -7.904 ------------------------------------------------------------------- slack 8.944 Slack (MET) : 8.944ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.392ns (logic 0.668ns (6.428%) route 9.724ns (93.572%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.938ns = ( 18.062 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.672 7.904 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X156Y206 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.890 18.062 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X156Y206 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1/C clock pessimism -0.514 17.548 clock uncertainty -0.071 17.478 SLICE_X156Y206 FDCE (Recov_fdce_C_CLR) -0.629 16.849 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1 ------------------------------------------------------------------- required time 16.849 arrival time -7.904 ------------------------------------------------------------------- slack 8.944 Slack (MET) : 8.944ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.392ns (logic 0.668ns (6.428%) route 9.724ns (93.572%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.938ns = ( 18.062 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.672 7.904 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X156Y206 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.890 18.062 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X156Y206 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2/C clock pessimism -0.514 17.548 clock uncertainty -0.071 17.478 SLICE_X156Y206 FDCE (Recov_fdce_C_CLR) -0.629 16.849 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2 ------------------------------------------------------------------- required time 16.849 arrival time -7.904 ------------------------------------------------------------------- slack 8.944 Slack (MET) : 8.982ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X158Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.696 17.867 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X158Y190 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4]/C clock pessimism -0.514 17.354 clock uncertainty -0.071 17.283 SLICE_X158Y190 FDCE (Recov_fdce_C_CLR) -0.543 16.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4] ------------------------------------------------------------------- required time 16.740 arrival time -7.758 ------------------------------------------------------------------- slack 8.982 Slack (MET) : 8.982ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X158Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.696 17.867 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X158Y190 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][8]/C clock pessimism -0.514 17.354 clock uncertainty -0.071 17.283 SLICE_X158Y190 FDCE (Recov_fdce_C_CLR) -0.543 16.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][8] ------------------------------------------------------------------- required time 16.740 arrival time -7.758 ------------------------------------------------------------------- slack 8.982 Slack (MET) : 9.009ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.040ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X148Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.814 17.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X148Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][10]/C clock pessimism -0.514 17.472 clock uncertainty -0.071 17.402 SLICE_X148Y205 FDCE (Recov_fdce_C_CLR) -0.543 16.859 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][10] ------------------------------------------------------------------- required time 16.859 arrival time -7.850 ------------------------------------------------------------------- slack 9.009 Slack (MET) : 9.009ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.040ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X148Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.814 17.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X148Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][6]/C clock pessimism -0.514 17.472 clock uncertainty -0.071 17.402 SLICE_X148Y205 FDCE (Recov_fdce_C_CLR) -0.543 16.859 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][6] ------------------------------------------------------------------- required time 16.859 arrival time -7.850 ------------------------------------------------------------------- slack 9.009 Slack (MET) : 9.014ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 9.960ns (logic 0.668ns (6.706%) route 9.292ns (93.294%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.326ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.300ns = ( 17.700 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.240 7.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X53Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.529 17.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X53Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][3]/C clock pessimism -0.514 17.187 clock uncertainty -0.071 17.116 SLICE_X53Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][3] ------------------------------------------------------------------- required time 16.487 arrival time -7.473 ------------------------------------------------------------------- slack 9.014 Slack (MET) : 9.038ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][11]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.118ns (logic 0.668ns (6.602%) route 9.450ns (93.398%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 17.795 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.397 7.630 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X148Y199 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][11]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.624 17.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X148Y199 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][11]/C clock pessimism -0.514 17.282 clock uncertainty -0.071 17.211 SLICE_X148Y199 FDCE (Recov_fdce_C_CLR) -0.543 16.668 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][11] ------------------------------------------------------------------- required time 16.668 arrival time -7.630 ------------------------------------------------------------------- slack 9.038 Slack (MET) : 9.038ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.118ns (logic 0.668ns (6.602%) route 9.450ns (93.398%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 17.795 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.397 7.630 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X148Y199 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.624 17.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X148Y199 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][1]/C clock pessimism -0.514 17.282 clock uncertainty -0.071 17.211 SLICE_X148Y199 FDCE (Recov_fdce_C_CLR) -0.543 16.668 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][1] ------------------------------------------------------------------- required time 16.668 arrival time -7.630 ------------------------------------------------------------------- slack 9.038 Slack (MET) : 9.038ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.118ns (logic 0.668ns (6.602%) route 9.450ns (93.398%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.205ns = ( 17.795 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.397 7.630 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X148Y199 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.624 17.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X148Y199 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][6]/C clock pessimism -0.514 17.282 clock uncertainty -0.071 17.211 SLICE_X148Y199 FDCE (Recov_fdce_C_CLR) -0.543 16.668 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][6] ------------------------------------------------------------------- required time 16.668 arrival time -7.630 ------------------------------------------------------------------- slack 9.038 Slack (MET) : 9.061ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.083ns (logic 0.668ns (6.625%) route 9.415ns (93.375%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.157ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.131ns = ( 17.869 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.363 7.595 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X156Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.698 17.869 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X156Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][4]/C clock pessimism -0.514 17.356 clock uncertainty -0.071 17.285 SLICE_X156Y195 FDCE (Recov_fdce_C_CLR) -0.629 16.656 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][4] ------------------------------------------------------------------- required time 16.656 arrival time -7.595 ------------------------------------------------------------------- slack 9.061 Slack (MET) : 9.061ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.083ns (logic 0.668ns (6.625%) route 9.415ns (93.375%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.157ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.131ns = ( 17.869 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.363 7.595 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X156Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.698 17.869 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X156Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][7]/C clock pessimism -0.514 17.356 clock uncertainty -0.071 17.285 SLICE_X156Y195 FDCE (Recov_fdce_C_CLR) -0.629 16.656 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][7] ------------------------------------------------------------------- required time 16.656 arrival time -7.595 ------------------------------------------------------------------- slack 9.061 Slack (MET) : 9.065ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.079ns (logic 0.668ns (6.628%) route 9.411ns (93.372%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.157ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.131ns = ( 17.869 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.358 7.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X157Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.698 17.869 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X157Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][3]/C clock pessimism -0.514 17.356 clock uncertainty -0.071 17.285 SLICE_X157Y195 FDCE (Recov_fdce_C_CLR) -0.629 16.656 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][3] ------------------------------------------------------------------- required time 16.656 arrival time -7.591 ------------------------------------------------------------------- slack 9.065 Slack (MET) : 9.065ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.079ns (logic 0.668ns (6.628%) route 9.411ns (93.372%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.157ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.131ns = ( 17.869 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.358 7.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X157Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.698 17.869 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X157Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][8]/C clock pessimism -0.514 17.356 clock uncertainty -0.071 17.285 SLICE_X157Y195 FDCE (Recov_fdce_C_CLR) -0.629 16.656 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][8] ------------------------------------------------------------------- required time 16.656 arrival time -7.591 ------------------------------------------------------------------- slack 9.065 Slack (MET) : 9.094ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.243ns (logic 0.668ns (6.521%) route 9.575ns (93.479%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.937ns = ( 18.063 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.523 7.756 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X156Y202 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.891 18.063 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X156Y202 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][6]/C clock pessimism -0.514 17.549 clock uncertainty -0.071 17.479 SLICE_X156Y202 FDCE (Recov_fdce_C_CLR) -0.629 16.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][6] ------------------------------------------------------------------- required time 16.850 arrival time -7.756 ------------------------------------------------------------------- slack 9.094 Slack (MET) : 9.094ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.243ns (logic 0.668ns (6.521%) route 9.575ns (93.479%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.937ns = ( 18.063 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.523 7.756 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X156Y202 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.891 18.063 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X156Y202 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][7]/C clock pessimism -0.514 17.549 clock uncertainty -0.071 17.479 SLICE_X156Y202 FDCE (Recov_fdce_C_CLR) -0.629 16.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][7] ------------------------------------------------------------------- required time 16.850 arrival time -7.756 ------------------------------------------------------------------- slack 9.094 Slack (MET) : 9.095ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[87][10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 9.886ns (logic 0.668ns (6.757%) route 9.218ns (93.243%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.320ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.166 7.398 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X50Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[87][10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.535 17.706 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X50Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[87][10]/C clock pessimism -0.514 17.193 clock uncertainty -0.071 17.122 SLICE_X50Y160 FDCE (Recov_fdce_C_CLR) -0.629 16.493 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[87][10] ------------------------------------------------------------------- required time 16.493 arrival time -7.398 ------------------------------------------------------------------- slack 9.095 Slack (MET) : 9.099ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[83][10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 9.882ns (logic 0.668ns (6.760%) route 9.214ns (93.240%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.320ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.161 7.394 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X51Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[83][10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.535 17.706 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X51Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[83][10]/C clock pessimism -0.514 17.193 clock uncertainty -0.071 17.122 SLICE_X51Y160 FDCE (Recov_fdce_C_CLR) -0.629 16.493 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[83][10] ------------------------------------------------------------------- required time 16.493 arrival time -7.394 ------------------------------------------------------------------- slack 9.099 Slack (MET) : 9.100ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 9.960ns (logic 0.668ns (6.706%) route 9.292ns (93.294%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.326ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.300ns = ( 17.700 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.240 7.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X52Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.529 17.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X52Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][3]/C clock pessimism -0.514 17.187 clock uncertainty -0.071 17.116 SLICE_X52Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][3] ------------------------------------------------------------------- required time 16.573 arrival time -7.473 ------------------------------------------------------------------- slack 9.100 Slack (MET) : 9.100ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 9.960ns (logic 0.668ns (6.706%) route 9.292ns (93.294%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.326ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.300ns = ( 17.700 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.240 7.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X52Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.529 17.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X52Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][6]/C clock pessimism -0.514 17.187 clock uncertainty -0.071 17.116 SLICE_X52Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][6] ------------------------------------------------------------------- required time 16.573 arrival time -7.473 ------------------------------------------------------------------- slack 9.100 Slack (MET) : 9.100ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 9.960ns (logic 0.668ns (6.706%) route 9.292ns (93.294%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.326ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.300ns = ( 17.700 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.240 7.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X52Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.529 17.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X52Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][7]/C clock pessimism -0.514 17.187 clock uncertainty -0.071 17.116 SLICE_X52Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][7] ------------------------------------------------------------------- required time 16.573 arrival time -7.473 ------------------------------------------------------------------- slack 9.100 Slack (MET) : 9.100ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 9.960ns (logic 0.668ns (6.706%) route 9.292ns (93.294%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.326ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.300ns = ( 17.700 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.240 7.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] SLICE_X52Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.529 17.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk SLICE_X52Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][8]/C clock pessimism -0.514 17.187 clock uncertainty -0.071 17.116 SLICE_X52Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][8] ------------------------------------------------------------------- required time 16.573 arrival time -7.473 ------------------------------------------------------------------- slack 9.100 Slack (MET) : 9.104ns (required time - arrival time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[254][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) Data Path Delay: 10.157ns (logic 0.668ns (6.576%) route 9.489ns (93.424%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.039ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.013ns = ( 17.987 - 20.000 ) Source Clock Delay (SCD): -2.488ns Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O net (fo=24670, routed) 8.437 7.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] SLICE_X155Y204 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[254][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.815 17.987 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk SLICE_X155Y204 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[254][4]/C clock pessimism -0.514 17.473 clock uncertainty -0.071 17.403 SLICE_X155Y204 FDCE (Recov_fdce_C_CLR) -0.629 16.774 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[254][4] ------------------------------------------------------------------- required time 16.774 arrival time -7.670 ------------------------------------------------------------------- slack 9.104 -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: cpu_clk Max Delay 59 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 12.140ns (logic 0.580ns (4.778%) route 11.560ns (95.222%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.662ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.834ns Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.726 -1.314 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.124 -1.190 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 10.834 9.644 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 SLICE_X11Y38 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.995 -1.834 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 12.140ns (logic 0.580ns (4.778%) route 11.560ns (95.222%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.662ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.834ns Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.726 -1.314 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.124 -1.190 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 10.834 9.644 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 SLICE_X11Y38 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.995 -1.834 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_cpu/delay_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 12.115ns (logic 0.580ns (4.787%) route 11.535ns (95.213%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.743ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.753ns Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.726 -1.314 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.124 -1.190 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 10.809 9.620 pll_clk.u_rst_cpu/p_0_in_0 SLICE_X5Y45 FDCE f pll_clk.u_rst_cpu/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.076 -1.753 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[0]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_cpu/delay_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 12.115ns (logic 0.580ns (4.787%) route 11.535ns (95.213%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.743ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.753ns Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=125, routed) 0.726 -1.314 pll_clk.u_rst_sys/Q[0] SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.124 -1.190 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O net (fo=5108, routed) 10.809 9.620 pll_clk.u_rst_cpu/p_0_in_0 SLICE_X5Y45 FDCE f pll_clk.u_rst_cpu/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.076 -1.753 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C Slack: inf Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.883ns (logic 0.175ns (9.295%) route 1.708ns (90.705%)) Logic Levels: 0 Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.608ns Source Clock Delay (SCD): -0.383ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk SLICE_X113Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y69 FDCE (Prop_fdce_C_Q) 0.175 -0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q net (fo=2, routed) 1.708 1.500 u_cpu/u_csr/interrupt[3] SLICE_X47Y54 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.654 -0.608 u_cpu/u_csr/cpu_clk SLICE_X47Y54 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 3.767ns (logic 1.314ns (34.882%) route 2.453ns (65.118%)) Logic Levels: 0 Clock Path Skew: 0.559ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.844ns Source Clock Delay (SCD): -2.403ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.939 -2.403 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) 1.314 -1.089 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 2.453 1.364 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.985 -1.844 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 3.751ns (logic 1.317ns (35.109%) route 2.434ns (64.891%)) Logic Levels: 0 Clock Path Skew: 0.556ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.847ns Source Clock Delay (SCD): -2.403ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.939 -2.403 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) 1.317 -1.086 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 2.434 1.349 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] SLICE_X17Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.982 -1.847 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.655ns (logic 0.612ns (36.985%) route 1.043ns (63.015%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.505ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.966 -0.342 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.270 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 1.043 1.313 u_Axi_CDC/rFifo/_zz_ram_port10__2[18] SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.619ns (logic 0.595ns (36.745%) route 1.024ns (63.255%)) Logic Levels: 0 Clock Path Skew: -0.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.510ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.252 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 1.024 1.276 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.753 -0.510 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.592ns (logic 0.491ns (30.847%) route 1.101ns (69.153%)) Logic Levels: 0 Clock Path Skew: -0.166ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.510ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.147 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 1.101 1.248 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] SLICE_X17Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.753 -0.510 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.553ns (logic 0.595ns (38.309%) route 0.958ns (61.691%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.505ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.966 -0.342 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.253 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.958 1.211 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.548ns (logic 0.612ns (39.544%) route 0.936ns (60.456%)) Logic Levels: 0 Clock Path Skew: -0.166ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.509ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.269 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.936 1.204 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.754 -0.509 u_Axi_CDC/rFifo/cpu_clk SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.546ns (logic 0.612ns (39.595%) route 0.934ns (60.405%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.506ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.269 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.934 1.202 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.529ns (logic 0.612ns (40.036%) route 0.917ns (59.964%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.268 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.917 1.184 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.523ns (logic 0.482ns (31.652%) route 1.041ns (68.348%)) Logic Levels: 0 Clock Path Skew: -0.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.510ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.139 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 1.041 1.180 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.753 -0.510 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.464ns (logic 0.485ns (33.126%) route 0.979ns (66.874%)) Logic Levels: 0 Clock Path Skew: -0.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.510ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.142 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 0.979 1.121 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.753 -0.510 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.438ns (logic 0.595ns (41.382%) route 0.843ns (58.618%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.251 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.843 1.094 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.405ns (logic 0.482ns (34.311%) route 0.923ns (65.689%)) Logic Levels: 0 Clock Path Skew: -0.166ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.508ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.966 -0.342 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.140 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 0.923 1.063 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] SLICE_X14Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.755 -0.508 u_Axi_CDC/rFifo/cpu_clk SLICE_X14Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.378ns (logic 0.482ns (34.967%) route 0.896ns (65.033%)) Logic Levels: 0 Clock Path Skew: -0.165ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.508ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.139 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 0.896 1.035 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] SLICE_X15Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.755 -0.508 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.378ns (logic 0.491ns (35.636%) route 0.887ns (64.364%)) Logic Levels: 0 Clock Path Skew: -0.165ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.509ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.147 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.887 1.034 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.754 -0.509 u_Axi_CDC/rFifo/cpu_clk SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.375ns (logic 0.480ns (34.917%) route 0.895ns (65.083%)) Logic Levels: 0 Clock Path Skew: -0.164ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.137 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 0.895 1.031 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.373ns (logic 0.595ns (43.346%) route 0.778ns (56.654%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.506ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.252 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.778 1.029 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.372ns (logic 0.485ns (35.358%) route 0.887ns (64.642%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.506ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.141 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.887 1.027 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.370ns (logic 0.595ns (43.428%) route 0.775ns (56.572%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.506ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.251 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.775 1.026 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.368ns (logic 0.491ns (35.893%) route 0.877ns (64.107%)) Logic Levels: 0 Clock Path Skew: -0.164ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.148 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.877 1.025 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.362ns (logic 0.612ns (44.930%) route 0.750ns (55.070%)) Logic Levels: 0 Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.505ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.268 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.750 1.018 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] SLICE_X17Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.351ns (logic 0.480ns (35.518%) route 0.871ns (64.482%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.506ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.136 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 0.871 1.007 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.350ns (logic 0.482ns (35.709%) route 0.868ns (64.291%)) Logic Levels: 0 Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.505ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 0.868 1.006 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.336ns (logic 0.485ns (36.291%) route 0.851ns (63.709%)) Logic Levels: 0 Clock Path Skew: -0.165ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.966 -0.342 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.143 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.851 0.994 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] SLICE_X14Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X14Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.337ns (logic 0.485ns (36.281%) route 0.852ns (63.719%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.141 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 0.852 0.993 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.327ns (logic 0.595ns (44.836%) route 0.732ns (55.164%)) Logic Levels: 0 Clock Path Skew: -0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.337ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.258 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.732 0.990 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.331ns (logic 0.491ns (36.899%) route 0.840ns (63.101%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.504ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.966 -0.342 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.149 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.840 0.988 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.759 -0.504 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.325ns (logic 0.485ns (36.591%) route 0.840ns (63.409%)) Logic Levels: 0 Clock Path Skew: -0.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.510ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.142 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.840 0.982 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.753 -0.510 u_Axi_CDC/rFifo/cpu_clk SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.310ns (logic 0.612ns (46.719%) route 0.698ns (53.281%)) Logic Levels: 0 Clock Path Skew: -0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.337ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.275 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 0.698 0.973 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.311ns (logic 0.491ns (37.451%) route 0.820ns (62.549%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.505ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.148 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 0.820 0.968 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.310ns (logic 0.480ns (36.641%) route 0.830ns (63.358%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.504ns Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.966 -0.342 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 0.830 0.968 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.759 -0.504 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.290ns (logic 0.480ns (37.196%) route 0.810ns (62.804%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.506ns Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.137 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 0.810 0.947 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_matmul_axi_slave/done_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.261ns (logic 0.175ns (13.873%) route 1.086ns (86.127%)) Logic Levels: 0 Clock Path Skew: -0.247ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.607ns Source Clock Delay (SCD): -0.360ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.948 -0.360 u_matmul_axi_slave/sys_clk SLICE_X41Y78 FDRE r u_matmul_axi_slave/done_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y78 FDRE (Prop_fdre_C_Q) 0.175 -0.185 r u_matmul_axi_slave/done_reg/Q net (fo=11, routed) 1.086 0.901 u_cpu/u_csr/interrupt[2] SLICE_X47Y52 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.655 -0.607 u_cpu/u_csr/cpu_clk SLICE_X47Y52 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.123ns (logic 0.491ns (43.737%) route 0.632ns (56.263%)) Logic Levels: 0 Clock Path Skew: -0.169ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.506ns Source Clock Delay (SCD): -0.337ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.154 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 0.632 0.785 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.100ns (logic 0.482ns (43.813%) route 0.618ns (56.187%)) Logic Levels: 0 Clock Path Skew: -0.164ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.501ns Source Clock Delay (SCD): -0.337ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y54 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.145 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 0.618 0.763 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] SLICE_X16Y34 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_Axi_CDC/rFifo/cpu_clk SLICE_X16Y34 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_confreg/int_out_or_q2_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.608ns (logic 0.160ns (26.335%) route 0.448ns (73.665%)) Logic Levels: 0 Clock Path Skew: -0.240ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.500ns Source Clock Delay (SCD): -0.260ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.048 -0.260 u_confreg/sys_clk SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y47 FDRE (Prop_fdre_C_Q) 0.160 -0.100 r u_confreg/int_out_or_q2_reg/Q net (fo=1, routed) 0.448 0.347 u_cpu/u_csr/interrupt[0] SLICE_X9Y33 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.763 -0.500 u_cpu/u_csr/cpu_clk SLICE_X9Y33 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C Slack: inf Source: u_snix_axil_cdma_mux_8ch/ch_done_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.663ns (logic 0.231ns (34.839%) route 0.432ns (65.161%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.608ns Source Clock Delay (SCD): -0.381ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.927 -0.381 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X49Y58 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y58 FDRE (Prop_fdre_C_Q) 0.175 -0.206 r u_snix_axil_cdma_mux_8ch/ch_done_reg[3]/Q net (fo=3, routed) 0.432 0.226 u_snix_axil_cdma_mux_8ch/ch_done_reg[3]_1 SLICE_X49Y56 LUT5 (Prop_lut5_I1_O) 0.056 0.282 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O net (fo=1, routed) 0.000 0.282 u_cpu/u_csr/interrupt[1] SLICE_X49Y56 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.654 -0.608 u_cpu/u_csr/cpu_clk SLICE_X49Y56 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.500ns (logic 0.204ns (40.806%) route 0.296ns (59.194%)) Logic Levels: 0 Clock Path Skew: -0.235ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.497ns Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/arFifo/sys_clk SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.204 -0.058 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.296 0.238 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.491ns (logic 0.204ns (41.563%) route 0.287ns (58.437%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.204 -0.058 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.287 0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.453ns (logic 0.175ns (38.668%) route 0.278ns (61.332%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.495ns Source Clock Delay (SCD): -0.261ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.175 -0.086 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.278 0.191 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.768 -0.495 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.408ns (logic 0.204ns (50.037%) route 0.204ns (49.963%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/bFifo/sys_clk SLICE_X8Y40 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y40 FDCE (Prop_fdce_C_Q) 0.204 -0.058 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.204 0.146 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.406ns (logic 0.204ns (50.186%) route 0.202ns (49.814%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.204 -0.058 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.202 0.144 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.401ns (logic 0.184ns (45.856%) route 0.217ns (54.144%)) Logic Levels: 0 Clock Path Skew: -0.235ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.497ns Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/arFifo/sys_clk SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.184 -0.078 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.217 0.139 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.386ns (logic 0.175ns (45.391%) route 0.211ns (54.609%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.495ns Source Clock Delay (SCD): -0.261ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.175 -0.086 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.211 0.124 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.768 -0.495 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.356ns (logic 0.184ns (51.719%) route 0.172ns (48.281%)) Logic Levels: 0 Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.184 -0.078 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.172 0.094 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: cpu_clk To Clock: sys_clk Max Delay 154 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.604ns (logic 0.612ns (38.148%) route 0.992ns (61.852%)) Logic Levels: 0 Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.379ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X42Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X42Y53 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.233 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/O net (fo=1, routed) 0.992 1.225 u_Axi_CDC/arFifo/_zz_ram_port10__1[18] SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/arFifo/sys_clk SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.436ns (logic 0.612ns (42.623%) route 0.824ns (57.377%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X36Y53 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y53 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.265 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/O net (fo=1, routed) 0.824 1.089 u_Axi_CDC/awFifo/_zz_ram_port10[18] SLICE_X13Y51 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/awFifo/sys_clk SLICE_X13Y51 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.360ns (logic 0.595ns (43.759%) route 0.765ns (56.241%)) Logic Levels: 0 Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.379ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X42Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X42Y53 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.216 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/O net (fo=1, routed) 0.765 0.981 u_Axi_CDC/arFifo/_zz_ram_port10__1[19] SLICE_X15Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/arFifo/sys_clk SLICE_X15Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.179ns (logic 0.595ns (50.464%) route 0.584ns (49.536%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.266ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.042 -0.266 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X14Y36 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y36 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.329 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.584 0.913 u_Axi_CDC/wFifo/_zz_ram_port10__0[7] SLICE_X13Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk SLICE_X13Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Fast Process Corner) Data Path Delay: 1.135ns (logic 0.231ns (20.356%) route 0.904ns (79.644%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.495ns Source Clock Delay (SCD): -0.232ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.076 -0.232 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.175 -0.057 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.406 0.349 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.056 0.405 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.497 0.903 u_Axi_CDC/awFifo/bufferCC_12/p_0_in SLICE_X8Y43 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Fast Process Corner) Data Path Delay: 1.135ns (logic 0.231ns (20.356%) route 0.904ns (79.644%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.263ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.495ns Source Clock Delay (SCD): -0.232ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.076 -0.232 pll_clk.u_rst_cpu/cpu_clk SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.175 -0.057 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.406 0.349 pll_clk.u_rst_cpu/cpu_resetn SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.056 0.405 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.497 0.903 u_Axi_CDC/awFifo/bufferCC_12/p_0_in SLICE_X8Y43 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.243ns (logic 0.612ns (49.219%) route 0.631ns (50.781%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X36Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y51 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.266 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/O net (fo=1, routed) 0.631 0.897 u_Axi_CDC/arFifo/_zz_ram_port10__1[24] SLICE_X16Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/arFifo/sys_clk SLICE_X16Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.245ns (logic 0.485ns (38.963%) route 0.760ns (61.037%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.568ns Source Clock Delay (SCD): -0.349ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.959 -0.349 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X40Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y57 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.136 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/O net (fo=1, routed) 0.760 0.896 u_Axi_CDC/awFifo/_zz_ram_port10[16] SLICE_X10Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.694 -0.568 u_Axi_CDC/awFifo/sys_clk SLICE_X10Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.236ns (logic 0.595ns (48.144%) route 0.641ns (51.856%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X36Y53 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y53 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.248 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/O net (fo=1, routed) 0.641 0.889 u_Axi_CDC/awFifo/_zz_ram_port10[19] SLICE_X15Y53 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/awFifo/sys_clk SLICE_X15Y53 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.218ns (logic 0.482ns (39.571%) route 0.736ns (60.429%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X36Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y51 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.136 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/O net (fo=1, routed) 0.736 0.872 u_Axi_CDC/arFifo/_zz_ram_port10__1[27] SLICE_X14Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/arFifo/sys_clk SLICE_X14Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.248ns (logic 0.485ns (38.854%) route 0.763ns (61.146%)) Logic Levels: 0 Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.379ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X44Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y54 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.106 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/O net (fo=1, routed) 0.763 0.869 u_Axi_CDC/arFifo/_zz_ram_port10__1[16] SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/arFifo/sys_clk SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.248ns (logic 0.480ns (38.477%) route 0.768ns (61.523%)) Logic Levels: 0 Clock Path Skew: -0.193ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.572ns Source Clock Delay (SCD): -0.379ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X42Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X42Y53 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.101 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/O net (fo=1, routed) 0.768 0.868 u_Axi_CDC/arFifo/_zz_ram_port10__1[23] SLICE_X27Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/arFifo/sys_clk SLICE_X27Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.122ns (logic 0.612ns (54.563%) route 0.510ns (45.437%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.263ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y39 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y39 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.349 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.510 0.858 u_Axi_CDC/wFifo/_zz_ram_port10__0[12] SLICE_X15Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk SLICE_X15Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.112ns (logic 0.595ns (53.517%) route 0.517ns (46.483%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.263ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y39 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y39 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.332 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.517 0.849 u_Axi_CDC/wFifo/_zz_ram_port10__0[13] SLICE_X13Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk SLICE_X13Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.194ns (logic 0.595ns (49.818%) route 0.599ns (50.182%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X36Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y51 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.249 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/O net (fo=1, routed) 0.599 0.848 u_Axi_CDC/arFifo/_zz_ram_port10__1[25] SLICE_X15Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/arFifo/sys_clk SLICE_X15Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.215ns (logic 0.485ns (39.902%) route 0.730ns (60.098%)) Logic Levels: 0 Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.379ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X42Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X42Y53 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.106 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/O net (fo=1, routed) 0.730 0.836 u_Axi_CDC/arFifo/_zz_ram_port10__1[22] SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/arFifo/sys_clk SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.206ns (logic 0.482ns (39.963%) route 0.724ns (60.037%)) Logic Levels: 0 Clock Path Skew: -0.190ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.569ns Source Clock Delay (SCD): -0.379ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X42Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X42Y53 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.103 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/O net (fo=1, routed) 0.724 0.827 u_Axi_CDC/arFifo/_zz_ram_port10__1[21] SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.693 -0.569 u_Axi_CDC/arFifo/sys_clk SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.174ns (logic 0.612ns (52.147%) route 0.562ns (47.853%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.573ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X36Y54 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y54 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.265 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/O net (fo=1, routed) 0.562 0.826 u_Axi_CDC/awFifo/_zz_ram_port10[24] SLICE_X27Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.689 -0.573 u_Axi_CDC/awFifo/sys_clk SLICE_X27Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.175ns (logic 0.480ns (40.841%) route 0.695ns (59.159%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.568ns Source Clock Delay (SCD): -0.349ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.959 -0.349 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X40Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X40Y57 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.131 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/O net (fo=1, routed) 0.695 0.826 u_Axi_CDC/awFifo/_zz_ram_port10[17] SLICE_X10Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.694 -0.568 u_Axi_CDC/awFifo/sys_clk SLICE_X10Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.200ns (logic 0.491ns (40.927%) route 0.709ns (59.073%)) Logic Levels: 0 Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.379ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK SLICE_X42Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X42Y53 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.112 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/O net (fo=1, routed) 0.709 0.821 u_Axi_CDC/arFifo/_zz_ram_port10__1[20] SLICE_X16Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/arFifo/sys_clk SLICE_X16Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.158ns (logic 0.480ns (41.467%) route 0.678ns (58.533%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X36Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y51 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.134 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/O net (fo=1, routed) 0.678 0.811 u_Axi_CDC/arFifo/_zz_ram_port10__1[29] SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/arFifo/sys_clk SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.158ns (logic 0.595ns (51.367%) route 0.563ns (48.633%)) Logic Levels: 0 Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.573ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X36Y54 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y54 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.248 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/O net (fo=1, routed) 0.563 0.811 u_Axi_CDC/awFifo/_zz_ram_port10[25] SLICE_X27Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.689 -0.573 u_Axi_CDC/awFifo/sys_clk SLICE_X27Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.150ns (logic 0.491ns (42.682%) route 0.659ns (57.318%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X36Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y51 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.145 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/O net (fo=1, routed) 0.659 0.804 u_Axi_CDC/arFifo/_zz_ram_port10__1[26] SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/arFifo/sys_clk SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.139ns (logic 0.485ns (42.577%) route 0.654ns (57.423%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X36Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y51 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.139 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/O net (fo=1, routed) 0.654 0.793 u_Axi_CDC/arFifo/_zz_ram_port10__1[28] SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/arFifo/sys_clk SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.033ns (logic 0.595ns (57.586%) route 0.438ns (42.414%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y41 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.333 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.438 0.771 u_Axi_CDC/wFifo/_zz_ram_port10__0[31] SLICE_X14Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk SLICE_X14Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.102ns (logic 0.485ns (44.015%) route 0.617ns (55.985%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X36Y53 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y53 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.138 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/O net (fo=1, routed) 0.617 0.755 u_Axi_CDC/awFifo/_zz_ram_port10[22] SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/awFifo/sys_clk SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.017ns (logic 0.485ns (47.694%) route 0.532ns (52.306%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.264ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.044 -0.264 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X16Y39 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y39 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.221 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.532 0.753 u_Axi_CDC/wFifo/_zz_ram_port10__0[22] SLICE_X12Y48 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk SLICE_X12Y48 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.998ns (logic 0.612ns (61.341%) route 0.386ns (38.659%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y41 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.350 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 0.386 0.736 u_Axi_CDC/wFifo/_zz_ram_port10__0[30] SLICE_X14Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk SLICE_X14Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.976ns (logic 0.491ns (50.313%) route 0.485ns (49.687%)) Logic Levels: 0 Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.263ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y39 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y39 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.228 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.485 0.713 u_Axi_CDC/wFifo/_zz_ram_port10__0[14] SLICE_X14Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk SLICE_X14Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.966ns (logic 0.612ns (63.335%) route 0.354ns (36.665%)) Logic Levels: 0 Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.495ns Source Clock Delay (SCD): -0.267ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.041 -0.267 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X16Y36 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y36 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.345 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.354 0.699 u_Axi_CDC/wFifo/_zz_ram_port10__0[24] SLICE_X12Y45 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/wFifo/sys_clk SLICE_X12Y45 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.045ns (logic 0.485ns (46.426%) route 0.560ns (53.574%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X36Y54 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y54 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.138 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/O net (fo=1, routed) 0.560 0.697 u_Axi_CDC/awFifo/_zz_ram_port10[28] SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/awFifo/sys_clk SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.073ns (logic 0.480ns (44.722%) route 0.593ns (55.278%)) Logic Levels: 0 Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.379ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X44Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X44Y54 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.101 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/O net (fo=1, routed) 0.593 0.694 u_Axi_CDC/arFifo/_zz_ram_port10__1[17] SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/arFifo/sys_clk SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.025ns (logic 0.482ns (47.041%) route 0.543ns (52.959%)) Logic Levels: 0 Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X36Y53 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y53 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.135 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/O net (fo=1, routed) 0.543 0.677 u_Axi_CDC/awFifo/_zz_ram_port10[21] SLICE_X17Y50 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/awFifo/sys_clk SLICE_X17Y50 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 1.018ns (logic 0.491ns (48.227%) route 0.527ns (51.773%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X36Y53 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y53 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.144 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/O net (fo=1, routed) 0.527 0.671 u_Axi_CDC/awFifo/_zz_ram_port10[20] SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/awFifo/sys_clk SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.923ns (logic 0.612ns (66.307%) route 0.311ns (33.693%)) Logic Levels: 0 Clock Path Skew: -0.305ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.261ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y49 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.351 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/O net (fo=1, routed) 0.311 0.662 u_Axi_CDC/awFifo/_zz_ram_port10[6] SLICE_X17Y50 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/awFifo/sys_clk SLICE_X17Y50 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.920ns (logic 0.612ns (66.542%) route 0.308ns (33.458%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.261ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X14Y45 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y45 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.351 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/O net (fo=1, routed) 0.308 0.659 u_Axi_CDC/awFifo/_zz_ram_port10[0] SLICE_X14Y48 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/awFifo/sys_clk SLICE_X14Y48 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.907ns (logic 0.595ns (65.606%) route 0.312ns (34.394%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X14Y40 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y40 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.333 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.312 0.645 u_Axi_CDC/wFifo/_zz_ram_port10__0[1] SLICE_X13Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk SLICE_X13Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[38]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.978ns (logic 0.491ns (50.222%) route 0.487ns (49.778%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.574ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK SLICE_X36Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y56 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.144 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/O net (fo=1, routed) 0.487 0.630 u_Axi_CDC/awFifo/_zz_ram_port10[38] SLICE_X28Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[38]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk SLICE_X28Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[38]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.890ns (logic 0.482ns (54.149%) route 0.408ns (45.851%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.261ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X14Y45 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y45 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.221 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/O net (fo=1, routed) 0.408 0.629 u_Axi_CDC/awFifo/_zz_ram_port10[3] SLICE_X14Y48 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/awFifo/sys_clk SLICE_X14Y48 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.887ns (logic 0.595ns (67.046%) route 0.292ns (32.954%)) Logic Levels: 0 Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.496ns Source Clock Delay (SCD): -0.267ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.041 -0.267 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X16Y36 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y36 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.328 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.292 0.620 u_Axi_CDC/wFifo/_zz_ram_port10__0[25] SLICE_X15Y40 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.767 -0.496 u_Axi_CDC/wFifo/sys_clk SLICE_X15Y40 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.880ns (logic 0.612ns (69.512%) route 0.268ns (30.488%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.495ns Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X14Y40 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y40 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.350 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.268 0.618 u_Axi_CDC/wFifo/_zz_ram_port10__0[0] SLICE_X14Y44 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/wFifo/sys_clk SLICE_X14Y44 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.965ns (logic 0.482ns (49.970%) route 0.483ns (50.030%)) Logic Levels: 0 Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X36Y54 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y54 RAMD32 (Prop_ramd32_CLK_O) 0.482 0.135 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/O net (fo=1, routed) 0.483 0.617 u_Axi_CDC/awFifo/_zz_ram_port10[27] SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/awFifo/sys_clk SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.881ns (logic 0.485ns (55.040%) route 0.396ns (44.960%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.497ns Source Clock Delay (SCD): -0.267ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.041 -0.267 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X16Y36 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y36 RAMD32 (Prop_ramd32_CLK_O) 0.485 0.218 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 0.396 0.614 u_Axi_CDC/wFifo/_zz_ram_port10__0[28] SLICE_X15Y39 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.766 -0.497 u_Axi_CDC/wFifo/sys_clk SLICE_X15Y39 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.860ns (logic 0.595ns (69.192%) route 0.265ns (30.808%)) Logic Levels: 0 Clock Path Skew: -0.305ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.566ns Source Clock Delay (SCD): -0.261ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y49 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.334 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/O net (fo=1, routed) 0.265 0.599 u_Axi_CDC/awFifo/_zz_ram_port10[7] SLICE_X17Y50 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/awFifo/sys_clk SLICE_X17Y50 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.932ns (logic 0.612ns (65.656%) route 0.320ns (34.344%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.567ns Source Clock Delay (SCD): -0.337ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X18Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X18Y56 RAMD32 (Prop_ramd32_CLK_O) 0.612 0.275 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/O net (fo=1, routed) 0.320 0.595 u_Axi_CDC/awFifo/_zz_ram_port10[30] SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/awFifo/sys_clk SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.942ns (logic 0.480ns (50.982%) route 0.462ns (49.018%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.571ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X36Y53 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y53 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.133 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/O net (fo=1, routed) 0.462 0.594 u_Axi_CDC/awFifo/_zz_ram_port10[23] SLICE_X22Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/awFifo/sys_clk SLICE_X22Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.941ns (logic 0.480ns (51.024%) route 0.461ns (48.976%)) Logic Levels: 0 Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.571ns Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK SLICE_X36Y54 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y54 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.133 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/O net (fo=1, routed) 0.461 0.594 u_Axi_CDC/awFifo/_zz_ram_port10[29] SLICE_X22Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/awFifo/sys_clk SLICE_X22Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.854ns (logic 0.480ns (56.183%) route 0.374ns (43.817%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.264ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.044 -0.264 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X16Y39 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y39 RAMD32 (Prop_ramd32_CLK_O) 0.480 0.216 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 0.374 0.590 u_Axi_CDC/wFifo/_zz_ram_port10__0[23] SLICE_X15Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk SLICE_X15Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.848ns (logic 0.491ns (57.928%) route 0.357ns (42.072%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.494ns Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X14Y40 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y40 RAMD32 (Prop_ramd32_CLK_O) 0.491 0.229 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.357 0.585 u_Axi_CDC/wFifo/_zz_ram_port10__0[2] SLICE_X12Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk SLICE_X12Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) Data Path Delay: 0.930ns (logic 0.595ns (63.955%) route 0.335ns (36.045%)) Logic Levels: 0 Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.578ns Source Clock Delay (SCD): -0.346ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X36Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y52 RAMD32 (Prop_ramd32_CLK_O) 0.595 0.249 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/O net (fo=1, routed) 0.335 0.584 u_Axi_CDC/arFifo/_zz_ram_port10__1[49] SLICE_X39Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 0.684 -0.578 u_Axi_CDC/arFifo/sys_clk SLICE_X39Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: clkfbout_clk_pll To Clock: Max Delay 1 Endpoint Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT (clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Path Group: (none) Path Type: Max at Fast Process Corner Data Path Delay: 1.519ns (logic 0.029ns (1.909%) route 1.490ns (98.091%)) Logic Levels: 1 (BUFG=1) Clock Uncertainty: 0.169ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.075ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clkfbout_clk_pll fall edge) 10.000 10.000 f K21 0.000 10.000 f clk (IN) net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 10.419 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 10.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.847 8.053 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT net (fo=1, routed) 0.611 8.663 pll_clk.u_clk_pll/inst/clkfbout_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 8.692 f pll_clk.u_clk_pll/inst/clkf_buf/O net (fo=1, routed) 0.880 9.572 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: Max Delay 41 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_axi_dvi/DVI_RECT_DIR_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 15.253ns (logic 6.148ns (40.303%) route 9.106ns (59.697%)) Logic Levels: 10 (CARRY4=5 LUT2=2 LUT4=1 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.007 -2.335 u_axi_dvi/sys_clk SLICE_X3Y75 FDRE r u_axi_dvi/DVI_RECT_DIR_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y75 FDRE (Prop_fdre_C_Q) 0.456 -1.879 r u_axi_dvi/DVI_RECT_DIR_reg[1]/Q net (fo=5, routed) 1.288 -0.591 u_axi_dvi/DVI_RECT_DIR_reg_n_0_[1] SLICE_X2Y75 LUT2 (Prop_lut2_I0_O) 0.124 -0.467 r u_axi_dvi/video_red_OBUF[2]_inst_i_285/O net (fo=1, routed) 0.000 -0.467 u_axi_dvi/video_red_OBUF[2]_inst_i_285_n_0 SLICE_X2Y75 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 0.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_274/CO[3] net (fo=1, routed) 0.000 0.066 u_axi_dvi/video_red_OBUF[2]_inst_i_274_n_0 SLICE_X2Y76 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 0.183 r u_axi_dvi/video_red_OBUF[2]_inst_i_256/CO[3] net (fo=1, routed) 0.000 0.183 u_axi_dvi/video_red_OBUF[2]_inst_i_256_n_0 SLICE_X2Y77 CARRY4 (Prop_carry4_CI_O[3]) 0.315 0.498 r u_axi_dvi/video_red_OBUF[2]_inst_i_220/O[3] net (fo=1, routed) 0.957 1.455 u_axi_dvi/video_red_OBUF[2]_inst_i_220_n_4 SLICE_X1Y77 LUT2 (Prop_lut2_I1_O) 0.307 1.762 r u_axi_dvi/video_red_OBUF[2]_inst_i_156/O net (fo=1, routed) 0.000 1.762 u_axi_dvi/video_red_OBUF[2]_inst_i_156_n_0 SLICE_X1Y77 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 2.163 r u_axi_dvi/video_red_OBUF[2]_inst_i_86/CO[3] net (fo=1, routed) 0.000 2.163 u_axi_dvi/video_red_OBUF[2]_inst_i_86_n_0 SLICE_X1Y78 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 2.277 f u_axi_dvi/video_red_OBUF[2]_inst_i_34/CO[3] net (fo=1, routed) 1.331 3.608 u_axi_dvi/video_red_OBUF[2]_inst_i_34_n_0 SLICE_X6Y74 LUT4 (Prop_lut4_I3_O) 0.124 3.732 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O net (fo=1, routed) 0.282 4.014 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 SLICE_X6Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.138 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 5.248 9.386 video_red_OBUF[0] K23 OBUF (Prop_obuf_I_O) 3.533 12.919 r video_red_OBUF[0]_inst/O net (fo=0) 0.000 12.919 video_red[0] K23 r video_red[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_RECT_DIR_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 15.140ns (logic 6.175ns (40.788%) route 8.964ns (59.212%)) Logic Levels: 10 (CARRY4=5 LUT2=2 LUT4=1 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.007 -2.335 u_axi_dvi/sys_clk SLICE_X3Y75 FDRE r u_axi_dvi/DVI_RECT_DIR_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y75 FDRE (Prop_fdre_C_Q) 0.456 -1.879 r u_axi_dvi/DVI_RECT_DIR_reg[1]/Q net (fo=5, routed) 1.288 -0.591 u_axi_dvi/DVI_RECT_DIR_reg_n_0_[1] SLICE_X2Y75 LUT2 (Prop_lut2_I0_O) 0.124 -0.467 r u_axi_dvi/video_red_OBUF[2]_inst_i_285/O net (fo=1, routed) 0.000 -0.467 u_axi_dvi/video_red_OBUF[2]_inst_i_285_n_0 SLICE_X2Y75 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 0.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_274/CO[3] net (fo=1, routed) 0.000 0.066 u_axi_dvi/video_red_OBUF[2]_inst_i_274_n_0 SLICE_X2Y76 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 0.183 r u_axi_dvi/video_red_OBUF[2]_inst_i_256/CO[3] net (fo=1, routed) 0.000 0.183 u_axi_dvi/video_red_OBUF[2]_inst_i_256_n_0 SLICE_X2Y77 CARRY4 (Prop_carry4_CI_O[3]) 0.315 0.498 r u_axi_dvi/video_red_OBUF[2]_inst_i_220/O[3] net (fo=1, routed) 0.957 1.455 u_axi_dvi/video_red_OBUF[2]_inst_i_220_n_4 SLICE_X1Y77 LUT2 (Prop_lut2_I1_O) 0.307 1.762 r u_axi_dvi/video_red_OBUF[2]_inst_i_156/O net (fo=1, routed) 0.000 1.762 u_axi_dvi/video_red_OBUF[2]_inst_i_156_n_0 SLICE_X1Y77 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 2.163 r u_axi_dvi/video_red_OBUF[2]_inst_i_86/CO[3] net (fo=1, routed) 0.000 2.163 u_axi_dvi/video_red_OBUF[2]_inst_i_86_n_0 SLICE_X1Y78 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 2.277 f u_axi_dvi/video_red_OBUF[2]_inst_i_34/CO[3] net (fo=1, routed) 1.331 3.608 u_axi_dvi/video_red_OBUF[2]_inst_i_34_n_0 SLICE_X6Y74 LUT4 (Prop_lut4_I3_O) 0.124 3.732 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O net (fo=1, routed) 0.282 4.014 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 SLICE_X6Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.138 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 5.106 9.245 video_red_OBUF[0] F24 OBUF (Prop_obuf_I_O) 3.560 12.805 r video_red_OBUF[1]_inst/O net (fo=0) 0.000 12.805 video_red[1] F24 r video_red[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/DVI_RECT_DIR_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 14.873ns (logic 6.202ns (41.697%) route 8.671ns (58.303%)) Logic Levels: 10 (CARRY4=5 LUT2=2 LUT4=1 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.007 -2.335 u_axi_dvi/sys_clk SLICE_X3Y75 FDRE r u_axi_dvi/DVI_RECT_DIR_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y75 FDRE (Prop_fdre_C_Q) 0.456 -1.879 r u_axi_dvi/DVI_RECT_DIR_reg[1]/Q net (fo=5, routed) 1.288 -0.591 u_axi_dvi/DVI_RECT_DIR_reg_n_0_[1] SLICE_X2Y75 LUT2 (Prop_lut2_I0_O) 0.124 -0.467 r u_axi_dvi/video_red_OBUF[2]_inst_i_285/O net (fo=1, routed) 0.000 -0.467 u_axi_dvi/video_red_OBUF[2]_inst_i_285_n_0 SLICE_X2Y75 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 0.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_274/CO[3] net (fo=1, routed) 0.000 0.066 u_axi_dvi/video_red_OBUF[2]_inst_i_274_n_0 SLICE_X2Y76 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 0.183 r u_axi_dvi/video_red_OBUF[2]_inst_i_256/CO[3] net (fo=1, routed) 0.000 0.183 u_axi_dvi/video_red_OBUF[2]_inst_i_256_n_0 SLICE_X2Y77 CARRY4 (Prop_carry4_CI_O[3]) 0.315 0.498 r u_axi_dvi/video_red_OBUF[2]_inst_i_220/O[3] net (fo=1, routed) 0.957 1.455 u_axi_dvi/video_red_OBUF[2]_inst_i_220_n_4 SLICE_X1Y77 LUT2 (Prop_lut2_I1_O) 0.307 1.762 r u_axi_dvi/video_red_OBUF[2]_inst_i_156/O net (fo=1, routed) 0.000 1.762 u_axi_dvi/video_red_OBUF[2]_inst_i_156_n_0 SLICE_X1Y77 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 2.163 r u_axi_dvi/video_red_OBUF[2]_inst_i_86/CO[3] net (fo=1, routed) 0.000 2.163 u_axi_dvi/video_red_OBUF[2]_inst_i_86_n_0 SLICE_X1Y78 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 2.277 f u_axi_dvi/video_red_OBUF[2]_inst_i_34/CO[3] net (fo=1, routed) 1.331 3.608 u_axi_dvi/video_red_OBUF[2]_inst_i_34_n_0 SLICE_X6Y74 LUT4 (Prop_lut4_I3_O) 0.124 3.732 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O net (fo=1, routed) 0.282 4.014 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 SLICE_X6Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.138 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 4.813 8.952 video_red_OBUF[0] E26 OBUF (Prop_obuf_I_O) 3.587 12.538 r video_red_OBUF[2]_inst/O net (fo=0) 0.000 12.538 video_red[2] E26 r video_red[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_clk (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.589ns (logic 3.629ns (42.252%) route 4.960ns (57.748%)) Logic Levels: 2 (BUFG=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk fall edge) 10.000 10.000 f K21 0.000 10.000 f clk (IN) net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 11.463 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 12.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 3.725 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 5.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 5.658 f pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 3.123 8.781 video_clk_OBUF H22 OBUF (Prop_obuf_I_O) 3.533 12.314 f video_clk_OBUF_inst/O net (fo=0) 0.000 12.314 video_clk H22 f video_clk (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 14.229ns (logic 3.990ns (28.040%) route 10.239ns (71.960%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q net (fo=1, routed) 10.239 8.380 dpy1_OBUF[5] G16 OBUF (Prop_obuf_I_O) 3.534 11.914 r dpy1_OBUF[5]_inst/O net (fo=0) 0.000 11.914 dpy1[5] G16 r dpy1[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[5]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_hsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 12.666ns (logic 4.311ns (34.035%) route 8.355ns (65.965%)) Logic Levels: 3 (LUT5=2 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.011 -2.331 u_axi_dvi/sys_clk SLICE_X6Y71 FDRE r u_axi_dvi/hdata_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y71 FDRE (Prop_fdre_C_Q) 0.518 -1.813 r u_axi_dvi/hdata_reg[5]/Q net (fo=12, routed) 1.535 -0.278 u_axi_dvi/hdata_reg_n_0_[5] SLICE_X0Y70 LUT5 (Prop_lut5_I1_O) 0.124 -0.154 f u_axi_dvi/video_hsync_OBUF_inst_i_2/O net (fo=1, routed) 1.000 0.847 u_axi_dvi/video_hsync_OBUF_inst_i_2_n_0 SLICE_X0Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.971 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O net (fo=1, routed) 5.820 6.791 video_hsync_OBUF J24 OBUF (Prop_obuf_I_O) 3.545 10.336 r video_hsync_OBUF_inst/O net (fo=0) 0.000 10.336 video_hsync J24 r video_hsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[5]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_de (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 12.471ns (logic 4.553ns (36.506%) route 7.918ns (63.494%)) Logic Levels: 3 (LUT5=1 LUT6=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.011 -2.331 u_axi_dvi/sys_clk SLICE_X6Y71 FDRE r u_axi_dvi/hdata_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y71 FDRE (Prop_fdre_C_Q) 0.518 -1.813 f u_axi_dvi/hdata_reg[5]/Q net (fo=12, routed) 1.755 -0.058 u_axi_dvi/hdata_reg_n_0_[5] SLICE_X2Y72 LUT5 (Prop_lut5_I4_O) 0.146 0.088 f u_axi_dvi/video_de_OBUF_inst_i_3/O net (fo=1, routed) 0.950 1.038 u_axi_dvi/video_de_OBUF_inst_i_3_n_0 SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.328 1.366 r u_axi_dvi/video_de_OBUF_inst_i_1/O net (fo=1, routed) 5.214 6.580 video_de_OBUF G24 OBUF (Prop_obuf_I_O) 3.561 10.141 r video_de_OBUF_inst/O net (fo=0) 0.000 10.141 video_de G24 r video_de (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[1]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.831ns (logic 4.135ns (34.951%) route 7.696ns (65.049%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.419 -1.899 r u_confreg/led_data_reg[1]_lopt_replica/Q net (fo=1, routed) 7.696 5.797 lopt_7 E21 OBUF (Prop_obuf_I_O) 3.716 9.513 r leds_OBUF[1]_inst/O net (fo=0) 0.000 9.513 leds[1] E21 r leds[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[13]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[13] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.808ns (logic 4.027ns (34.101%) route 7.781ns (65.899%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.862 r u_confreg/led_data_reg[13]_lopt_replica/Q net (fo=1, routed) 7.781 5.920 lopt_4 A22 OBUF (Prop_obuf_I_O) 3.571 9.490 r leds_OBUF[13]_inst/O net (fo=0) 0.000 9.490 leds[13] A22 r leds[13] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.797ns (logic 3.976ns (33.704%) route 7.821ns (66.296%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q net (fo=1, routed) 7.821 5.961 dpy1_OBUF[7] G17 OBUF (Prop_obuf_I_O) 3.520 9.482 r dpy1_OBUF[7]_inst/O net (fo=0) 0.000 9.482 dpy1[7] G17 r dpy1[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_vsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.798ns (logic 4.379ns (37.113%) route 7.419ns (62.887%)) Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.007 -2.335 u_axi_dvi/sys_clk SLICE_X0Y74 FDRE r u_axi_dvi/vdata_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y74 FDRE (Prop_fdre_C_Q) 0.456 -1.879 r u_axi_dvi/vdata_reg[3]/Q net (fo=11, routed) 1.199 -0.680 u_axi_dvi/vdata_reg_n_0_[3] SLICE_X1Y80 LUT2 (Prop_lut2_I0_O) 0.124 -0.556 f u_axi_dvi/vdata[11]_i_4/O net (fo=3, routed) 0.670 0.114 u_axi_dvi/vdata[11]_i_4_n_0 SLICE_X1Y79 LUT6 (Prop_lut6_I5_O) 0.124 0.238 r u_axi_dvi/video_vsync_OBUF_inst_i_2/O net (fo=1, routed) 0.571 0.810 u_axi_dvi/video_vsync_OBUF_inst_i_2_n_0 SLICE_X1Y80 LUT4 (Prop_lut4_I0_O) 0.124 0.934 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O net (fo=1, routed) 4.979 5.913 video_vsync_OBUF H24 OBUF (Prop_obuf_I_O) 3.551 9.463 r video_vsync_OBUF_inst/O net (fo=0) 0.000 9.463 video_vsync H24 r video_vsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[9]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[9] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.407ns (logic 4.038ns (35.402%) route 7.369ns (64.598%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.020 -2.322 u_confreg/sys_clk SLICE_X0Y84 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.456 -1.866 r u_confreg/led_data_reg[9]_lopt_replica/Q net (fo=1, routed) 7.369 5.503 lopt_15 A23 OBUF (Prop_obuf_I_O) 3.582 9.085 r leds_OBUF[9]_inst/O net (fo=0) 0.000 9.085 leds[9] A23 r leds[9] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[8]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[8] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.228ns (logic 4.155ns (37.007%) route 7.073ns (62.993%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.419 -1.899 r u_confreg/led_data_reg[8]_lopt_replica/Q net (fo=1, routed) 7.073 5.174 lopt_14 C23 OBUF (Prop_obuf_I_O) 3.736 8.910 r leds_OBUF[8]_inst/O net (fo=0) 0.000 8.910 leds[8] C23 r leds[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[2]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 11.173ns (logic 4.043ns (36.183%) route 7.130ns (63.817%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.020 -2.322 u_confreg/sys_clk SLICE_X0Y84 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.456 -1.866 r u_confreg/led_data_reg[2]_lopt_replica/Q net (fo=1, routed) 7.130 5.265 lopt_8 A24 OBUF (Prop_obuf_I_O) 3.587 8.852 r leds_OBUF[2]_inst/O net (fo=0) 0.000 8.852 leds[2] A24 r leds[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_TX (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.783ns (logic 4.124ns (38.250%) route 6.658ns (61.750%)) Logic Levels: 2 (LUT3=1 OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.210 -2.132 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X3Y39 FDRE r u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y39 FDRE (Prop_fdre_C_Q) 0.456 -1.676 f u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/Q net (fo=13, routed) 1.623 -0.052 u_axi_uart_controller/uart0/regs/transmitter/tf_pop_reg_0[1] SLICE_X0Y42 LUT3 (Prop_lut3_I1_O) 0.124 0.072 f u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O net (fo=1, routed) 5.035 5.107 UART_TX_IOBUF_inst/T H18 OBUFT (TriStatE_obuft_T_O) 3.544 8.651 r UART_TX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 8.651 UART_TX H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.945ns (logic 3.998ns (36.523%) route 6.948ns (63.477%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q net (fo=1, routed) 6.948 5.088 dpy1_OBUF[2] E17 OBUF (Prop_obuf_I_O) 3.542 8.630 r dpy1_OBUF[2]_inst/O net (fo=0) 0.000 8.630 dpy1[2] E17 r dpy1[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.860ns (logic 4.001ns (36.837%) route 6.860ns (63.163%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q net (fo=1, routed) 6.860 5.001 dpy0_OBUF[7] C17 OBUF (Prop_obuf_I_O) 3.545 8.546 r dpy0_OBUF[7]_inst/O net (fo=0) 0.000 8.546 dpy0[7] C17 r dpy0[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.784ns (logic 3.995ns (37.049%) route 6.788ns (62.951%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q net (fo=1, routed) 6.788 4.930 dpy0_OBUF[4] E18 OBUF (Prop_obuf_I_O) 3.539 8.469 r dpy0_OBUF[4]_inst/O net (fo=0) 0.000 8.469 dpy0[4] E18 r dpy0[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.693ns (logic 4.012ns (37.523%) route 6.681ns (62.477%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q net (fo=1, routed) 6.681 4.822 dpy0_OBUF[6] B17 OBUF (Prop_obuf_I_O) 3.556 8.379 r dpy0_OBUF[6]_inst/O net (fo=0) 0.000 8.379 dpy0[6] B17 r dpy0[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 10.507ns (logic 4.021ns (38.273%) route 6.486ns (61.727%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q net (fo=1, routed) 6.486 4.626 dpy1_OBUF[0] A17 OBUF (Prop_obuf_I_O) 3.565 8.192 r dpy1_OBUF[0]_inst/O net (fo=0) 0.000 8.192 dpy1[0] A17 r dpy1[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/sclk_reg_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_RX (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.779ns (logic 4.299ns (43.966%) route 5.479ns (56.034%)) Logic Levels: 2 (LUT2=1 OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.209 -2.133 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X6Y42 FDRE r u_axi_uart_controller/uart0/regs/sclk_reg_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y42 FDRE (Prop_fdre_C_Q) 0.478 -1.655 r u_axi_uart_controller/uart0/regs/sclk_reg_reg/Q net (fo=2, routed) 0.825 -0.829 u_axi_uart_controller/uart0/regs/sclk_reg_reg_n_0 SLICE_X6Y41 LUT2 (Prop_lut2_I0_O) 0.301 -0.528 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/O net (fo=1, routed) 4.654 4.126 UART_RX_IOBUF_inst/I J20 OBUFT (Prop_obuft_I_O) 3.520 7.646 r UART_RX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 7.646 UART_RX J20 r UART_RX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.847ns (logic 3.970ns (40.320%) route 5.877ns (59.680%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q net (fo=1, routed) 5.877 4.017 dpy1_OBUF[3] F17 OBUF (Prop_obuf_I_O) 3.514 7.531 r dpy1_OBUF[3]_inst/O net (fo=0) 0.000 7.531 dpy1[3] F17 r dpy1[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[14]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[14] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.844ns (logic 4.019ns (40.824%) route 5.826ns (59.176%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.862 r u_confreg/led_data_reg[14]_lopt_replica/Q net (fo=1, routed) 5.826 3.964 lopt_5 A20 OBUF (Prop_obuf_I_O) 3.563 7.527 r leds_OBUF[14]_inst/O net (fo=0) 0.000 7.527 leds[14] A20 r leds[14] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.776ns (logic 3.998ns (40.890%) route 5.779ns (59.110%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q net (fo=1, routed) 5.779 3.919 dpy1_OBUF[4] E16 OBUF (Prop_obuf_I_O) 3.542 7.461 r dpy1_OBUF[4]_inst/O net (fo=0) 0.000 7.461 dpy1[4] E16 r dpy1[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.751ns (logic 4.001ns (41.036%) route 5.749ns (58.964%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q net (fo=1, routed) 5.749 3.891 dpy0_OBUF[1] D19 OBUF (Prop_obuf_I_O) 3.545 7.436 r dpy0_OBUF[1]_inst/O net (fo=0) 0.000 7.436 dpy0[1] D19 r dpy0[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[1] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.624ns (logic 4.005ns (41.615%) route 5.619ns (58.385%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q net (fo=1, routed) 5.619 3.759 dpy1_OBUF[1] D16 OBUF (Prop_obuf_I_O) 3.549 7.308 r dpy1_OBUF[1]_inst/O net (fo=0) 0.000 7.308 dpy1[1] D16 r dpy1[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.616ns (logic 3.993ns (41.526%) route 5.623ns (58.474%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q net (fo=1, routed) 5.623 3.763 dpy1_OBUF[6] F15 OBUF (Prop_obuf_I_O) 3.537 7.300 r dpy1_OBUF[6]_inst/O net (fo=0) 0.000 7.300 dpy1[6] F15 r dpy1[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.497ns (logic 4.016ns (42.289%) route 5.481ns (57.711%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q net (fo=1, routed) 5.481 3.622 dpy0_OBUF[0] B19 OBUF (Prop_obuf_I_O) 3.560 7.182 r dpy0_OBUF[0]_inst/O net (fo=0) 0.000 7.182 dpy0[0] B19 r dpy0[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.492ns (logic 4.029ns (42.447%) route 5.463ns (57.553%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q net (fo=1, routed) 5.463 3.605 dpy0_OBUF[3] A19 OBUF (Prop_obuf_I_O) 3.573 7.178 r dpy0_OBUF[3]_inst/O net (fo=0) 0.000 7.178 dpy0[3] A19 r dpy0[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[2] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.459ns (logic 4.014ns (42.440%) route 5.445ns (57.560%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q net (fo=1, routed) 5.445 3.586 dpy0_OBUF[2] B21 OBUF (Prop_obuf_I_O) 3.558 7.144 r dpy0_OBUF[2]_inst/O net (fo=0) 0.000 7.144 dpy0[2] B21 r dpy0[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.304ns (logic 4.002ns (43.014%) route 5.302ns (56.986%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q net (fo=1, routed) 5.302 3.443 dpy0_OBUF[5] C19 OBUF (Prop_obuf_I_O) 3.546 6.989 r dpy0_OBUF[5]_inst/O net (fo=0) 0.000 6.989 dpy0[5] C19 r dpy0[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[3]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.295ns (logic 4.153ns (44.682%) route 5.142ns (55.318%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.419 -1.899 r u_confreg/led_data_reg[3]_lopt_replica/Q net (fo=1, routed) 5.142 3.243 lopt_9 D23 OBUF (Prop_obuf_I_O) 3.734 6.977 r leds_OBUF[3]_inst/O net (fo=0) 0.000 6.977 leds[3] D23 r leds[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[5]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.093ns (logic 4.145ns (45.587%) route 4.948ns (54.413%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.419 -1.899 r u_confreg/led_data_reg[5]_lopt_replica/Q net (fo=1, routed) 4.948 3.049 lopt_11 C21 OBUF (Prop_obuf_I_O) 3.726 6.776 r leds_OBUF[5]_inst/O net (fo=0) 0.000 6.776 leds[5] C21 r leds[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[6]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[6] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 9.051ns (logic 3.998ns (44.165%) route 5.054ns (55.835%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.013 -2.329 u_confreg/sys_clk SLICE_X0Y78 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y78 FDRE (Prop_fdre_C_Q) 0.456 -1.873 r u_confreg/led_data_reg[6]_lopt_replica/Q net (fo=1, routed) 5.054 3.181 lopt_12 E20 OBUF (Prop_obuf_I_O) 3.542 6.723 r leds_OBUF[6]_inst/O net (fo=0) 0.000 6.723 leds[6] E20 r leds[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[11]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[11] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.964ns (logic 4.023ns (44.875%) route 4.942ns (55.125%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.862 r u_confreg/led_data_reg[11]_lopt_replica/Q net (fo=1, routed) 4.942 3.080 lopt_2 A18 OBUF (Prop_obuf_I_O) 3.567 6.647 r leds_OBUF[11]_inst/O net (fo=0) 0.000 6.647 leds[11] A18 r leds[11] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[4]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.824ns (logic 4.018ns (45.536%) route 4.806ns (54.464%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.013 -2.329 u_confreg/sys_clk SLICE_X0Y78 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y78 FDRE (Prop_fdre_C_Q) 0.456 -1.873 r u_confreg/led_data_reg[4]_lopt_replica/Q net (fo=1, routed) 4.806 2.933 lopt_10 C22 OBUF (Prop_obuf_I_O) 3.562 6.496 r leds_OBUF[4]_inst/O net (fo=0) 0.000 6.496 leds[4] C22 r leds[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[12]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[12] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.644ns (logic 3.998ns (46.258%) route 4.645ns (53.742%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.022 -2.320 u_confreg/sys_clk SLICE_X0Y85 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y85 FDRE (Prop_fdre_C_Q) 0.456 -1.864 r u_confreg/led_data_reg[12]_lopt_replica/Q net (fo=1, routed) 4.645 2.782 lopt_3 D20 OBUF (Prop_obuf_I_O) 3.542 6.324 r leds_OBUF[12]_inst/O net (fo=0) 0.000 6.324 leds[12] D20 r leds[12] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[10]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[10] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.623ns (logic 4.003ns (46.423%) route 4.620ns (53.577%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.016 -2.326 u_confreg/sys_clk SLICE_X1Y81 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X1Y81 FDRE (Prop_fdre_C_Q) 0.456 -1.870 r u_confreg/led_data_reg[10]_lopt_replica/Q net (fo=1, routed) 4.620 2.750 lopt_1 D21 OBUF (Prop_obuf_I_O) 3.547 6.297 r leds_OBUF[10]_inst/O net (fo=0) 0.000 6.297 leds[10] D21 r leds[10] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[7]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.622ns (logic 4.028ns (46.720%) route 4.594ns (53.280%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.016 -2.326 u_confreg/sys_clk SLICE_X0Y81 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y81 FDRE (Prop_fdre_C_Q) 0.456 -1.870 r u_confreg/led_data_reg[7]_lopt_replica/Q net (fo=1, routed) 4.594 2.724 lopt_13 B22 OBUF (Prop_obuf_I_O) 3.572 6.296 r leds_OBUF[7]_inst/O net (fo=0) 0.000 6.296 leds[7] B22 r leds[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.609ns (logic 4.031ns (46.822%) route 4.578ns (53.178%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.862 r u_confreg/led_data_reg[0]_lopt_replica/Q net (fo=1, routed) 4.578 2.716 lopt B24 OBUF (Prop_obuf_I_O) 3.575 6.291 r leds_OBUF[0]_inst/O net (fo=0) 0.000 6.291 leds[0] B24 r leds[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[15]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[15] (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 8.459ns (logic 4.019ns (47.509%) route 4.440ns (52.491%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.020 -2.322 u_confreg/sys_clk SLICE_X0Y84 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.456 -1.866 r u_confreg/led_data_reg[15]_lopt_replica/Q net (fo=1, routed) 4.440 2.575 lopt_6 B20 OBUF (Prop_obuf_I_O) 3.563 6.138 r leds_OBUF[15]_inst/O net (fo=0) 0.000 6.138 leds[15] B20 r leds[15] (OUT) ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: To Clock: sys_clk Max Delay 43 Endpoints Min Delay 0 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: dip_sw[25] (input port) Destination: u_confreg/s_rdata_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 12.140ns (logic 1.737ns (14.310%) route 10.403ns (85.690%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.930ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.930ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R3 0.000 0.000 r dip_sw[25] (IN) net (fo=0) 0.000 0.000 dip_sw[25] R3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[25]_inst/O net (fo=1, routed) 9.452 10.941 u_confreg/dip_sw_IBUF[25] SLICE_X1Y60 LUT5 (Prop_lut5_I4_O) 0.124 11.065 r u_confreg/s_rdata[25]_i_4/O net (fo=1, routed) 0.951 12.016 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 SLICE_X5Y58 LUT6 (Prop_lut6_I4_O) 0.124 12.140 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O net (fo=1, routed) 0.000 12.140 u_confreg/u_int_ctrl_n_6 SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.898 -1.930 u_confreg/sys_clk SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[25]/C Slack: inf Source: dip_sw[28] (input port) Destination: u_confreg/s_rdata_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 11.642ns (logic 1.716ns (14.736%) route 9.927ns (85.264%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.928ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.928ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R5 0.000 0.000 r dip_sw[28] (IN) net (fo=0) 0.000 0.000 dip_sw[28] R5 IBUF (Prop_ibuf_I_O) 1.468 1.468 r dip_sw_IBUF[28]_inst/O net (fo=1, routed) 8.694 10.162 u_confreg/dip_sw_IBUF[28] SLICE_X12Y58 LUT5 (Prop_lut5_I4_O) 0.124 10.286 r u_confreg/s_rdata[28]_i_4/O net (fo=1, routed) 1.232 11.518 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 SLICE_X3Y58 LUT6 (Prop_lut6_I4_O) 0.124 11.642 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O net (fo=1, routed) 0.000 11.642 u_confreg/u_int_ctrl_n_3 SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.900 -1.928 u_confreg/sys_clk SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[28]/C Slack: inf Source: dip_sw[27] (input port) Destination: u_confreg/s_rdata_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 11.213ns (logic 1.753ns (15.632%) route 9.460ns (84.368%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.930ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.930ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R1 0.000 0.000 r dip_sw[27] (IN) net (fo=0) 0.000 0.000 dip_sw[27] R1 IBUF (Prop_ibuf_I_O) 1.505 1.505 r dip_sw_IBUF[27]_inst/O net (fo=1, routed) 8.793 10.298 u_confreg/dip_sw_IBUF[27] SLICE_X5Y58 LUT5 (Prop_lut5_I4_O) 0.124 10.422 r u_confreg/s_rdata[27]_i_4/O net (fo=1, routed) 0.667 11.089 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 SLICE_X5Y58 LUT6 (Prop_lut6_I4_O) 0.124 11.213 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O net (fo=1, routed) 0.000 11.213 u_confreg/u_int_ctrl_n_4 SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.898 -1.930 u_confreg/sys_clk SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[27]/C Slack: inf Source: dip_sw[7] (input port) Destination: u_confreg/s_rdata_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 11.208ns (logic 1.719ns (15.340%) route 9.489ns (84.660%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.927ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N6 0.000 0.000 r dip_sw[7] (IN) net (fo=0) 0.000 0.000 dip_sw[7] N6 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[7]_inst/O net (fo=1, routed) 8.842 10.313 u_confreg/dip_sw_IBUF[7] SLICE_X3Y56 LUT5 (Prop_lut5_I4_O) 0.124 10.437 r u_confreg/s_rdata[7]_i_4/O net (fo=1, routed) 0.647 11.084 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 SLICE_X3Y56 LUT6 (Prop_lut6_I4_O) 0.124 11.208 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O net (fo=1, routed) 0.000 11.208 u_confreg/u_int_ctrl_n_24 SLICE_X3Y56 FDRE r u_confreg/s_rdata_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.901 -1.927 u_confreg/sys_clk SLICE_X3Y56 FDRE r u_confreg/s_rdata_reg[7]/C Slack: inf Source: dip_sw[4] (input port) Destination: u_confreg/s_rdata_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 11.066ns (logic 1.736ns (15.690%) route 9.330ns (84.310%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.927ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P4 0.000 0.000 r dip_sw[4] (IN) net (fo=0) 0.000 0.000 dip_sw[4] P4 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[4]_inst/O net (fo=1, routed) 8.159 9.647 u_confreg/dip_sw_IBUF[4] SLICE_X0Y59 LUT5 (Prop_lut5_I4_O) 0.124 9.771 r u_confreg/s_rdata[4]_i_4/O net (fo=1, routed) 1.171 10.942 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 SLICE_X1Y53 LUT6 (Prop_lut6_I4_O) 0.124 11.066 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O net (fo=1, routed) 0.000 11.066 u_confreg/u_int_ctrl_n_27 SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.901 -1.927 u_confreg/sys_clk SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[4]/C Slack: inf Source: dip_sw[22] (input port) Destination: u_confreg/s_rdata_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.666ns (logic 1.710ns (16.036%) route 8.955ns (83.964%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P6 0.000 0.000 r dip_sw[22] (IN) net (fo=0) 0.000 0.000 dip_sw[22] P6 IBUF (Prop_ibuf_I_O) 1.462 1.462 r dip_sw_IBUF[22]_inst/O net (fo=1, routed) 8.551 10.013 u_confreg/dip_sw_IBUF[22] SLICE_X9Y61 LUT5 (Prop_lut5_I4_O) 0.124 10.137 r u_confreg/s_rdata[22]_i_4/O net (fo=1, routed) 0.405 10.542 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.124 10.666 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O net (fo=1, routed) 0.000 10.666 u_confreg/u_int_ctrl_n_9 SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.819 -2.009 u_confreg/sys_clk SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[22]/C Slack: inf Source: dip_sw[30] (input port) Destination: u_confreg/s_rdata_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.527ns (logic 1.707ns (16.216%) route 8.820ns (83.784%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R6 0.000 0.000 r dip_sw[30] (IN) net (fo=0) 0.000 0.000 dip_sw[30] R6 IBUF (Prop_ibuf_I_O) 1.459 1.459 r dip_sw_IBUF[30]_inst/O net (fo=1, routed) 8.530 9.989 u_confreg/dip_sw_IBUF[30] SLICE_X9Y60 LUT5 (Prop_lut5_I4_O) 0.124 10.113 r u_confreg/s_rdata[30]_i_4/O net (fo=1, routed) 0.290 10.403 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.124 10.527 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O net (fo=1, routed) 0.000 10.527 u_confreg/u_int_ctrl_n_1 SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.819 -2.009 u_confreg/sys_clk SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[30]/C Slack: inf Source: dip_sw[18] (input port) Destination: u_confreg/s_rdata_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.249ns (logic 1.737ns (16.949%) route 8.512ns (83.051%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.007ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N3 0.000 0.000 r dip_sw[18] (IN) net (fo=0) 0.000 0.000 dip_sw[18] N3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[18]_inst/O net (fo=1, routed) 7.712 9.201 u_confreg/dip_sw_IBUF[18] SLICE_X13Y57 LUT5 (Prop_lut5_I4_O) 0.124 9.325 r u_confreg/s_rdata[18]_i_4/O net (fo=1, routed) 0.800 10.125 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 SLICE_X13Y55 LUT6 (Prop_lut6_I4_O) 0.124 10.249 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O net (fo=1, routed) 0.000 10.249 u_confreg/u_int_ctrl_n_13 SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.821 -2.007 u_confreg/sys_clk SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[18]/C Slack: inf Source: dip_sw[21] (input port) Destination: u_confreg/s_rdata_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.165ns (logic 1.736ns (17.081%) route 8.428ns (82.919%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.007ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N2 0.000 0.000 r dip_sw[21] (IN) net (fo=0) 0.000 0.000 dip_sw[21] N2 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[21]_inst/O net (fo=1, routed) 8.090 9.578 u_confreg/dip_sw_IBUF[21] SLICE_X12Y56 LUT5 (Prop_lut5_I4_O) 0.124 9.702 r u_confreg/s_rdata[21]_i_4/O net (fo=1, routed) 0.339 10.041 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 SLICE_X13Y56 LUT6 (Prop_lut6_I4_O) 0.124 10.165 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O net (fo=1, routed) 0.000 10.165 u_confreg/u_int_ctrl_n_10 SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.821 -2.007 u_confreg/sys_clk SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[21]/C Slack: inf Source: dip_sw[31] (input port) Destination: u_confreg/s_rdata_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 10.112ns (logic 1.742ns (17.224%) route 8.370ns (82.776%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- R2 0.000 0.000 r dip_sw[31] (IN) net (fo=0) 0.000 0.000 dip_sw[31] R2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[31]_inst/O net (fo=1, routed) 8.072 9.566 u_confreg/dip_sw_IBUF[31] SLICE_X9Y61 LUT5 (Prop_lut5_I4_O) 0.124 9.690 r u_confreg/s_rdata[31]_i_6/O net (fo=1, routed) 0.298 9.988 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.124 10.112 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O net (fo=1, routed) 0.000 10.112 u_confreg/u_int_ctrl_n_0 SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.819 -2.009 u_confreg/sys_clk SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[31]/C Slack: inf Source: touch_btn[0] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.728ns (logic 1.499ns (15.408%) route 8.229ns (84.592%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -2.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T2 0.000 0.000 r touch_btn[0] (IN) net (fo=0) 0.000 0.000 touch_btn[0] T2 IBUF (Prop_ibuf_I_O) 1.499 1.499 r touch_btn_IBUF[0]_inst/O net (fo=1, routed) 8.229 9.728 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] SLICE_X8Y57 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.820 -2.008 u_confreg/u_int_ctrl/sys_clk SLICE_X8Y57 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C Slack: inf Source: dip_sw[26] (input port) Destination: u_confreg/s_rdata_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.706ns (logic 1.757ns (18.105%) route 7.949ns (81.895%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.928ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.928ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T4 0.000 0.000 r dip_sw[26] (IN) net (fo=0) 0.000 0.000 dip_sw[26] T4 IBUF (Prop_ibuf_I_O) 1.509 1.509 r dip_sw_IBUF[26]_inst/O net (fo=1, routed) 7.304 8.813 u_confreg/dip_sw_IBUF[26] SLICE_X1Y58 LUT5 (Prop_lut5_I4_O) 0.124 8.937 r u_confreg/s_rdata[26]_i_4/O net (fo=1, routed) 0.645 9.582 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 SLICE_X1Y58 LUT6 (Prop_lut6_I4_O) 0.124 9.706 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O net (fo=1, routed) 0.000 9.706 u_confreg/u_int_ctrl_n_5 SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.900 -1.928 u_confreg/sys_clk SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[26]/C Slack: inf Source: dip_sw[1] (input port) Destination: u_confreg/s_rdata_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.635ns (logic 1.746ns (18.119%) route 7.890ns (81.881%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.928ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.928ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J3 0.000 0.000 r dip_sw[1] (IN) net (fo=0) 0.000 0.000 dip_sw[1] J3 IBUF (Prop_ibuf_I_O) 1.498 1.498 r dip_sw_IBUF[1]_inst/O net (fo=1, routed) 7.101 8.599 u_confreg/dip_sw_IBUF[1] SLICE_X5Y51 LUT5 (Prop_lut5_I4_O) 0.124 8.723 r u_confreg/s_rdata[1]_i_4/O net (fo=1, routed) 0.789 9.511 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 SLICE_X5Y50 LUT6 (Prop_lut6_I4_O) 0.124 9.635 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O net (fo=1, routed) 0.000 9.635 u_confreg/u_int_ctrl_n_30 SLICE_X5Y50 FDRE r u_confreg/s_rdata_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.900 -1.928 u_confreg/sys_clk SLICE_X5Y50 FDRE r u_confreg/s_rdata_reg[1]/C Slack: inf Source: touch_btn[3] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.625ns (logic 1.513ns (15.717%) route 8.112ns (84.283%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -2.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- U2 0.000 0.000 r touch_btn[3] (IN) net (fo=0) 0.000 0.000 touch_btn[3] U2 IBUF (Prop_ibuf_I_O) 1.513 1.513 r touch_btn_IBUF[3]_inst/O net (fo=1, routed) 8.112 9.625 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] SLICE_X10Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.819 -2.009 u_confreg/u_int_ctrl/sys_clk SLICE_X10Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C Slack: inf Source: dip_sw[3] (input port) Destination: u_confreg/s_rdata_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.596ns (logic 1.752ns (18.262%) route 7.843ns (81.738%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.928ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.928ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P1 0.000 0.000 r dip_sw[3] (IN) net (fo=0) 0.000 0.000 dip_sw[3] P1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[3]_inst/O net (fo=1, routed) 7.682 9.186 u_confreg/dip_sw_IBUF[3] SLICE_X4Y51 LUT5 (Prop_lut5_I4_O) 0.124 9.310 r u_confreg/s_rdata[3]_i_4/O net (fo=1, routed) 0.162 9.472 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 SLICE_X4Y51 LUT6 (Prop_lut6_I4_O) 0.124 9.596 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O net (fo=1, routed) 0.000 9.596 u_confreg/u_int_ctrl_n_28 SLICE_X4Y51 FDRE r u_confreg/s_rdata_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.900 -1.928 u_confreg/sys_clk SLICE_X4Y51 FDRE r u_confreg/s_rdata_reg[3]/C Slack: inf Source: dip_sw[12] (input port) Destination: u_confreg/s_rdata_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.409ns (logic 1.717ns (18.250%) route 7.692ns (81.750%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.007ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M5 0.000 0.000 r dip_sw[12] (IN) net (fo=0) 0.000 0.000 dip_sw[12] M5 IBUF (Prop_ibuf_I_O) 1.469 1.469 r dip_sw_IBUF[12]_inst/O net (fo=1, routed) 6.895 8.364 u_confreg/dip_sw_IBUF[12] SLICE_X14Y57 LUT5 (Prop_lut5_I4_O) 0.124 8.488 r u_confreg/s_rdata[12]_i_4/O net (fo=1, routed) 0.797 9.285 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 SLICE_X13Y56 LUT6 (Prop_lut6_I4_O) 0.124 9.409 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O net (fo=1, routed) 0.000 9.409 u_confreg/u_int_ctrl_n_19 SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.821 -2.007 u_confreg/sys_clk SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[12]/C Slack: inf Source: dip_sw[20] (input port) Destination: u_confreg/s_rdata_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.377ns (logic 1.723ns (18.375%) route 7.654ns (81.625%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.928ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.928ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M4 0.000 0.000 r dip_sw[20] (IN) net (fo=0) 0.000 0.000 dip_sw[20] M4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r dip_sw_IBUF[20]_inst/O net (fo=1, routed) 7.206 8.681 u_confreg/dip_sw_IBUF[20] SLICE_X1Y61 LUT5 (Prop_lut5_I4_O) 0.124 8.805 r u_confreg/s_rdata[20]_i_4/O net (fo=1, routed) 0.448 9.253 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 SLICE_X1Y58 LUT6 (Prop_lut6_I4_O) 0.124 9.377 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O net (fo=1, routed) 0.000 9.377 u_confreg/u_int_ctrl_n_11 SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.900 -1.928 u_confreg/sys_clk SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[20]/C Slack: inf Source: touch_btn[1] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.363ns (logic 1.515ns (16.181%) route 7.848ns (83.819%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -2.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.010ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M1 0.000 0.000 r touch_btn[1] (IN) net (fo=0) 0.000 0.000 touch_btn[1] M1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r touch_btn_IBUF[1]_inst/O net (fo=1, routed) 7.848 9.363 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] SLICE_X15Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.818 -2.010 u_confreg/u_int_ctrl/sys_clk SLICE_X15Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C Slack: inf Source: dip_sw[8] (input port) Destination: u_confreg/s_rdata_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.225ns (logic 1.724ns (18.686%) route 7.501ns (81.314%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.005ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.005ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M6 0.000 0.000 r dip_sw[8] (IN) net (fo=0) 0.000 0.000 dip_sw[8] M6 IBUF (Prop_ibuf_I_O) 1.476 1.476 r dip_sw_IBUF[8]_inst/O net (fo=1, routed) 6.702 8.178 u_confreg/dip_sw_IBUF[8] SLICE_X11Y54 LUT5 (Prop_lut5_I4_O) 0.124 8.302 r u_confreg/s_rdata[8]_i_4/O net (fo=1, routed) 0.799 9.101 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 SLICE_X11Y52 LUT6 (Prop_lut6_I4_O) 0.124 9.225 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O net (fo=1, routed) 0.000 9.225 u_confreg/u_int_ctrl_n_23 SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.823 -2.005 u_confreg/sys_clk SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[8]/C Slack: inf Source: dip_sw[17] (input port) Destination: u_confreg/s_rdata_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.190ns (logic 1.752ns (19.066%) route 7.438ns (80.934%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.928ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.928ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K1 0.000 0.000 r dip_sw[17] (IN) net (fo=0) 0.000 0.000 dip_sw[17] K1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[17]_inst/O net (fo=1, routed) 6.773 8.277 u_confreg/dip_sw_IBUF[17] SLICE_X3Y58 LUT5 (Prop_lut5_I4_O) 0.124 8.401 r u_confreg/s_rdata[17]_i_4/O net (fo=1, routed) 0.665 9.066 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 SLICE_X3Y58 LUT6 (Prop_lut6_I4_O) 0.124 9.190 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O net (fo=1, routed) 0.000 9.190 u_confreg/u_int_ctrl_n_14 SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.900 -1.928 u_confreg/sys_clk SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[17]/C Slack: inf Source: dip_sw[23] (input port) Destination: u_confreg/s_rdata_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.174ns (logic 1.766ns (19.255%) route 7.407ns (80.745%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.009ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N1 0.000 0.000 r dip_sw[23] (IN) net (fo=0) 0.000 0.000 dip_sw[23] N1 IBUF (Prop_ibuf_I_O) 1.518 1.518 r dip_sw_IBUF[23]_inst/O net (fo=1, routed) 6.395 7.913 u_confreg/dip_sw_IBUF[23] SLICE_X15Y60 LUT5 (Prop_lut5_I4_O) 0.124 8.037 r u_confreg/s_rdata[23]_i_4/O net (fo=1, routed) 1.013 9.050 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.124 9.174 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O net (fo=1, routed) 0.000 9.174 u_confreg/u_int_ctrl_n_8 SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.819 -2.009 u_confreg/sys_clk SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[23]/C Slack: inf Source: dip_sw[2] (input port) Destination: u_confreg/s_rdata_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.173ns (logic 1.743ns (19.002%) route 7.430ns (80.998%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.927ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M2 0.000 0.000 r dip_sw[2] (IN) net (fo=0) 0.000 0.000 dip_sw[2] M2 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[2]_inst/O net (fo=1, routed) 6.469 7.964 u_confreg/dip_sw_IBUF[2] SLICE_X2Y56 LUT5 (Prop_lut5_I4_O) 0.124 8.088 r u_confreg/s_rdata[2]_i_4/O net (fo=1, routed) 0.961 9.049 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 SLICE_X2Y53 LUT6 (Prop_lut6_I4_O) 0.124 9.173 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O net (fo=1, routed) 0.000 9.173 u_confreg/u_int_ctrl_n_29 SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.901 -1.927 u_confreg/sys_clk SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[2]/C Slack: inf Source: dip_sw[9] (input port) Destination: u_confreg/s_rdata_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.158ns (logic 1.718ns (18.757%) route 7.440ns (81.243%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.007ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- N7 0.000 0.000 r dip_sw[9] (IN) net (fo=0) 0.000 0.000 dip_sw[9] N7 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[9]_inst/O net (fo=1, routed) 6.889 8.359 u_confreg/dip_sw_IBUF[9] SLICE_X13Y57 LUT5 (Prop_lut5_I4_O) 0.124 8.483 r u_confreg/s_rdata[9]_i_4/O net (fo=1, routed) 0.551 9.034 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 SLICE_X13Y55 LUT6 (Prop_lut6_I4_O) 0.124 9.158 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O net (fo=1, routed) 0.000 9.158 u_confreg/u_int_ctrl_n_22 SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.821 -2.007 u_confreg/sys_clk SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[9]/C Slack: inf Source: dip_sw[24] (input port) Destination: u_confreg/s_rdata_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.072ns (logic 1.714ns (18.898%) route 7.358ns (81.102%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P5 0.000 0.000 r dip_sw[24] (IN) net (fo=0) 0.000 0.000 dip_sw[24] P5 IBUF (Prop_ibuf_I_O) 1.466 1.466 r dip_sw_IBUF[24]_inst/O net (fo=1, routed) 6.951 8.417 u_confreg/dip_sw_IBUF[24] SLICE_X15Y58 LUT5 (Prop_lut5_I4_O) 0.124 8.541 r u_confreg/s_rdata[24]_i_4/O net (fo=1, routed) 0.407 8.948 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 SLICE_X15Y58 LUT6 (Prop_lut6_I4_O) 0.124 9.072 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O net (fo=1, routed) 0.000 9.072 u_confreg/u_int_ctrl_n_7 SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.820 -2.008 u_confreg/sys_clk SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[24]/C Slack: inf Source: dip_sw[5] (input port) Destination: u_confreg/s_rdata_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.066ns (logic 1.718ns (18.955%) route 7.347ns (81.045%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.926ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.926ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L5 0.000 0.000 r dip_sw[5] (IN) net (fo=0) 0.000 0.000 dip_sw[5] L5 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[5]_inst/O net (fo=1, routed) 7.193 8.663 u_confreg/dip_sw_IBUF[5] SLICE_X3Y52 LUT5 (Prop_lut5_I4_O) 0.124 8.787 r u_confreg/s_rdata[5]_i_4/O net (fo=1, routed) 0.154 8.942 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 SLICE_X3Y52 LUT6 (Prop_lut6_I4_O) 0.124 9.066 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O net (fo=1, routed) 0.000 9.066 u_confreg/u_int_ctrl_n_26 SLICE_X3Y52 FDRE r u_confreg/s_rdata_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.902 -1.926 u_confreg/sys_clk SLICE_X3Y52 FDRE r u_confreg/s_rdata_reg[5]/C Slack: inf Source: dip_sw[15] (input port) Destination: u_confreg/s_rdata_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.052ns (logic 1.742ns (19.246%) route 7.310ns (80.754%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.927ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L2 0.000 0.000 r dip_sw[15] (IN) net (fo=0) 0.000 0.000 dip_sw[15] L2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[15]_inst/O net (fo=1, routed) 6.630 8.124 u_confreg/dip_sw_IBUF[15] SLICE_X2Y53 LUT5 (Prop_lut5_I4_O) 0.124 8.248 r u_confreg/s_rdata[15]_i_4/O net (fo=1, routed) 0.680 8.928 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 SLICE_X2Y53 LUT6 (Prop_lut6_I4_O) 0.124 9.052 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O net (fo=1, routed) 0.000 9.052 u_confreg/u_int_ctrl_n_16 SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.901 -1.927 u_confreg/sys_clk SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[15]/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED (internal pin) Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 9.038ns (logic 0.124ns (1.372%) route 8.914ns (98.628%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED net (fo=1, routed) 8.281 8.281 pll_clk.u_rst_sys/locked SLICE_X106Y69 LUT1 (Prop_lut1_I0_O) 0.124 8.405 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 0.633 9.038 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X106Y69 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.720 -2.108 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED (internal pin) Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) Data Path Delay: 9.038ns (logic 0.124ns (1.372%) route 8.914ns (98.628%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED net (fo=1, routed) 8.281 8.281 pll_clk.u_rst_sys/locked SLICE_X106Y69 LUT1 (Prop_lut1_I0_O) 0.124 8.405 f pll_clk.u_rst_sys/delay[1]_i_1/O net (fo=2, routed) 0.633 9.038 pll_clk.u_rst_sys/delay[1]_i_1_n_0 SLICE_X106Y69 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.720 -2.108 pll_clk.u_rst_sys/sys_clk SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C Slack: inf Source: dip_sw[10] (input port) Destination: u_confreg/s_rdata_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 9.021ns (logic 1.720ns (19.069%) route 7.301ns (80.931%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.830ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.830ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- M7 0.000 0.000 r dip_sw[10] (IN) net (fo=0) 0.000 0.000 dip_sw[10] M7 IBUF (Prop_ibuf_I_O) 1.472 1.472 r dip_sw_IBUF[10]_inst/O net (fo=1, routed) 7.136 8.608 u_confreg/dip_sw_IBUF[10] SLICE_X10Y49 LUT5 (Prop_lut5_I4_O) 0.124 8.732 r u_confreg/s_rdata[10]_i_4/O net (fo=1, routed) 0.165 8.897 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 SLICE_X10Y49 LUT6 (Prop_lut6_I4_O) 0.124 9.021 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O net (fo=1, routed) 0.000 9.021 u_confreg/u_int_ctrl_n_21 SLICE_X10Y49 FDRE r u_confreg/s_rdata_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.999 -1.830 u_confreg/sys_clk SLICE_X10Y49 FDRE r u_confreg/s_rdata_reg[10]/C Slack: inf Source: dip_sw[19] (input port) Destination: u_confreg/s_rdata_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.878ns (logic 1.726ns (19.444%) route 7.152ns (80.556%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.008ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L4 0.000 0.000 r dip_sw[19] (IN) net (fo=0) 0.000 0.000 dip_sw[19] L4 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[19]_inst/O net (fo=1, routed) 6.997 8.476 u_confreg/dip_sw_IBUF[19] SLICE_X15Y58 LUT5 (Prop_lut5_I4_O) 0.124 8.600 r u_confreg/s_rdata[19]_i_4/O net (fo=1, routed) 0.154 8.754 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 SLICE_X15Y58 LUT6 (Prop_lut6_I4_O) 0.124 8.878 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O net (fo=1, routed) 0.000 8.878 u_confreg/u_int_ctrl_n_12 SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.820 -2.008 u_confreg/sys_clk SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[19]/C Slack: inf Source: dip_sw[14] (input port) Destination: u_confreg/s_rdata_reg[14]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.788ns (logic 1.763ns (20.063%) route 7.024ns (79.937%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.927ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J1 0.000 0.000 r dip_sw[14] (IN) net (fo=0) 0.000 0.000 dip_sw[14] J1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r dip_sw_IBUF[14]_inst/O net (fo=1, routed) 6.870 8.385 u_confreg/dip_sw_IBUF[14] SLICE_X1Y53 LUT5 (Prop_lut5_I4_O) 0.124 8.509 r u_confreg/s_rdata[14]_i_4/O net (fo=1, routed) 0.154 8.664 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 SLICE_X1Y53 LUT6 (Prop_lut6_I4_O) 0.124 8.788 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O net (fo=1, routed) 0.000 8.788 u_confreg/u_int_ctrl_n_17 SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[14]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.901 -1.927 u_confreg/sys_clk SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[14]/C Slack: inf Source: dip_sw[6] (input port) Destination: u_confreg/s_rdata_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.778ns (logic 1.736ns (19.777%) route 7.042ns (80.223%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.007ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L3 0.000 0.000 r dip_sw[6] (IN) net (fo=0) 0.000 0.000 dip_sw[6] L3 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[6]_inst/O net (fo=1, routed) 6.227 7.715 u_confreg/dip_sw_IBUF[6] SLICE_X8Y59 LUT5 (Prop_lut5_I4_O) 0.124 7.839 r u_confreg/s_rdata[6]_i_4/O net (fo=1, routed) 0.815 8.654 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 SLICE_X8Y54 LUT6 (Prop_lut6_I4_O) 0.124 8.778 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O net (fo=1, routed) 0.000 8.778 u_confreg/u_int_ctrl_n_25 SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.821 -2.007 u_confreg/sys_clk SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[6]/C Slack: inf Source: touch_btn[2] (input port) Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.774ns (logic 1.487ns (16.947%) route 7.287ns (83.053%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -2.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.011ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- P3 0.000 0.000 r touch_btn[2] (IN) net (fo=0) 0.000 0.000 touch_btn[2] P3 IBUF (Prop_ibuf_I_O) 1.487 1.487 r touch_btn_IBUF[2]_inst/O net (fo=1, routed) 7.287 8.774 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] SLICE_X9Y62 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.817 -2.011 u_confreg/u_int_ctrl/sys_clk SLICE_X9Y62 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C Slack: inf Source: dip_sw[0] (input port) Destination: u_confreg/s_rdata_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.755ns (logic 1.743ns (19.910%) route 7.012ns (80.090%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.007ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T3 0.000 0.000 r dip_sw[0] (IN) net (fo=0) 0.000 0.000 dip_sw[0] T3 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[0]_inst/O net (fo=1, routed) 6.342 7.837 u_confreg/dip_sw_IBUF[0] SLICE_X8Y54 LUT5 (Prop_lut5_I4_O) 0.124 7.961 r u_confreg/s_rdata[0]_i_4/O net (fo=1, routed) 0.669 8.631 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 SLICE_X8Y54 LUT6 (Prop_lut6_I4_O) 0.124 8.755 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O net (fo=1, routed) 0.000 8.755 u_confreg/u_int_ctrl_n_31 SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.821 -2.007 u_confreg/sys_clk SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[0]/C Slack: inf Source: dip_sw[11] (input port) Destination: u_confreg/s_rdata_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.713ns (logic 1.719ns (19.731%) route 6.994ns (80.269%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.006ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- L7 0.000 0.000 r dip_sw[11] (IN) net (fo=0) 0.000 0.000 dip_sw[11] L7 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[11]_inst/O net (fo=1, routed) 6.840 8.311 u_confreg/dip_sw_IBUF[11] SLICE_X9Y51 LUT5 (Prop_lut5_I4_O) 0.124 8.435 r u_confreg/s_rdata[11]_i_4/O net (fo=1, routed) 0.154 8.589 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 SLICE_X9Y51 LUT6 (Prop_lut6_I4_O) 0.124 8.713 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O net (fo=1, routed) 0.000 8.713 u_confreg/u_int_ctrl_n_20 SLICE_X9Y51 FDRE r u_confreg/s_rdata_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.822 -2.006 u_confreg/sys_clk SLICE_X9Y51 FDRE r u_confreg/s_rdata_reg[11]/C Slack: inf Source: dip_sw[13] (input port) Destination: u_confreg/s_rdata_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.663ns (logic 1.734ns (20.014%) route 6.929ns (79.986%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -2.005ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.005ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K3 0.000 0.000 r dip_sw[13] (IN) net (fo=0) 0.000 0.000 dip_sw[13] K3 IBUF (Prop_ibuf_I_O) 1.486 1.486 r dip_sw_IBUF[13]_inst/O net (fo=1, routed) 6.526 8.012 u_confreg/dip_sw_IBUF[13] SLICE_X10Y52 LUT5 (Prop_lut5_I4_O) 0.124 8.136 r u_confreg/s_rdata[13]_i_4/O net (fo=1, routed) 0.403 8.539 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 SLICE_X11Y52 LUT6 (Prop_lut6_I4_O) 0.124 8.663 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O net (fo=1, routed) 0.000 8.663 u_confreg/u_int_ctrl_n_18 SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.823 -2.005 u_confreg/sys_clk SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[13]/C Slack: inf Source: dip_sw[16] (input port) Destination: u_confreg/s_rdata_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 8.477ns (logic 1.748ns (20.621%) route 6.729ns (79.379%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.927ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.927ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- K2 0.000 0.000 r dip_sw[16] (IN) net (fo=0) 0.000 0.000 dip_sw[16] K2 IBUF (Prop_ibuf_I_O) 1.500 1.500 r dip_sw_IBUF[16]_inst/O net (fo=1, routed) 6.325 7.825 u_confreg/dip_sw_IBUF[16] SLICE_X1Y56 LUT5 (Prop_lut5_I4_O) 0.124 7.949 r u_confreg/s_rdata[16]_i_4/O net (fo=1, routed) 0.405 8.353 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 SLICE_X1Y54 LUT6 (Prop_lut6_I4_O) 0.124 8.477 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O net (fo=1, routed) 0.000 8.477 u_confreg/u_int_ctrl_n_15 SLICE_X1Y54 FDRE r u_confreg/s_rdata_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.901 -1.927 u_confreg/sys_clk SLICE_X1Y54 FDRE r u_confreg/s_rdata_reg[16]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.372ns (logic 1.978ns (26.838%) route 5.393ns (73.162%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) Clock Path Skew: -1.753ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.753ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 4.394 5.868 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X1Y38 LUT2 (Prop_lut2_I1_O) 0.150 6.018 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.999 7.018 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X1Y39 LUT5 (Prop_lut5_I1_O) 0.354 7.372 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O net (fo=1, routed) 0.000 7.372 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.076 -1.753 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C Slack: inf Source: dip_sw[29] (input port) Destination: u_confreg/s_rdata_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 7.370ns (logic 1.726ns (23.422%) route 5.644ns (76.578%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) Clock Path Skew: -1.931ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.931ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- T5 0.000 0.000 r dip_sw[29] (IN) net (fo=0) 0.000 0.000 dip_sw[29] T5 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[29]_inst/O net (fo=1, routed) 5.492 6.970 u_confreg/dip_sw_IBUF[29] SLICE_X5Y59 LUT5 (Prop_lut5_I4_O) 0.124 7.094 r u_confreg/s_rdata[29]_i_4/O net (fo=1, routed) 0.151 7.246 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 SLICE_X5Y59 LUT6 (Prop_lut6_I4_O) 0.124 7.370 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O net (fo=1, routed) 0.000 7.370 u_confreg/u_int_ctrl_n_2 SLICE_X5Y59 FDRE r u_confreg/s_rdata_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 1.897 -1.931 u_confreg/sys_clk SLICE_X5Y59 FDRE r u_confreg/s_rdata_reg[29]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.649ns (logic 1.950ns (29.333%) route 4.699ns (70.667%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) Clock Path Skew: -1.753ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.753ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 4.394 5.868 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X1Y38 LUT2 (Prop_lut2_I1_O) 0.150 6.018 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O net (fo=2, routed) 0.305 6.323 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 SLICE_X1Y39 LUT6 (Prop_lut6_I2_O) 0.326 6.649 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O net (fo=1, routed) 0.000 6.649 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.076 -1.753 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 6.111ns (logic 1.598ns (26.155%) route 4.513ns (73.845%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -1.753ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.753ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 4.513 5.987 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF SLICE_X1Y39 LUT5 (Prop_lut5_I2_O) 0.124 6.111 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O net (fo=1, routed) 0.000 6.111 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.076 -1.753 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C Slack: inf Source: UART_TX (input port) Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.992ns (logic 1.598ns (26.673%) route 4.394ns (73.327%)) Logic Levels: 2 (IBUF=1 LUT5=1) Clock Path Skew: -1.754ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.754ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 r UART_TX_IOBUF_inst/IBUF/O net (fo=4, routed) 4.394 5.868 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF SLICE_X1Y38 LUT5 (Prop_lut5_I0_O) 0.124 5.992 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O net (fo=1, routed) 0.000 5.992 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 SLICE_X1Y38 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.075 -1.754 u_axi_uart_controller/uart0/regs/transmitter/sys_clk SLICE_X1Y38 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C Slack: inf Source: UART_RX (input port) Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) Data Path Delay: 5.968ns (logic 1.590ns (26.636%) route 4.378ns (73.364%)) Logic Levels: 2 (IBUF=1 LUT4=1) Clock Path Skew: -1.752ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.752ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- J20 0.000 0.000 r UART_RX (INOUT) net (fo=1, unset) 0.000 0.000 UART_RX_IOBUF_inst/IO J20 IBUF (Prop_ibuf_I_O) 1.466 1.466 r UART_RX_IOBUF_inst/IBUF/O net (fo=1, routed) 4.378 5.844 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_RX_IBUF SLICE_X0Y42 LUT4 (Prop_lut4_I3_O) 0.124 5.968 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O net (fo=1, routed) 0.000 5.968 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i SLICE_X0Y42 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=35652, routed) 2.077 -1.752 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk SLICE_X0Y42 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C