Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 | Date : Wed Jul 8 02:57:57 2026 | Host : fedora running 64-bit unknown | Command : report_timing -delay_type min -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_withdsp/timing_hold_paths.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Report Slack (MET) : 0.022ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.551ns (logic 0.492ns (89.293%) route 0.059ns (10.707%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X60Y98 RAMD32 0.000 -0.610 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK SLICE_X60Y98 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.118 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.059 -0.059 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6] SLICE_X61Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y98 FDRE (Hold_fdre_C_D) 0.004 -0.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6] ------------------------------------------------------------------- required time 0.082 arrival time -0.059 ------------------------------------------------------------------- slack 0.022 Slack (MET) : 0.022ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.551ns (logic 0.492ns (89.293%) route 0.059ns (10.707%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X60Y98 RAMD32 0.000 -0.610 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK SLICE_X60Y98 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.118 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.059 -0.059 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6] SLICE_X61Y98 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y98 FDRE (Hold_fdre_C_D) 0.004 -0.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6] ------------------------------------------------------------------- required time 0.082 arrival time -0.059 ------------------------------------------------------------------- slack 0.022 Slack (MET) : 0.035ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.558ns (logic 0.394ns (70.668%) route 0.164ns (29.332%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.239 -0.609 SLICE_X56Y94 RAMD32 0.000 -0.609 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.215 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.164 -0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X55Y93 FDRE (Hold_fdre_C_D) -0.002 -0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26] ------------------------------------------------------------------- required time 0.087 arrival time -0.052 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.035ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.558ns (logic 0.394ns (70.668%) route 0.164ns (29.332%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.239 -0.609 SLICE_X56Y94 RAMD32 0.000 -0.609 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.164 -0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] SLICE_X55Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X55Y93 FDRE (Hold_fdre_C_D) -0.002 -0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26] ------------------------------------------------------------------- required time 0.087 arrival time -0.052 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.035ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d2_r_reg[9]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[9]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.445ns (logic 0.249ns (55.966%) route 0.196ns (44.034%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.279ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.449ns Source Clock Delay (SCD): -0.683ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.683 SLICE_X60Y150 FDCE 0.000 -0.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d2_r_reg[9]/C SLICE_X60Y150 FDCE (Prop_fdce_C_Q) 0.148 -0.535 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d2_r_reg[9]/Q net (fo=1, routed) 0.196 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d2_r[9] SLICE_X56Y149 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r[9]_i_1/I0 SLICE_X56Y149 LUT3 (Prop_lut3_I0_O) 0.101 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r[9]_i_1/O net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/p_0_in[9] SLICE_X56Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.498 -0.449 clock pessimism 0.045 -0.404 SLICE_X56Y149 FDCE (Hold_fdce_C_D) 0.131 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[9] ------------------------------------------------------------------- required time 0.273 arrival time -0.238 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.035ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d2_r_reg[9]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[9]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.445ns (logic 0.249ns (55.966%) route 0.196ns (44.034%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.279ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.449ns Source Clock Delay (SCD): -0.683ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.683 SLICE_X60Y150 FDCE 0.000 -0.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d2_r_reg[9]/C SLICE_X60Y150 FDCE (Prop_fdce_C_Q) 0.148 -0.535 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d2_r_reg[9]/Q net (fo=1, routed) 0.196 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d2_r[9] SLICE_X56Y149 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r[9]_i_1/I0 SLICE_X56Y149 LUT3 (Prop_lut3_I0_O) 0.101 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r[9]_i_1/O net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/p_0_in[9] SLICE_X56Y149 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.498 -0.449 clock pessimism 0.045 -0.404 SLICE_X56Y149 FDCE (Hold_fdce_C_D) 0.131 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[9] ------------------------------------------------------------------- required time 0.273 arrival time -0.238 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.036ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.627ns (logic 0.388ns (61.845%) route 0.239ns (38.155%)) Logic Levels: 0 Clock Path Skew: 0.325ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X48Y93 RAMD32 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK SLICE_X48Y93 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 0.239 0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] SLICE_X47Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.565 -0.382 clock pessimism 0.099 -0.283 clock uncertainty 0.197 -0.087 SLICE_X47Y88 FDRE (Hold_fdre_C_D) 0.070 -0.017 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39] ------------------------------------------------------------------- required time 0.017 arrival time 0.019 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.036ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.627ns (logic 0.388ns (61.845%) route 0.239ns (38.155%)) Logic Levels: 0 Clock Path Skew: 0.325ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X48Y93 RAMD32 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK SLICE_X48Y93 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.220 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 0.239 0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] SLICE_X47Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.565 -0.382 clock pessimism 0.099 -0.283 clock uncertainty 0.197 -0.087 SLICE_X47Y88 FDRE (Hold_fdre_C_D) 0.070 -0.017 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39] ------------------------------------------------------------------- required time 0.017 arrival time 0.019 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.044ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.562ns (logic 0.390ns (69.355%) route 0.172ns (30.645%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X62Y94 RAMD32 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.172 -0.051 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y92 FDRE (Hold_fdre_C_D) -0.005 -0.095 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16] ------------------------------------------------------------------- required time 0.095 arrival time -0.051 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.562ns (logic 0.390ns (69.355%) route 0.172ns (30.645%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X62Y94 RAMD32 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.172 -0.051 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] SLICE_X62Y92 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y92 FDRE (Hold_fdre_C_D) -0.005 -0.095 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16] ------------------------------------------------------------------- required time 0.095 arrival time -0.051 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.390ns (69.198%) route 0.174ns (30.802%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y95 RAMD32 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK SLICE_X52Y95 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.218 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.174 -0.045 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[22] SLICE_X52Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X52Y97 FDRE (Hold_fdre_C_D) -0.005 -0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22] ------------------------------------------------------------------- required time 0.089 arrival time -0.045 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.390ns (69.198%) route 0.174ns (30.802%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y95 RAMD32 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK SLICE_X52Y95 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.218 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.174 -0.045 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[22] SLICE_X52Y97 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X52Y97 FDRE (Hold_fdre_C_D) -0.005 -0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22] ------------------------------------------------------------------- required time 0.089 arrival time -0.045 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.368ns (logic 0.141ns (38.293%) route 0.227ns (61.707%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.354ns Source Clock Delay (SCD): -0.582ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.266 -0.582 SLICE_X41Y84 FDCE 0.000 -0.582 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.227 -0.214 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.593 -0.354 clock pessimism -0.215 -0.569 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.259 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.259 arrival time -0.214 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.368ns (logic 0.141ns (38.293%) route 0.227ns (61.707%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.354ns Source Clock Delay (SCD): -0.582ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.266 -0.582 SLICE_X41Y84 FDCE 0.000 -0.582 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.141 -0.441 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.227 -0.214 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X40Y84 RAMD32 f axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.593 -0.354 clock pessimism -0.215 -0.569 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.259 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.259 arrival time -0.214 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.368ns (logic 0.141ns (38.293%) route 0.227ns (61.707%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.354ns Source Clock Delay (SCD): -0.582ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.266 -0.582 SLICE_X41Y84 FDCE 0.000 -0.582 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.227 -0.214 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.593 -0.354 clock pessimism -0.215 -0.569 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.259 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.259 arrival time -0.214 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.368ns (logic 0.141ns (38.293%) route 0.227ns (61.707%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.354ns Source Clock Delay (SCD): -0.582ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.266 -0.582 SLICE_X41Y84 FDCE 0.000 -0.582 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.141 -0.441 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.227 -0.214 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X40Y84 RAMD32 f axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.593 -0.354 clock pessimism -0.215 -0.569 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.259 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.259 arrival time -0.214 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.047ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.569ns (logic 0.394ns (69.239%) route 0.175ns (30.761%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y96 RAMD32 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/CLK SLICE_X52Y96 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 0.175 -0.039 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[32] SLICE_X54Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X54Y98 FDRE (Hold_fdre_C_D) -0.003 -0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32] ------------------------------------------------------------------- required time 0.087 arrival time -0.039 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.569ns (logic 0.394ns (69.239%) route 0.175ns (30.761%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y96 RAMD32 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/CLK SLICE_X52Y96 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.214 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 0.175 -0.039 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[32] SLICE_X54Y98 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X54Y98 FDRE (Hold_fdre_C_D) -0.003 -0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32] ------------------------------------------------------------------- required time 0.087 arrival time -0.039 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.623ns (logic 0.478ns (76.671%) route 0.145ns (23.329%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.239 -0.609 SLICE_X56Y93 RAMD32 0.000 -0.609 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.131 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.145 0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] SLICE_X56Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X56Y92 FDRE (Hold_fdre_C_D) 0.052 -0.034 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19] ------------------------------------------------------------------- required time 0.034 arrival time 0.014 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.623ns (logic 0.478ns (76.671%) route 0.145ns (23.329%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.239 -0.609 SLICE_X56Y93 RAMD32 0.000 -0.609 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.131 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.145 0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] SLICE_X56Y92 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X56Y92 FDRE (Hold_fdre_C_D) 0.052 -0.034 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19] ------------------------------------------------------------------- required time 0.034 arrival time 0.014 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.568ns (logic 0.394ns (69.353%) route 0.174ns (30.647%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.237 -0.611 SLICE_X60Y96 RAMD32 0.000 -0.611 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK SLICE_X60Y96 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.174 -0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[14] SLICE_X61Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y99 FDRE (Hold_fdre_C_D) -0.007 -0.093 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14] ------------------------------------------------------------------- required time 0.093 arrival time -0.043 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.568ns (logic 0.394ns (69.353%) route 0.174ns (30.647%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.237 -0.611 SLICE_X60Y96 RAMD32 0.000 -0.611 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK SLICE_X60Y96 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.217 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.174 -0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[14] SLICE_X61Y99 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y99 FDRE (Hold_fdre_C_D) -0.007 -0.093 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14] ------------------------------------------------------------------- required time 0.093 arrival time -0.043 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.054ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.574ns (logic 0.394ns (68.584%) route 0.180ns (31.416%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.241 -0.607 SLICE_X52Y98 RAMD32 0.000 -0.607 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.180 -0.033 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[26] SLICE_X54Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X54Y98 FDRE (Hold_fdre_C_D) -0.003 -0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26] ------------------------------------------------------------------- required time 0.087 arrival time -0.033 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.054ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.574ns (logic 0.394ns (68.584%) route 0.180ns (31.416%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.241 -0.607 SLICE_X52Y98 RAMD32 0.000 -0.607 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.180 -0.033 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[26] SLICE_X54Y98 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X54Y98 FDRE (Hold_fdre_C_D) -0.003 -0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26] ------------------------------------------------------------------- required time 0.087 arrival time -0.033 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.054ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.651ns (logic 0.478ns (73.473%) route 0.173ns (26.527%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X60Y98 RAMD32 0.000 -0.610 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK SLICE_X60Y98 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.173 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[7] SLICE_X61Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y98 FDRE (Hold_fdre_C_D) 0.072 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7] ------------------------------------------------------------------- required time 0.014 arrival time 0.040 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.054ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.651ns (logic 0.478ns (73.473%) route 0.173ns (26.527%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.238 -0.610 SLICE_X60Y98 RAMD32 0.000 -0.610 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK SLICE_X60Y98 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.132 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.173 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[7] SLICE_X61Y98 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y98 FDRE (Hold_fdre_C_D) 0.072 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7] ------------------------------------------------------------------- required time 0.014 arrival time 0.040 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.054ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_im_reg[127][12]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.412ns (logic 0.209ns (50.735%) route 0.203ns (49.265%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.403ns Source Clock Delay (SCD): -0.632ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.216 -0.632 SLICE_X84Y65 FDRE 0.000 -0.632 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_im_reg[127][12]__0/C SLICE_X84Y65 FDRE (Prop_fdre_C_Q) 0.164 -0.468 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_im_reg[127][12]__0/Q net (fo=6, routed) 0.203 -0.265 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_im_reg[127][14]__0_0[12] SLICE_X81Y62 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/bf1_do_re[12]_i_1__1/I3 SLICE_X81Y62 LUT6 (Prop_lut6_I3_O) 0.045 -0.220 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/bf1_do_re[12]_i_1__1/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_sp_re[12] SLICE_X81Y62 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.544 -0.403 clock pessimism 0.037 -0.366 SLICE_X81Y62 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[12] ------------------------------------------------------------------- required time 0.274 arrival time -0.220 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.054ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_im_reg[127][12]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.412ns (logic 0.209ns (50.735%) route 0.203ns (49.265%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.403ns Source Clock Delay (SCD): -0.632ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.216 -0.632 SLICE_X84Y65 FDRE 0.000 -0.632 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_im_reg[127][12]__0/C SLICE_X84Y65 FDRE (Prop_fdre_C_Q) 0.164 -0.468 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_im_reg[127][12]__0/Q net (fo=6, routed) 0.203 -0.265 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_im_reg[127][14]__0_0[12] SLICE_X81Y62 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/bf1_do_re[12]_i_1__1/I3 SLICE_X81Y62 LUT6 (Prop_lut6_I3_O) 0.045 -0.220 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/bf1_do_re[12]_i_1__1/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_sp_re[12] SLICE_X81Y62 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.544 -0.403 clock pessimism 0.037 -0.366 SLICE_X81Y62 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[12] ------------------------------------------------------------------- required time 0.274 arrival time -0.220 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.056ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.575ns (logic 0.394ns (68.577%) route 0.181ns (31.423%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.237 -0.611 SLICE_X60Y95 RAMD32 0.000 -0.611 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK SLICE_X60Y95 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.181 -0.037 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[2] SLICE_X61Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y97 FDRE (Hold_fdre_C_D) -0.007 -0.093 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2] ------------------------------------------------------------------- required time 0.093 arrival time -0.037 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.056ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.575ns (logic 0.394ns (68.577%) route 0.181ns (31.423%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.237 -0.611 SLICE_X60Y95 RAMD32 0.000 -0.611 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK SLICE_X60Y95 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.217 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.181 -0.037 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[2] SLICE_X61Y97 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y97 FDRE (Hold_fdre_C_D) -0.007 -0.093 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2] ------------------------------------------------------------------- required time 0.093 arrival time -0.037 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.061ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.647ns (logic 0.478ns (73.858%) route 0.169ns (26.142%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.239 -0.609 SLICE_X56Y94 RAMD32 0.000 -0.609 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.131 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.169 0.038 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] SLICE_X56Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X56Y92 FDRE (Hold_fdre_C_D) 0.063 -0.023 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25] ------------------------------------------------------------------- required time 0.023 arrival time 0.038 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.061ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.647ns (logic 0.478ns (73.858%) route 0.169ns (26.142%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.239 -0.609 SLICE_X56Y94 RAMD32 0.000 -0.609 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.131 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.169 0.038 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] SLICE_X56Y92 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X56Y92 FDRE (Hold_fdre_C_D) 0.063 -0.023 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25] ------------------------------------------------------------------- required time 0.023 arrival time 0.038 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.061ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.275ns Source Clock Delay (SCD): -0.508ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.341 -0.508 SLICE_X23Y28 FDRE 0.000 -0.508 r u_cpu/u_csr/csr_tlbelo1_reg[14]/C SLICE_X23Y28 FDRE (Prop_fdre_C_Q) 0.141 -0.367 r u_cpu/u_csr/csr_tlbelo1_reg[14]/Q net (fo=4, routed) 0.080 -0.287 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIA0 SLICE_X22Y28 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.672 -0.275 clock pessimism -0.220 -0.495 SLICE_X22Y28 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.348 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.348 arrival time -0.287 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.061ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.275ns Source Clock Delay (SCD): -0.508ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.341 -0.508 SLICE_X23Y28 FDRE 0.000 -0.508 r u_cpu/u_csr/csr_tlbelo1_reg[14]/C SLICE_X23Y28 FDRE (Prop_fdre_C_Q) 0.141 -0.367 f u_cpu/u_csr/csr_tlbelo1_reg[14]/Q net (fo=4, routed) 0.080 -0.287 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIA0 SLICE_X22Y28 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.672 -0.275 clock pessimism -0.220 -0.495 SLICE_X22Y28 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.348 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.348 arrival time -0.287 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.065ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.591ns (logic 0.390ns (65.936%) route 0.201ns (34.064%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y96 RAMD32 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK SLICE_X52Y96 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.218 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/O net (fo=1, routed) 0.201 -0.017 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[34] SLICE_X53Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X53Y97 FDRE (Hold_fdre_C_D) 0.002 -0.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34] ------------------------------------------------------------------- required time 0.082 arrival time -0.017 ------------------------------------------------------------------- slack 0.065 Slack (MET) : 0.065ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.591ns (logic 0.390ns (65.936%) route 0.201ns (34.064%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y96 RAMD32 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK SLICE_X52Y96 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.218 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/O net (fo=1, routed) 0.201 -0.017 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[34] SLICE_X53Y97 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X53Y97 FDRE (Hold_fdre_C_D) 0.002 -0.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34] ------------------------------------------------------------------- required time 0.082 arrival time -0.017 ------------------------------------------------------------------- slack 0.065 Slack (MET) : 0.065ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/C (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[9]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.385ns (logic 0.186ns (48.253%) route 0.199ns (51.747%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y93 FDRE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/C SLICE_X69Y93 FDRE (Prop_fdre_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/Q net (fo=1, routed) 0.199 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_burst_reg[1]_1[9] SLICE_X70Y100 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[9]_i_1/I0 SLICE_X70Y100 LUT4 (Prop_lut4_I0_O) 0.045 -0.231 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[9]_i_1/O net (fo=1, routed) 0.000 -0.231 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[9] SLICE_X70Y100 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.490 -0.457 clock pessimism 0.040 -0.417 SLICE_X70Y100 FDRE (Hold_fdre_C_D) 0.121 -0.296 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[9] ------------------------------------------------------------------- required time 0.296 arrival time -0.231 ------------------------------------------------------------------- slack 0.065 Slack (MET) : 0.065ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/C (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[9]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.385ns (logic 0.186ns (48.253%) route 0.199ns (51.747%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X69Y93 FDRE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/C SLICE_X69Y93 FDRE (Prop_fdre_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/Q net (fo=1, routed) 0.199 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_burst_reg[1]_1[9] SLICE_X70Y100 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[9]_i_1/I0 SLICE_X70Y100 LUT4 (Prop_lut4_I0_O) 0.045 -0.231 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[9]_i_1/O net (fo=1, routed) 0.000 -0.231 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[9] SLICE_X70Y100 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.490 -0.457 clock pessimism 0.040 -0.417 SLICE_X70Y100 FDRE (Hold_fdre_C_D) 0.121 -0.296 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[9] ------------------------------------------------------------------- required time 0.296 arrival time -0.231 ------------------------------------------------------------------- slack 0.065 Slack (MET) : 0.068ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.595ns (logic 0.492ns (82.730%) route 0.103ns (17.270%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X48Y93 RAMD32 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK SLICE_X48Y93 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.116 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O net (fo=1, routed) 0.103 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] SLICE_X47Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X47Y92 FDRE (Hold_fdre_C_D) 0.004 -0.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36] ------------------------------------------------------------------- required time 0.082 arrival time -0.014 ------------------------------------------------------------------- slack 0.068 Slack (MET) : 0.068ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.595ns (logic 0.492ns (82.730%) route 0.103ns (17.270%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X48Y93 RAMD32 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK SLICE_X48Y93 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.116 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O net (fo=1, routed) 0.103 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] SLICE_X47Y92 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X47Y92 FDRE (Hold_fdre_C_D) 0.004 -0.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36] ------------------------------------------------------------------- required time 0.082 arrival time -0.014 ------------------------------------------------------------------- slack 0.068 Slack (MET) : 0.069ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.391ns (logic 0.141ns (36.049%) route 0.250ns (63.951%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.323ns Source Clock Delay (SCD): -0.552ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.296 -0.552 SLICE_X4Y73 FDCE 0.000 -0.552 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X4Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.250 -0.161 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X6Y73 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.624 -0.323 clock pessimism -0.216 -0.539 SLICE_X6Y73 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.230 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.230 arrival time -0.161 ------------------------------------------------------------------- slack 0.069 Slack (MET) : 0.069ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.391ns (logic 0.141ns (36.049%) route 0.250ns (63.951%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.323ns Source Clock Delay (SCD): -0.552ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.296 -0.552 SLICE_X4Y73 FDCE 0.000 -0.552 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X4Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.250 -0.161 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X6Y73 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.624 -0.323 clock pessimism -0.216 -0.539 SLICE_X6Y73 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.230 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.230 arrival time -0.161 ------------------------------------------------------------------- slack 0.069 Slack (MET) : 0.069ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.391ns (logic 0.141ns (36.049%) route 0.250ns (63.951%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.323ns Source Clock Delay (SCD): -0.552ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.296 -0.552 SLICE_X4Y73 FDCE 0.000 -0.552 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X4Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.250 -0.161 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X6Y73 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.624 -0.323 clock pessimism -0.216 -0.539 SLICE_X6Y73 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.230 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.230 arrival time -0.161 ------------------------------------------------------------------- slack 0.069 Slack (MET) : 0.069ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.391ns (logic 0.141ns (36.049%) route 0.250ns (63.951%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.323ns Source Clock Delay (SCD): -0.552ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.296 -0.552 SLICE_X4Y73 FDCE 0.000 -0.552 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X4Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.250 -0.161 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X6Y73 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.624 -0.323 clock pessimism -0.216 -0.539 SLICE_X6Y73 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.230 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.230 arrival time -0.161 ------------------------------------------------------------------- slack 0.069 Slack (MET) : 0.071ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.575ns (logic 0.394ns (68.577%) route 0.181ns (31.423%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y95 RAMD32 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK SLICE_X52Y95 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.181 -0.034 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[20] SLICE_X52Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X52Y97 FDRE (Hold_fdre_C_D) -0.021 -0.105 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20] ------------------------------------------------------------------- required time 0.105 arrival time -0.034 ------------------------------------------------------------------- slack 0.071 Slack (MET) : 0.071ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.575ns (logic 0.394ns (68.577%) route 0.181ns (31.423%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y95 RAMD32 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK SLICE_X52Y95 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.214 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.181 -0.034 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[20] SLICE_X52Y97 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X52Y97 FDRE (Hold_fdre_C_D) -0.021 -0.105 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20] ------------------------------------------------------------------- required time 0.105 arrival time -0.034 ------------------------------------------------------------------- slack 0.071 Slack (MET) : 0.075ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.650ns (logic 0.478ns (73.492%) route 0.172ns (26.508%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X62Y93 RAMD32 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.172 0.037 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y90 FDRE (Hold_fdre_C_D) 0.052 -0.038 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1] ------------------------------------------------------------------- required time 0.038 arrival time 0.037 ------------------------------------------------------------------- slack 0.075 Slack (MET) : 0.075ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.650ns (logic 0.478ns (73.492%) route 0.172ns (26.508%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X62Y93 RAMD32 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.172 0.037 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] SLICE_X62Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y90 FDRE (Hold_fdre_C_D) 0.052 -0.038 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1] ------------------------------------------------------------------- required time 0.038 arrival time 0.037 ------------------------------------------------------------------- slack 0.075 Slack (MET) : 0.075ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.459ns (logic 0.187ns (40.764%) route 0.272ns (59.236%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/Q net (fo=8, routed) 0.272 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][0] SLICE_X45Y149 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/I1 SLICE_X45Y149 LUT5 (Prop_lut5_I1_O) 0.046 -0.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/O net (fo=1, routed) 0.000 -0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[3] SLICE_X45Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.107 -0.296 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3] ------------------------------------------------------------------- required time 0.296 arrival time -0.221 ------------------------------------------------------------------- slack 0.075 Slack (MET) : 0.075ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.459ns (logic 0.187ns (40.764%) route 0.272ns (59.236%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/Q net (fo=8, routed) 0.272 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][0] SLICE_X45Y149 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/I1 SLICE_X45Y149 LUT5 (Prop_lut5_I1_O) 0.046 -0.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/O net (fo=1, routed) 0.000 -0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[3] SLICE_X45Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.107 -0.296 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3] ------------------------------------------------------------------- required time 0.296 arrival time -0.221 ------------------------------------------------------------------- slack 0.075 Slack (MET) : 0.075ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.459ns (logic 0.187ns (40.764%) route 0.272ns (59.236%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/Q net (fo=8, routed) 0.272 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][0] SLICE_X45Y149 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/I1 SLICE_X45Y149 LUT5 (Prop_lut5_I1_O) 0.046 -0.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/O net (fo=1, routed) 0.000 -0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[3] SLICE_X45Y149 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.107 -0.296 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3] ------------------------------------------------------------------- required time 0.296 arrival time -0.221 ------------------------------------------------------------------- slack 0.075 Slack (MET) : 0.075ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.459ns (logic 0.187ns (40.764%) route 0.272ns (59.236%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/Q net (fo=8, routed) 0.272 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][0] SLICE_X45Y149 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/I1 SLICE_X45Y149 LUT5 (Prop_lut5_I1_O) 0.046 -0.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/O net (fo=1, routed) 0.000 -0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[3] SLICE_X45Y149 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.107 -0.296 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3] ------------------------------------------------------------------- required time 0.296 arrival time -0.221 ------------------------------------------------------------------- slack 0.075 Slack (MET) : 0.076ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.236ns (logic 0.141ns (59.832%) route 0.095ns (40.168%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.279ns Source Clock Delay (SCD): -0.511ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.338 -0.511 SLICE_X23Y25 FDRE 0.000 -0.511 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C SLICE_X23Y25 FDRE (Prop_fdre_C_Q) 0.141 -0.370 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q net (fo=4, routed) 0.095 -0.275 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/DIA0 SLICE_X22Y25 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.668 -0.279 clock pessimism -0.219 -0.498 SLICE_X22Y25 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.351 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA ------------------------------------------------------------------- required time 0.351 arrival time -0.275 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.076ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.236ns (logic 0.141ns (59.832%) route 0.095ns (40.168%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.279ns Source Clock Delay (SCD): -0.511ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.338 -0.511 SLICE_X23Y25 FDRE 0.000 -0.511 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C SLICE_X23Y25 FDRE (Prop_fdre_C_Q) 0.141 -0.370 f u_cpu/u_csr/csr_tlbelo1_reg[26]/Q net (fo=4, routed) 0.095 -0.275 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/DIA0 SLICE_X22Y25 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.668 -0.279 clock pessimism -0.219 -0.498 SLICE_X22Y25 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.351 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA ------------------------------------------------------------------- required time 0.351 arrival time -0.275 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.076ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.675ns (logic 0.478ns (70.764%) route 0.197ns (29.236%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X62Y94 RAMD32 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.197 0.062 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y92 FDRE (Hold_fdre_C_D) 0.076 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13] ------------------------------------------------------------------- required time 0.014 arrival time 0.062 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.076ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.675ns (logic 0.478ns (70.764%) route 0.197ns (29.236%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.235 -0.613 SLICE_X62Y94 RAMD32 0.000 -0.613 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.197 0.062 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] SLICE_X62Y92 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y92 FDRE (Hold_fdre_C_D) 0.076 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13] ------------------------------------------------------------------- required time 0.014 arrival time 0.062 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.081ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_sp_en_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_do_en_reg/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.418ns (logic 0.141ns (33.715%) route 0.277ns (66.285%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.402ns Source Clock Delay (SCD): -0.632ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.216 -0.632 SLICE_X81Y64 FDCE 0.000 -0.632 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_sp_en_reg/C SLICE_X81Y64 FDCE (Prop_fdce_C_Q) 0.141 -0.491 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_sp_en_reg/Q net (fo=12, routed) 0.277 -0.214 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_sp_en SLICE_X87Y61 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_do_en_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.545 -0.402 clock pessimism 0.037 -0.365 SLICE_X87Y61 FDCE (Hold_fdce_C_D) 0.070 -0.295 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_do_en_reg ------------------------------------------------------------------- required time 0.295 arrival time -0.214 ------------------------------------------------------------------- slack 0.081 Slack (MET) : 0.081ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_sp_en_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_do_en_reg/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.418ns (logic 0.141ns (33.715%) route 0.277ns (66.285%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.402ns Source Clock Delay (SCD): -0.632ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.216 -0.632 SLICE_X81Y64 FDCE 0.000 -0.632 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_sp_en_reg/C SLICE_X81Y64 FDCE (Prop_fdce_C_Q) 0.141 -0.491 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_sp_en_reg/Q net (fo=12, routed) 0.277 -0.214 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_sp_en SLICE_X87Y61 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_do_en_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.545 -0.402 clock pessimism 0.037 -0.365 SLICE_X87Y61 FDCE (Hold_fdce_C_D) 0.070 -0.295 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_do_en_reg ------------------------------------------------------------------- required time 0.295 arrival time -0.214 ------------------------------------------------------------------- slack 0.081 Slack (MET) : 0.084ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[7]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC/I (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.239 -0.609 SLICE_X43Y59 FDRE 0.000 -0.609 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[7]/C SLICE_X43Y59 FDRE (Prop_fdre_C_Q) 0.128 -0.481 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[7]/Q net (fo=1, routed) 0.059 -0.422 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIC0 SLICE_X42Y59 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC/I ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism -0.216 -0.596 SLICE_X42Y59 RAMD32 (Hold_ramd32_CLK_I) 0.090 -0.506 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC ------------------------------------------------------------------- required time 0.506 arrival time -0.422 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[7]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC/I (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.239 -0.609 SLICE_X43Y59 FDRE 0.000 -0.609 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[7]/C SLICE_X43Y59 FDRE (Prop_fdre_C_Q) 0.128 -0.481 f u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[7]/Q net (fo=1, routed) 0.059 -0.422 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIC0 SLICE_X42Y59 RAMD32 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC/I ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism -0.216 -0.596 SLICE_X42Y59 RAMD32 (Hold_ramd32_CLK_I) 0.090 -0.506 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC ------------------------------------------------------------------- required time 0.506 arrival time -0.422 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.468ns (logic 0.223ns (47.645%) route 0.245ns (52.355%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/Q net (fo=7, routed) 0.245 -0.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][1] SLICE_X45Y149 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/I2 SLICE_X45Y149 LUT5 (Prop_lut5_I2_O) 0.095 -0.212 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/O net (fo=1, routed) 0.000 -0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[3] SLICE_X45Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.107 -0.296 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3] ------------------------------------------------------------------- required time 0.296 arrival time -0.212 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.468ns (logic 0.223ns (47.645%) route 0.245ns (52.355%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/Q net (fo=7, routed) 0.245 -0.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][1] SLICE_X45Y149 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/I2 SLICE_X45Y149 LUT5 (Prop_lut5_I2_O) 0.095 -0.212 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/O net (fo=1, routed) 0.000 -0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[3] SLICE_X45Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.107 -0.296 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3] ------------------------------------------------------------------- required time 0.296 arrival time -0.212 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.468ns (logic 0.223ns (47.645%) route 0.245ns (52.355%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/Q net (fo=7, routed) 0.245 -0.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][1] SLICE_X45Y149 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/I2 SLICE_X45Y149 LUT5 (Prop_lut5_I2_O) 0.095 -0.212 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/O net (fo=1, routed) 0.000 -0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[3] SLICE_X45Y149 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.107 -0.296 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3] ------------------------------------------------------------------- required time 0.296 arrival time -0.212 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.084ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.468ns (logic 0.223ns (47.645%) route 0.245ns (52.355%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/Q net (fo=7, routed) 0.245 -0.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][1] SLICE_X45Y149 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/I2 SLICE_X45Y149 LUT5 (Prop_lut5_I2_O) 0.095 -0.212 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/O net (fo=1, routed) 0.000 -0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[3] SLICE_X45Y149 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.107 -0.296 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3] ------------------------------------------------------------------- required time 0.296 arrival time -0.212 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.089ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_dc_done_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.446ns (logic 0.186ns (41.696%) route 0.260ns (58.304%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.423ns Source Clock Delay (SCD): -0.644ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.204 -0.644 SLICE_X38Y148 FDCE 0.000 -0.644 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_dc_done_reg/C SLICE_X38Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.503 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_dc_done_reg/Q net (fo=11, routed) 0.260 -0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/dec_dc_done_reg_0 SLICE_X38Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/dec_cidx[0]_i_1/I1 SLICE_X38Y151 LUT6 (Prop_lut6_I1_O) 0.045 -0.198 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/dec_cidx[0]_i_1/O net (fo=1, routed) 0.000 -0.198 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx0_out[0] SLICE_X38Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.524 -0.423 clock pessimism 0.045 -0.378 SLICE_X38Y151 FDCE (Hold_fdce_C_D) 0.091 -0.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx_reg[0] ------------------------------------------------------------------- required time 0.287 arrival time -0.198 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.089ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_dc_done_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.446ns (logic 0.186ns (41.696%) route 0.260ns (58.304%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.423ns Source Clock Delay (SCD): -0.644ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.204 -0.644 SLICE_X38Y148 FDCE 0.000 -0.644 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_dc_done_reg/C SLICE_X38Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.503 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_dc_done_reg/Q net (fo=11, routed) 0.260 -0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/dec_dc_done_reg_0 SLICE_X38Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/dec_cidx[0]_i_1/I1 SLICE_X38Y151 LUT6 (Prop_lut6_I1_O) 0.045 -0.198 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/dec_cidx[0]_i_1/O net (fo=1, routed) 0.000 -0.198 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx0_out[0] SLICE_X38Y151 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.524 -0.423 clock pessimism 0.045 -0.378 SLICE_X38Y151 FDCE (Hold_fdce_C_D) 0.091 -0.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx_reg[0] ------------------------------------------------------------------- required time 0.287 arrival time -0.198 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.090ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.458ns (logic 0.186ns (40.635%) route 0.272ns (59.365%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/Q net (fo=8, routed) 0.272 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][0] SLICE_X45Y149 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/I2 SLICE_X45Y149 LUT4 (Prop_lut4_I2_O) 0.045 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/O net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[2] SLICE_X45Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.091 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2] ------------------------------------------------------------------- required time 0.312 arrival time -0.222 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.090ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.458ns (logic 0.186ns (40.635%) route 0.272ns (59.365%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/Q net (fo=8, routed) 0.272 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][0] SLICE_X45Y149 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/I2 SLICE_X45Y149 LUT4 (Prop_lut4_I2_O) 0.045 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/O net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[2] SLICE_X45Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.091 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2] ------------------------------------------------------------------- required time 0.312 arrival time -0.222 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.090ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.458ns (logic 0.186ns (40.635%) route 0.272ns (59.365%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/Q net (fo=8, routed) 0.272 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][0] SLICE_X45Y149 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/I2 SLICE_X45Y149 LUT4 (Prop_lut4_I2_O) 0.045 -0.222 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/O net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[2] SLICE_X45Y149 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.091 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2] ------------------------------------------------------------------- required time 0.312 arrival time -0.222 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.090ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.458ns (logic 0.186ns (40.635%) route 0.272ns (59.365%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/Q net (fo=8, routed) 0.272 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][0] SLICE_X45Y149 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/I2 SLICE_X45Y149 LUT4 (Prop_lut4_I2_O) 0.045 -0.222 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/O net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[2] SLICE_X45Y149 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.091 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2] ------------------------------------------------------------------- required time 0.312 arrival time -0.222 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.094ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA/I (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.254ns (logic 0.141ns (55.511%) route 0.113ns (44.489%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.239 -0.609 SLICE_X45Y59 FDRE 0.000 -0.609 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[9]/C SLICE_X45Y59 FDRE (Prop_fdre_C_Q) 0.141 -0.468 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[9]/Q net (fo=1, routed) 0.113 -0.355 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/DIA0 SLICE_X44Y59 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA/I ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism -0.216 -0.596 SLICE_X44Y59 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.449 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA ------------------------------------------------------------------- required time 0.449 arrival time -0.355 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.094ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA/I (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.254ns (logic 0.141ns (55.511%) route 0.113ns (44.489%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.239 -0.609 SLICE_X45Y59 FDRE 0.000 -0.609 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[9]/C SLICE_X45Y59 FDRE (Prop_fdre_C_Q) 0.141 -0.468 f u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[9]/Q net (fo=1, routed) 0.113 -0.355 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/DIA0 SLICE_X44Y59 RAMD32 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA/I ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism -0.216 -0.596 SLICE_X44Y59 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.449 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA ------------------------------------------------------------------- required time 0.449 arrival time -0.355 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.094ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.417ns (logic 0.141ns (33.777%) route 0.276ns (66.223%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X43Y85 FDCE 0.000 -0.612 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X43Y85 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.276 -0.195 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X42Y84 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.213 -0.598 SLICE_X42Y84 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.289 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.289 arrival time -0.195 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.094ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.417ns (logic 0.141ns (33.777%) route 0.276ns (66.223%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X43Y85 FDCE 0.000 -0.612 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X43Y85 FDCE (Prop_fdce_C_Q) 0.141 -0.471 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.276 -0.195 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X42Y84 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.213 -0.598 SLICE_X42Y84 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.289 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.289 arrival time -0.195 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.094ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.417ns (logic 0.141ns (33.777%) route 0.276ns (66.223%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X43Y85 FDCE 0.000 -0.612 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X43Y85 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.276 -0.195 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X42Y84 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.213 -0.598 SLICE_X42Y84 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.289 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.289 arrival time -0.195 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.094ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.417ns (logic 0.141ns (33.777%) route 0.276ns (66.223%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X43Y85 FDCE 0.000 -0.612 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X43Y85 FDCE (Prop_fdce_C_Q) 0.141 -0.471 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.276 -0.195 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X42Y84 RAMD32 f axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.213 -0.598 SLICE_X42Y84 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.289 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.289 arrival time -0.195 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMB ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMB ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMC ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMC ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMD ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMD ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/axi_bridge/awaddr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.568ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.280 -0.568 SLICE_X17Y58 FDRE 0.000 -0.568 r u_cpu/axi_bridge/awaddr_reg[0]/C SLICE_X17Y58 FDRE (Prop_fdre_C_Q) 0.141 -0.427 r u_cpu/axi_bridge/awaddr_reg[0]/Q net (fo=1, routed) 0.116 -0.311 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 SLICE_X16Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.214 -0.553 SLICE_X16Y60 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.406 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA ------------------------------------------------------------------- required time 0.406 arrival time -0.311 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/axi_bridge/awaddr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.568ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.280 -0.568 SLICE_X17Y58 FDRE 0.000 -0.568 r u_cpu/axi_bridge/awaddr_reg[0]/C SLICE_X17Y58 FDRE (Prop_fdre_C_Q) 0.141 -0.427 f u_cpu/axi_bridge/awaddr_reg[0]/Q net (fo=1, routed) 0.116 -0.311 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 SLICE_X16Y60 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.214 -0.553 SLICE_X16Y60 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.406 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA ------------------------------------------------------------------- required time 0.406 arrival time -0.311 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.096ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.354ns Source Clock Delay (SCD): -0.582ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.266 -0.582 SLICE_X41Y84 FDCE 0.000 -0.582 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.236 -0.218 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.593 -0.354 clock pessimism -0.215 -0.569 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR1) 0.255 -0.314 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.314 arrival time -0.218 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.354ns Source Clock Delay (SCD): -0.582ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.266 -0.582 SLICE_X41Y84 FDCE 0.000 -0.582 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.128 -0.454 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.236 -0.218 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X40Y84 RAMD32 f axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.593 -0.354 clock pessimism -0.215 -0.569 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR1) 0.255 -0.314 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.314 arrival time -0.218 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.354ns Source Clock Delay (SCD): -0.582ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.266 -0.582 SLICE_X41Y84 FDCE 0.000 -0.582 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.236 -0.218 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.593 -0.354 clock pessimism -0.215 -0.569 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR1) 0.255 -0.314 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.314 arrival time -0.218 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.354ns Source Clock Delay (SCD): -0.582ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.266 -0.582 SLICE_X41Y84 FDCE 0.000 -0.582 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.128 -0.454 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.236 -0.218 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X40Y84 RAMD32 f axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.593 -0.354 clock pessimism -0.215 -0.569 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR1) 0.255 -0.314 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.314 arrival time -0.218 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.097ns (arrival time - required time) Source: u_cpu/axi_bridge/wstrb_reg[2]/C (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): -0.567ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.281 -0.567 SLICE_X11Y54 FDSE 0.000 -0.567 r u_cpu/axi_bridge/wstrb_reg[2]/C SLICE_X11Y54 FDSE (Prop_fdse_C_Q) 0.141 -0.426 r u_cpu/axi_bridge/wstrb_reg[2]/Q net (fo=1, routed) 0.116 -0.310 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0 SLICE_X10Y56 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.611 -0.336 clock pessimism -0.215 -0.551 SLICE_X10Y56 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.407 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- required time 0.407 arrival time -0.310 ------------------------------------------------------------------- slack 0.097 Slack (MET) : 0.097ns (arrival time - required time) Source: u_cpu/axi_bridge/wstrb_reg[2]/C (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): -0.567ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.281 -0.567 SLICE_X11Y54 FDSE 0.000 -0.567 r u_cpu/axi_bridge/wstrb_reg[2]/C SLICE_X11Y54 FDSE (Prop_fdse_C_Q) 0.141 -0.426 f u_cpu/axi_bridge/wstrb_reg[2]/Q net (fo=1, routed) 0.116 -0.310 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0 SLICE_X10Y56 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.611 -0.336 clock pessimism -0.215 -0.551 SLICE_X10Y56 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.407 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- required time 0.407 arrival time -0.310 ------------------------------------------------------------------- slack 0.097 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMB ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMB ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMC ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMC ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMD ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMS32 f u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMD ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.308 -0.541 SLICE_X50Y13 FDRE 0.000 -0.541 r u_cpu/btb/ras_ptr_reg[1]/C SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMS32 f u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.638 -0.309 clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/u_csr/csr_asid_reg[4]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_asid_reg[24][4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.367ns (logic 0.141ns (38.455%) route 0.226ns (61.545%)) Logic Levels: 0 Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.344ns Source Clock Delay (SCD): -0.504ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.345 -0.504 SLICE_X37Y48 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_asid_reg[4]/C SLICE_X37Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_asid_reg[4]/Q net (fo=35, routed) 0.226 -0.137 u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[9]_0[4] SLICE_X33Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_asid_reg[24][4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.603 -0.344 clock pessimism 0.037 -0.307 SLICE_X33Y51 FDRE (Hold_fdre_C_D) 0.072 -0.235 u_cpu/addr_trans/tlb_entry/tlb_asid_reg[24][4] ------------------------------------------------------------------- required time 0.235 arrival time -0.137 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/u_csr/csr_asid_reg[4]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_asid_reg[24][4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.367ns (logic 0.141ns (38.455%) route 0.226ns (61.545%)) Logic Levels: 0 Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.344ns Source Clock Delay (SCD): -0.504ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.345 -0.504 SLICE_X37Y48 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_asid_reg[4]/C SLICE_X37Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/u_csr/csr_asid_reg[4]/Q net (fo=35, routed) 0.226 -0.137 u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[9]_0[4] SLICE_X33Y51 FDRE f u_cpu/addr_trans/tlb_entry/tlb_asid_reg[24][4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.603 -0.344 clock pessimism 0.037 -0.307 SLICE_X33Y51 FDRE (Hold_fdre_C_D) 0.072 -0.235 u_cpu/addr_trans/tlb_entry/tlb_asid_reg[24][4] ------------------------------------------------------------------- required time 0.235 arrival time -0.137 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.100ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_4/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.380ns (logic 0.128ns (33.677%) route 0.252ns (66.323%)) Logic Levels: 0 Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.705 SLICE_X86Y165 FDCE 0.000 -0.705 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3/C SLICE_X86Y165 FDCE (Prop_fdce_C_Q) 0.128 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3/Q net (fo=27, routed) 0.252 -0.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3_0 SLICE_X81Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_4/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X81Y165 FDCE (Hold_fdce_C_D) 0.016 -0.425 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_4 ------------------------------------------------------------------- required time 0.425 arrival time -0.325 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_4/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.380ns (logic 0.128ns (33.677%) route 0.252ns (66.323%)) Logic Levels: 0 Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.144 -0.705 SLICE_X86Y165 FDCE 0.000 -0.705 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3/C SLICE_X86Y165 FDCE (Prop_fdce_C_Q) 0.128 -0.577 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3/Q net (fo=27, routed) 0.252 -0.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3_0 SLICE_X81Y165 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_4/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.466 -0.481 clock pessimism 0.040 -0.441 SLICE_X81Y165 FDCE (Hold_fdce_C_D) 0.016 -0.425 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_4 ------------------------------------------------------------------- required time 0.425 arrival time -0.325 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMB ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMB ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMC ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMC ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMD ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMD ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.678 -0.269 clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1 ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1 ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1 ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1 ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.607ns (logic 0.492ns (81.071%) route 0.115ns (18.929%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.237 -0.611 SLICE_X60Y96 RAMD32 0.000 -0.611 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK SLICE_X60Y96 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.119 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.115 -0.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[12] SLICE_X61Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y98 FDRE (Hold_fdre_C_D) -0.020 -0.106 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12] ------------------------------------------------------------------- required time 0.106 arrival time -0.004 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.607ns (logic 0.492ns (81.071%) route 0.115ns (18.929%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.237 -0.611 SLICE_X60Y96 RAMD32 0.000 -0.611 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK SLICE_X60Y96 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.119 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.115 -0.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[12] SLICE_X61Y98 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y98 FDRE (Hold_fdre_C_D) -0.020 -0.106 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12] ------------------------------------------------------------------- required time 0.106 arrival time -0.004 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.263ns (logic 0.164ns (62.300%) route 0.099ns (37.700%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X48Y94 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[0]/C SLICE_X48Y94 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[0]/Q net (fo=1, routed) 0.099 -0.345 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/DIB0 SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism -0.212 -0.592 SLICE_X46Y93 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.446 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB ------------------------------------------------------------------- required time 0.446 arrival time -0.345 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.263ns (logic 0.164ns (62.300%) route 0.099ns (37.700%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X48Y94 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[0]/C SLICE_X48Y94 FDCE (Prop_fdce_C_Q) 0.164 -0.444 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[0]/Q net (fo=1, routed) 0.099 -0.345 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/DIB0 SLICE_X46Y93 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism -0.212 -0.592 SLICE_X46Y93 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.446 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB ------------------------------------------------------------------- required time 0.446 arrival time -0.345 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.103ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.471ns (logic 0.226ns (47.978%) route 0.245ns (52.022%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/Q net (fo=7, routed) 0.245 -0.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][1] SLICE_X45Y149 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/I1 SLICE_X45Y149 LUT4 (Prop_lut4_I1_O) 0.098 -0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/O net (fo=1, routed) 0.000 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[2] SLICE_X45Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.091 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2] ------------------------------------------------------------------- required time 0.312 arrival time -0.209 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.471ns (logic 0.226ns (47.978%) route 0.245ns (52.022%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/Q net (fo=7, routed) 0.245 -0.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][1] SLICE_X45Y149 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/I1 SLICE_X45Y149 LUT4 (Prop_lut4_I1_O) 0.098 -0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/O net (fo=1, routed) 0.000 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[2] SLICE_X45Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.091 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2] ------------------------------------------------------------------- required time 0.312 arrival time -0.209 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.471ns (logic 0.226ns (47.978%) route 0.245ns (52.022%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.128 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/Q net (fo=7, routed) 0.245 -0.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][1] SLICE_X45Y149 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/I1 SLICE_X45Y149 LUT4 (Prop_lut4_I1_O) 0.098 -0.209 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/O net (fo=1, routed) 0.000 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[2] SLICE_X45Y149 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.091 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2] ------------------------------------------------------------------- required time 0.312 arrival time -0.209 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.471ns (logic 0.226ns (47.978%) route 0.245ns (52.022%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.169 -0.680 SLICE_X45Y150 FDCE 0.000 -0.680 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/C SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.128 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[1]/Q net (fo=7, routed) 0.245 -0.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][1] SLICE_X45Y149 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/I1 SLICE_X45Y149 LUT4 (Prop_lut4_I1_O) 0.098 -0.209 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/O net (fo=1, routed) 0.000 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[2] SLICE_X45Y149 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.499 -0.448 clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.091 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2] ------------------------------------------------------------------- required time 0.312 arrival time -0.209 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.263ns (logic 0.164ns (62.300%) route 0.099ns (37.700%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X48Y94 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[2]/C SLICE_X48Y94 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[2]/Q net (fo=1, routed) 0.099 -0.345 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/DIC0 SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism -0.212 -0.592 SLICE_X46Y93 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.448 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- required time 0.448 arrival time -0.345 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.103ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.263ns (logic 0.164ns (62.300%) route 0.099ns (37.700%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X48Y94 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[2]/C SLICE_X48Y94 FDCE (Prop_fdce_C_Q) 0.164 -0.444 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[2]/Q net (fo=1, routed) 0.099 -0.345 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/DIC0 SLICE_X46Y93 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism -0.212 -0.592 SLICE_X46Y93 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.448 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- required time 0.448 arrival time -0.345 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cdma_matmul_bridge/bank_dst_addr_reg[0][9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cdma_matmul_bridge/cdma_wr_req_dst_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.238ns (logic 0.186ns (78.117%) route 0.052ns (21.883%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X49Y85 FDRE 0.000 -0.612 r u_cdma_matmul_bridge/bank_dst_addr_reg[0][9]/C SLICE_X49Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.471 r u_cdma_matmul_bridge/bank_dst_addr_reg[0][9]/Q net (fo=1, routed) 0.052 -0.419 u_cdma_matmul_bridge/bank_dst_addr_reg[0]_3[9] SLICE_X48Y85 r u_cdma_matmul_bridge/cdma_wr_req_dst[9]_i_1/I5 SLICE_X48Y85 LUT6 (Prop_lut6_I5_O) 0.045 -0.374 r u_cdma_matmul_bridge/cdma_wr_req_dst[9]_i_1/O net (fo=1, routed) 0.000 -0.374 u_cdma_matmul_bridge/cdma_wr_req_dst[9]_i_1_n_0 SLICE_X48Y85 FDRE r u_cdma_matmul_bridge/cdma_wr_req_dst_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.214 -0.599 SLICE_X48Y85 FDRE (Hold_fdre_C_D) 0.121 -0.478 u_cdma_matmul_bridge/cdma_wr_req_dst_reg[9] ------------------------------------------------------------------- required time 0.478 arrival time -0.374 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cdma_matmul_bridge/bank_dst_addr_reg[0][9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cdma_matmul_bridge/cdma_wr_req_dst_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.238ns (logic 0.186ns (78.117%) route 0.052ns (21.883%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.236 -0.612 SLICE_X49Y85 FDRE 0.000 -0.612 r u_cdma_matmul_bridge/bank_dst_addr_reg[0][9]/C SLICE_X49Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.471 f u_cdma_matmul_bridge/bank_dst_addr_reg[0][9]/Q net (fo=1, routed) 0.052 -0.419 u_cdma_matmul_bridge/bank_dst_addr_reg[0]_3[9] SLICE_X48Y85 f u_cdma_matmul_bridge/cdma_wr_req_dst[9]_i_1/I5 SLICE_X48Y85 LUT6 (Prop_lut6_I5_O) 0.045 -0.374 f u_cdma_matmul_bridge/cdma_wr_req_dst[9]_i_1/O net (fo=1, routed) 0.000 -0.374 u_cdma_matmul_bridge/cdma_wr_req_dst[9]_i_1_n_0 SLICE_X48Y85 FDRE f u_cdma_matmul_bridge/cdma_wr_req_dst_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.214 -0.599 SLICE_X48Y85 FDRE (Hold_fdre_C_D) 0.121 -0.478 u_cdma_matmul_bridge/cdma_wr_req_dst_reg[9] ------------------------------------------------------------------- required time 0.478 arrival time -0.374 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[10]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[118][10]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.458ns (logic 0.186ns (40.603%) route 0.272ns (59.397%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.488ns Source Clock Delay (SCD): -0.711ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.138 -0.711 SLICE_X87Y171 FDCE 0.000 -0.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[10]/C SLICE_X87Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[10]/Q net (fo=231, routed) 0.272 -0.298 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] SLICE_X83Y170 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[118][10]_i_1/I2 SLICE_X83Y170 LUT6 (Prop_lut6_I2_O) 0.045 -0.253 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[118][10]_i_1/O net (fo=1, routed) 0.000 -0.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[118][10]_i_1_n_0 SLICE_X83Y170 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[118][10]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.459 -0.488 clock pessimism 0.040 -0.448 SLICE_X83Y170 FDCE (Hold_fdce_C_D) 0.091 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[118][10] ------------------------------------------------------------------- required time 0.357 arrival time -0.253 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.104ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[10]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[118][10]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.458ns (logic 0.186ns (40.603%) route 0.272ns (59.397%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.488ns Source Clock Delay (SCD): -0.711ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.138 -0.711 SLICE_X87Y171 FDCE 0.000 -0.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[10]/C SLICE_X87Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[10]/Q net (fo=231, routed) 0.272 -0.298 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] SLICE_X83Y170 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[118][10]_i_1/I2 SLICE_X83Y170 LUT6 (Prop_lut6_I2_O) 0.045 -0.253 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[118][10]_i_1/O net (fo=1, routed) 0.000 -0.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[118][10]_i_1_n_0 SLICE_X83Y170 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[118][10]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.459 -0.488 clock pessimism 0.040 -0.448 SLICE_X83Y170 FDCE (Hold_fdce_C_D) 0.091 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[118][10] ------------------------------------------------------------------- required time 0.357 arrival time -0.253 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.105ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.265ns (logic 0.141ns (53.280%) route 0.124ns (46.720%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.277ns Source Clock Delay (SCD): -0.510ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.339 -0.510 SLICE_X19Y24 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[10]/C SLICE_X19Y24 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[10]/Q net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/DIB0 SLICE_X16Y23 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.670 -0.277 clock pessimism -0.219 -0.496 SLICE_X16Y23 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.350 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/RAMB ------------------------------------------------------------------- required time 0.350 arrival time -0.245 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.265ns (logic 0.141ns (53.280%) route 0.124ns (46.720%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.277ns Source Clock Delay (SCD): -0.510ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.339 -0.510 SLICE_X19Y24 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[10]/C SLICE_X19Y24 FDRE (Prop_fdre_C_Q) 0.141 -0.369 f u_cpu/u_csr/csr_tlbelo1_reg[10]/Q net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/DIB0 SLICE_X16Y23 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.670 -0.277 clock pessimism -0.219 -0.496 SLICE_X16Y23 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.350 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/RAMB ------------------------------------------------------------------- required time 0.350 arrival time -0.245 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_18_23/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.265ns (logic 0.141ns (53.192%) route 0.124ns (46.808%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.272ns Source Clock Delay (SCD): -0.503ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.346 -0.503 SLICE_X13Y19 FDRE 0.000 -0.503 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C SLICE_X13Y19 FDRE (Prop_fdre_C_Q) 0.141 -0.362 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/Q net (fo=6, routed) 0.124 -0.238 u_regfile/rf_reg_r2_0_31_18_23/DIA0 SLICE_X14Y20 RAMD32 r u_regfile/rf_reg_r2_0_31_18_23/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.675 -0.272 clock pessimism -0.218 -0.490 SLICE_X14Y20 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.343 u_regfile/rf_reg_r2_0_31_18_23/RAMA ------------------------------------------------------------------- required time 0.343 arrival time -0.238 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_18_23/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.265ns (logic 0.141ns (53.192%) route 0.124ns (46.808%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.272ns Source Clock Delay (SCD): -0.503ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.346 -0.503 SLICE_X13Y19 FDRE 0.000 -0.503 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C SLICE_X13Y19 FDRE (Prop_fdre_C_Q) 0.141 -0.362 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/Q net (fo=6, routed) 0.124 -0.238 u_regfile/rf_reg_r2_0_31_18_23/DIA0 SLICE_X14Y20 RAMD32 f u_regfile/rf_reg_r2_0_31_18_23/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.675 -0.272 clock pessimism -0.218 -0.490 SLICE_X14Y20 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.343 u_regfile/rf_reg_r2_0_31_18_23/RAMA ------------------------------------------------------------------- required time 0.343 arrival time -0.238 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X49Y82 FDCE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.494ns (logic 0.186ns (37.665%) route 0.308ns (62.335%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.147 -0.702 SLICE_X79Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/C SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/Q net (fo=118, routed) 0.308 -0.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[35] SLICE_X84Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[845]_i_1/I2 SLICE_X84Y152 LUT4 (Prop_lut4_I2_O) 0.045 -0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[845]_i_1/O net (fo=1, routed) 0.000 -0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]_0 SLICE_X84Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.472 -0.475 clock pessimism 0.040 -0.435 SLICE_X84Y152 FDCE (Hold_fdce_C_D) 0.121 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845] ------------------------------------------------------------------- required time 0.314 arrival time -0.208 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.494ns (logic 0.186ns (37.665%) route 0.308ns (62.335%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.147 -0.702 SLICE_X79Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/C SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/Q net (fo=118, routed) 0.308 -0.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[35] SLICE_X84Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[845]_i_1/I2 SLICE_X84Y152 LUT4 (Prop_lut4_I2_O) 0.045 -0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[845]_i_1/O net (fo=1, routed) 0.000 -0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]_0 SLICE_X84Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.472 -0.475 clock pessimism 0.040 -0.435 SLICE_X84Y152 FDCE (Hold_fdce_C_D) 0.121 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845] ------------------------------------------------------------------- required time 0.314 arrival time -0.208 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.494ns (logic 0.186ns (37.665%) route 0.308ns (62.335%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.147 -0.702 SLICE_X79Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/C SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/Q net (fo=118, routed) 0.308 -0.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[35] SLICE_X84Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[845]_i_1/I2 SLICE_X84Y152 LUT4 (Prop_lut4_I2_O) 0.045 -0.208 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[845]_i_1/O net (fo=1, routed) 0.000 -0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]_0 SLICE_X84Y152 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.472 -0.475 clock pessimism 0.040 -0.435 SLICE_X84Y152 FDCE (Hold_fdce_C_D) 0.121 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845] ------------------------------------------------------------------- required time 0.314 arrival time -0.208 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.494ns (logic 0.186ns (37.665%) route 0.308ns (62.335%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.147 -0.702 SLICE_X79Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/C SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/Q net (fo=118, routed) 0.308 -0.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[35] SLICE_X84Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[845]_i_1/I2 SLICE_X84Y152 LUT4 (Prop_lut4_I2_O) 0.045 -0.208 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[845]_i_1/O net (fo=1, routed) 0.000 -0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]_0 SLICE_X84Y152 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.472 -0.475 clock pessimism 0.040 -0.435 SLICE_X84Y152 FDCE (Hold_fdce_C_D) 0.121 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845] ------------------------------------------------------------------- required time 0.314 arrival time -0.208 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d1_r_reg[6]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[6]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.240ns (logic 0.186ns (77.466%) route 0.054ns (22.534%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.449ns Source Clock Delay (SCD): -0.675ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.675 SLICE_X57Y149 FDCE 0.000 -0.675 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d1_r_reg[6]/C SLICE_X57Y149 FDCE (Prop_fdce_C_Q) 0.141 -0.534 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d1_r_reg[6]/Q net (fo=1, routed) 0.054 -0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d1_r[6] SLICE_X56Y149 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r[6]_i_1/I1 SLICE_X56Y149 LUT3 (Prop_lut3_I1_O) 0.045 -0.435 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r[6]_i_1/O net (fo=1, routed) 0.000 -0.435 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/p_0_in[6] SLICE_X56Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.498 -0.449 clock pessimism -0.213 -0.662 SLICE_X56Y149 FDCE (Hold_fdce_C_D) 0.121 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[6] ------------------------------------------------------------------- required time 0.541 arrival time -0.435 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d1_r_reg[6]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[6]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.240ns (logic 0.186ns (77.466%) route 0.054ns (22.534%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.449ns Source Clock Delay (SCD): -0.675ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.173 -0.675 SLICE_X57Y149 FDCE 0.000 -0.675 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d1_r_reg[6]/C SLICE_X57Y149 FDCE (Prop_fdce_C_Q) 0.141 -0.534 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d1_r_reg[6]/Q net (fo=1, routed) 0.054 -0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d1_r[6] SLICE_X56Y149 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r[6]_i_1/I1 SLICE_X56Y149 LUT3 (Prop_lut3_I1_O) 0.045 -0.435 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r[6]_i_1/O net (fo=1, routed) 0.000 -0.435 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/p_0_in[6] SLICE_X56Y149 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.498 -0.449 clock pessimism -0.213 -0.662 SLICE_X56Y149 FDCE (Hold_fdce_C_D) 0.121 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[6] ------------------------------------------------------------------- required time 0.541 arrival time -0.435 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.110ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/buf_im_reg[7][10]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_do_im_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.394ns (logic 0.209ns (53.059%) route 0.185ns (46.941%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.193ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.313 -0.536 SLICE_X46Y48 FDRE 0.000 -0.536 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/buf_im_reg[7][10]__0/C SLICE_X46Y48 FDRE (Prop_fdre_C_Q) 0.164 -0.372 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/buf_im_reg[7][10]__0/Q net (fo=6, routed) 0.185 -0.187 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/buf_im_reg[7][14]__0_0[10] SLICE_X47Y52 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/bf1_do_im[10]_i_1__3/I2 SLICE_X47Y52 LUT6 (Prop_lut6_I2_O) 0.045 -0.142 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/bf1_do_im[10]_i_1__3/O net (fo=1, routed) 0.000 -0.142 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_sp_im[10] SLICE_X47Y52 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_do_im_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.037 -0.342 SLICE_X47Y52 FDRE (Hold_fdre_C_D) 0.091 -0.251 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_do_im_reg[10] ------------------------------------------------------------------- required time 0.251 arrival time -0.142 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.110ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/buf_im_reg[7][10]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_do_im_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.394ns (logic 0.209ns (53.059%) route 0.185ns (46.941%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.193ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.313 -0.536 SLICE_X46Y48 FDRE 0.000 -0.536 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/buf_im_reg[7][10]__0/C SLICE_X46Y48 FDRE (Prop_fdre_C_Q) 0.164 -0.372 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/buf_im_reg[7][10]__0/Q net (fo=6, routed) 0.185 -0.187 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/buf_im_reg[7][14]__0_0[10] SLICE_X47Y52 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/bf1_do_im[10]_i_1__3/I2 SLICE_X47Y52 LUT6 (Prop_lut6_I2_O) 0.045 -0.142 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/bf1_do_im[10]_i_1__3/O net (fo=1, routed) 0.000 -0.142 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_sp_im[10] SLICE_X47Y52 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_do_im_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.037 -0.342 SLICE_X47Y52 FDRE (Hold_fdre_C_D) 0.091 -0.251 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_do_im_reg[10] ------------------------------------------------------------------- required time 0.251 arrival time -0.142 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_re_reg[127][11]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.470ns (logic 0.209ns (44.512%) route 0.261ns (55.488%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.403ns Source Clock Delay (SCD): -0.632ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.216 -0.632 SLICE_X84Y63 FDRE 0.000 -0.632 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_re_reg[127][11]__0/C SLICE_X84Y63 FDRE (Prop_fdre_C_Q) 0.164 -0.468 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_re_reg[127][11]__0/Q net (fo=6, routed) 0.261 -0.208 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_re_reg[127][14]__0_0[11] SLICE_X81Y62 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/bf1_do_re[11]_i_1__1/I2 SLICE_X81Y62 LUT6 (Prop_lut6_I2_O) 0.045 -0.163 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/bf1_do_re[11]_i_1__1/O net (fo=1, routed) 0.000 -0.163 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_sp_re[11] SLICE_X81Y62 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.544 -0.403 clock pessimism 0.037 -0.366 SLICE_X81Y62 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[11] ------------------------------------------------------------------- required time 0.274 arrival time -0.163 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_re_reg[127][11]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.470ns (logic 0.209ns (44.512%) route 0.261ns (55.488%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.403ns Source Clock Delay (SCD): -0.632ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.216 -0.632 SLICE_X84Y63 FDRE 0.000 -0.632 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_re_reg[127][11]__0/C SLICE_X84Y63 FDRE (Prop_fdre_C_Q) 0.164 -0.468 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_re_reg[127][11]__0/Q net (fo=6, routed) 0.261 -0.208 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_re_reg[127][14]__0_0[11] SLICE_X81Y62 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/bf1_do_re[11]_i_1__1/I2 SLICE_X81Y62 LUT6 (Prop_lut6_I2_O) 0.045 -0.163 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/bf1_do_re[11]_i_1__1/O net (fo=1, routed) 0.000 -0.163 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_sp_re[11] SLICE_X81Y62 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.544 -0.403 clock pessimism 0.037 -0.366 SLICE_X81Y62 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[11] ------------------------------------------------------------------- required time 0.274 arrival time -0.163 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_a_reg[2]__1/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[2].u_mult/prod0/B[13] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.624ns (logic 0.164ns (26.291%) route 0.460ns (73.709%)) Logic Levels: 0 Clock Path Skew: 0.430ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.250ns Source Clock Delay (SCD): -0.639ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.209 -0.639 SLICE_X22Y110 FDRE 0.000 -0.639 r u_matmul_axi_slave/m_in_a_reg[2]__1/C SLICE_X22Y110 FDRE (Prop_fdre_C_Q) 0.164 -0.475 r u_matmul_axi_slave/m_in_a_reg[2]__1/Q net (fo=2, routed) 0.460 -0.015 u_matmul_axi_slave/mult_inst[2].u_mult/Q[13] DSP48_X1Y36 DSP48E1 r u_matmul_axi_slave/mult_inst[2].u_mult/prod0/B[13] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.698 -0.250 clock pessimism 0.040 -0.209 DSP48_X1Y36 DSP48E1 (Hold_dsp48e1_CLK_B[13]) 0.082 -0.127 u_matmul_axi_slave/mult_inst[2].u_mult/prod0 ------------------------------------------------------------------- required time 0.127 arrival time -0.015 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_a_reg[2]__1/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[2].u_mult/prod0/B[13] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.624ns (logic 0.164ns (26.291%) route 0.460ns (73.709%)) Logic Levels: 0 Clock Path Skew: 0.430ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.250ns Source Clock Delay (SCD): -0.639ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.209 -0.639 SLICE_X22Y110 FDRE 0.000 -0.639 r u_matmul_axi_slave/m_in_a_reg[2]__1/C SLICE_X22Y110 FDRE (Prop_fdre_C_Q) 0.164 -0.475 f u_matmul_axi_slave/m_in_a_reg[2]__1/Q net (fo=2, routed) 0.460 -0.015 u_matmul_axi_slave/mult_inst[2].u_mult/Q[13] DSP48_X1Y36 DSP48E1 f u_matmul_axi_slave/mult_inst[2].u_mult/prod0/B[13] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.698 -0.250 clock pessimism 0.040 -0.209 DSP48_X1Y36 DSP48E1 (Hold_dsp48e1_CLK_B[13]) 0.082 -0.127 u_matmul_axi_slave/mult_inst[2].u_mult/prod0 ------------------------------------------------------------------- required time 0.127 arrival time -0.015 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[4]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.273ns (logic 0.141ns (51.636%) route 0.132ns (48.364%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.273ns Source Clock Delay (SCD): -0.505ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.344 -0.505 SLICE_X15Y27 FDRE 0.000 -0.505 r u_cpu/u_csr/csr_tlbelo1_reg[4]/C SLICE_X15Y27 FDRE (Prop_fdre_C_Q) 0.141 -0.364 r u_cpu/u_csr/csr_tlbelo1_reg[4]/Q net (fo=7, routed) 0.132 -0.232 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/D SLICE_X14Y28 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.674 -0.273 clock pessimism -0.218 -0.491 SLICE_X14Y28 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.345 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/SP ------------------------------------------------------------------- required time 0.345 arrival time -0.232 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[4]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.273ns (logic 0.141ns (51.636%) route 0.132ns (48.364%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.273ns Source Clock Delay (SCD): -0.505ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.344 -0.505 SLICE_X15Y27 FDRE 0.000 -0.505 r u_cpu/u_csr/csr_tlbelo1_reg[4]/C SLICE_X15Y27 FDRE (Prop_fdre_C_Q) 0.141 -0.364 f u_cpu/u_csr/csr_tlbelo1_reg[4]/Q net (fo=7, routed) 0.132 -0.232 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/D SLICE_X14Y28 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.674 -0.273 clock pessimism -0.218 -0.491 SLICE_X14Y28 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.345 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/SP ------------------------------------------------------------------- required time 0.345 arrival time -0.232 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.114ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.830ns (logic 0.367ns (44.206%) route 0.463ns (55.794%)) Logic Levels: 0 Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.418ns Source Clock Delay (SCD): -2.030ns Clock Pessimism Removal (CPR): -0.409ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -5.674 -5.674 propagated clock network latency 3.644 -2.030 SLICE_X41Y84 FDCE 0.000 -2.030 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.367 -1.663 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.463 -1.200 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.858 -2.418 clock pessimism 0.409 -2.008 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR0) 0.694 -1.314 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 1.314 arrival time -1.200 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.114ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.830ns (logic 0.367ns (44.206%) route 0.463ns (55.794%)) Logic Levels: 0 Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.418ns Source Clock Delay (SCD): -2.030ns Clock Pessimism Removal (CPR): -0.409ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -5.674 -5.674 propagated clock network latency 3.644 -2.030 SLICE_X41Y84 FDCE 0.000 -2.030 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.367 -1.663 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.463 -1.200 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X40Y84 RAMD32 f axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.858 -2.418 clock pessimism 0.409 -2.008 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR0) 0.694 -1.314 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 1.314 arrival time -1.200 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.114ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.830ns (logic 0.367ns (44.206%) route 0.463ns (55.794%)) Logic Levels: 0 Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.418ns Source Clock Delay (SCD): -2.030ns Clock Pessimism Removal (CPR): -0.409ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -5.674 -5.674 propagated clock network latency 3.644 -2.030 SLICE_X41Y84 FDCE 0.000 -2.030 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.367 -1.663 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.463 -1.200 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.858 -2.418 clock pessimism 0.409 -2.008 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR0) 0.694 -1.314 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 1.314 arrival time -1.200 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.114ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.830ns (logic 0.367ns (44.206%) route 0.463ns (55.794%)) Logic Levels: 0 Clock Path Skew: 0.022ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.418ns Source Clock Delay (SCD): -2.030ns Clock Pessimism Removal (CPR): -0.409ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -5.674 -5.674 propagated clock network latency 3.644 -2.030 SLICE_X41Y84 FDCE 0.000 -2.030 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.367 -1.663 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.463 -1.200 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X40Y84 RAMD32 f axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency 3.858 -2.418 clock pessimism 0.409 -2.008 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR0) 0.694 -1.314 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 1.314 arrival time -1.200 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.115ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.708ns (logic 0.478ns (67.468%) route 0.230ns (32.532%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.241 -0.607 SLICE_X52Y98 RAMD32 0.000 -0.607 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.129 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.230 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] SLICE_X55Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X55Y98 FDRE (Hold_fdre_C_D) 0.070 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25] ------------------------------------------------------------------- required time 0.014 arrival time 0.101 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.115ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.708ns (logic 0.478ns (67.468%) route 0.230ns (32.532%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.241 -0.607 SLICE_X52Y98 RAMD32 0.000 -0.607 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.129 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.230 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] SLICE_X55Y98 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X55Y98 FDRE (Hold_fdre_C_D) 0.070 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25] ------------------------------------------------------------------- required time 0.014 arrival time 0.101 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.116ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.274ns (logic 0.141ns (51.492%) route 0.133ns (48.508%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.273ns Source Clock Delay (SCD): -0.505ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.344 -0.505 SLICE_X15Y27 FDRE 0.000 -0.505 r u_cpu/u_csr/csr_tlbelo1_reg[5]/C SLICE_X15Y27 FDRE (Prop_fdre_C_Q) 0.141 -0.364 r u_cpu/u_csr/csr_tlbelo1_reg[5]/Q net (fo=7, routed) 0.133 -0.231 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/D SLICE_X14Y28 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.674 -0.273 clock pessimism -0.218 -0.491 SLICE_X14Y28 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.347 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/SP ------------------------------------------------------------------- required time 0.347 arrival time -0.231 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.274ns (logic 0.141ns (51.492%) route 0.133ns (48.508%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.273ns Source Clock Delay (SCD): -0.505ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.344 -0.505 SLICE_X15Y27 FDRE 0.000 -0.505 r u_cpu/u_csr/csr_tlbelo1_reg[5]/C SLICE_X15Y27 FDRE (Prop_fdre_C_Q) 0.141 -0.364 f u_cpu/u_csr/csr_tlbelo1_reg[5]/Q net (fo=7, routed) 0.133 -0.231 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/D SLICE_X14Y28 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.674 -0.273 clock pessimism -0.218 -0.491 SLICE_X14Y28 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.347 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/SP ------------------------------------------------------------------- required time 0.347 arrival time -0.231 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.515ns (logic 0.186ns (36.124%) route 0.329ns (63.876%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.278ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.147 -0.702 SLICE_X79Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/C SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/Q net (fo=118, routed) 0.329 -0.232 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[707] SLICE_X80Y146 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[963]_i_1/I2 SLICE_X80Y146 LUT4 (Prop_lut4_I2_O) 0.045 -0.187 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[963]_i_1/O net (fo=1, routed) 0.000 -0.187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]_0 SLICE_X80Y146 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.478 -0.469 clock pessimism 0.045 -0.424 SLICE_X80Y146 FDCE (Hold_fdce_C_D) 0.121 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963] ------------------------------------------------------------------- required time 0.303 arrival time -0.187 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.515ns (logic 0.186ns (36.124%) route 0.329ns (63.876%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.278ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.147 -0.702 SLICE_X79Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/C SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/Q net (fo=118, routed) 0.329 -0.232 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[707] SLICE_X80Y146 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[963]_i_1/I2 SLICE_X80Y146 LUT4 (Prop_lut4_I2_O) 0.045 -0.187 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[963]_i_1/O net (fo=1, routed) 0.000 -0.187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]_0 SLICE_X80Y146 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.478 -0.469 clock pessimism 0.045 -0.424 SLICE_X80Y146 FDCE (Hold_fdce_C_D) 0.121 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963] ------------------------------------------------------------------- required time 0.303 arrival time -0.187 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.515ns (logic 0.186ns (36.124%) route 0.329ns (63.876%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.278ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.147 -0.702 SLICE_X79Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/C SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/Q net (fo=118, routed) 0.329 -0.232 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[707] SLICE_X80Y146 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[963]_i_1/I2 SLICE_X80Y146 LUT4 (Prop_lut4_I2_O) 0.045 -0.187 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[963]_i_1/O net (fo=1, routed) 0.000 -0.187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]_0 SLICE_X80Y146 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.478 -0.469 clock pessimism 0.045 -0.424 SLICE_X80Y146 FDCE (Hold_fdce_C_D) 0.121 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963] ------------------------------------------------------------------- required time 0.303 arrival time -0.187 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.515ns (logic 0.186ns (36.124%) route 0.329ns (63.876%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.278ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.147 -0.702 SLICE_X79Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/C SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/Q net (fo=118, routed) 0.329 -0.232 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[707] SLICE_X80Y146 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[963]_i_1/I2 SLICE_X80Y146 LUT4 (Prop_lut4_I2_O) 0.045 -0.187 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[963]_i_1/O net (fo=1, routed) 0.000 -0.187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]_0 SLICE_X80Y146 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.478 -0.469 clock pessimism 0.045 -0.424 SLICE_X80Y146 FDCE (Hold_fdce_C_D) 0.121 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963] ------------------------------------------------------------------- required time 0.303 arrival time -0.187 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.273ns (logic 0.141ns (51.645%) route 0.132ns (48.355%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.275ns Source Clock Delay (SCD): -0.507ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.342 -0.507 SLICE_X19Y27 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[24]/C SLICE_X19Y27 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[24]/Q net (fo=4, routed) 0.132 -0.234 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIC0 SLICE_X18Y27 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.672 -0.275 clock pessimism -0.219 -0.494 SLICE_X18Y27 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.350 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMC ------------------------------------------------------------------- required time 0.350 arrival time -0.234 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.273ns (logic 0.141ns (51.645%) route 0.132ns (48.355%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.275ns Source Clock Delay (SCD): -0.507ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.342 -0.507 SLICE_X19Y27 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[24]/C SLICE_X19Y27 FDRE (Prop_fdre_C_Q) 0.141 -0.366 f u_cpu/u_csr/csr_tlbelo1_reg[24]/Q net (fo=4, routed) 0.132 -0.234 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIC0 SLICE_X18Y27 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.672 -0.275 clock pessimism -0.219 -0.494 SLICE_X18Y27 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.350 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMC ------------------------------------------------------------------- required time 0.350 arrival time -0.234 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[40]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_6_11/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.275ns (logic 0.141ns (51.258%) route 0.134ns (48.742%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.502ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.347 -0.502 SLICE_X19Y16 FDRE 0.000 -0.502 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[40]/C SLICE_X19Y16 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[40]/Q net (fo=6, routed) 0.134 -0.227 u_regfile/rf_reg_r1_0_31_6_11/DIB0 SLICE_X18Y17 RAMD32 r u_regfile/rf_reg_r1_0_31_6_11/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.219 -0.489 SLICE_X18Y17 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.343 u_regfile/rf_reg_r1_0_31_6_11/RAMB ------------------------------------------------------------------- required time 0.343 arrival time -0.227 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[40]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_6_11/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.275ns (logic 0.141ns (51.258%) route 0.134ns (48.742%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.502ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.347 -0.502 SLICE_X19Y16 FDRE 0.000 -0.502 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[40]/C SLICE_X19Y16 FDRE (Prop_fdre_C_Q) 0.141 -0.361 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[40]/Q net (fo=6, routed) 0.134 -0.227 u_regfile/rf_reg_r1_0_31_6_11/DIB0 SLICE_X18Y17 RAMD32 f u_regfile/rf_reg_r1_0_31_6_11/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.219 -0.489 SLICE_X18Y17 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.343 u_regfile/rf_reg_r1_0_31_6_11/RAMB ------------------------------------------------------------------- required time 0.343 arrival time -0.227 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1 ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1 ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1 ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X52Y93 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMS32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.566 -0.381 clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1 ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.117ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.712ns (logic 0.388ns (54.475%) route 0.324ns (45.525%)) Logic Levels: 0 Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X48Y82 RAMD32 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/O net (fo=1, routed) 0.324 0.098 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[3] SLICE_X51Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X51Y94 FDRE (Hold_fdre_C_D) 0.066 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3] ------------------------------------------------------------------- required time 0.019 arrival time 0.098 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.712ns (logic 0.388ns (54.475%) route 0.324ns (45.525%)) Logic Levels: 0 Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X48Y82 RAMD32 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/O net (fo=1, routed) 0.324 0.098 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[3] SLICE_X51Y94 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X51Y94 FDRE (Hold_fdre_C_D) 0.066 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3] ------------------------------------------------------------------- required time 0.019 arrival time 0.098 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_cpu/axi_bridge/wstrb_reg[1]/C (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): -0.567ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.281 -0.567 SLICE_X11Y54 FDSE 0.000 -0.567 r u_cpu/axi_bridge/wstrb_reg[1]/C SLICE_X11Y54 FDSE (Prop_fdse_C_Q) 0.141 -0.426 r u_cpu/axi_bridge/wstrb_reg[1]/Q net (fo=1, routed) 0.116 -0.310 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIB1 SLICE_X10Y56 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.611 -0.336 clock pessimism -0.215 -0.551 SLICE_X10Y56 RAMD32 (Hold_ramd32_CLK_I) 0.124 -0.427 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1 ------------------------------------------------------------------- required time 0.427 arrival time -0.310 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.117ns (arrival time - required time) Source: u_cpu/axi_bridge/wstrb_reg[1]/C (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): -0.567ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.281 -0.567 SLICE_X11Y54 FDSE 0.000 -0.567 r u_cpu/axi_bridge/wstrb_reg[1]/C SLICE_X11Y54 FDSE (Prop_fdse_C_Q) 0.141 -0.426 f u_cpu/axi_bridge/wstrb_reg[1]/Q net (fo=1, routed) 0.116 -0.310 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIB1 SLICE_X10Y56 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.611 -0.336 clock pessimism -0.215 -0.551 SLICE_X10Y56 RAMD32 (Hold_ramd32_CLK_I) 0.124 -0.427 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1 ------------------------------------------------------------------- required time 0.427 arrival time -0.310 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.118ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.278ns (logic 0.141ns (50.687%) route 0.137ns (49.313%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.274ns Source Clock Delay (SCD): -0.507ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.342 -0.507 SLICE_X17Y27 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[22]/C SLICE_X17Y27 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[22]/Q net (fo=4, routed) 0.137 -0.229 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/DIB0 SLICE_X18Y28 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.673 -0.274 clock pessimism -0.219 -0.493 SLICE_X18Y28 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/RAMB ------------------------------------------------------------------- required time 0.347 arrival time -0.229 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.118ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.278ns (logic 0.141ns (50.687%) route 0.137ns (49.313%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.274ns Source Clock Delay (SCD): -0.507ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.342 -0.507 SLICE_X17Y27 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[22]/C SLICE_X17Y27 FDRE (Prop_fdre_C_Q) 0.141 -0.366 f u_cpu/u_csr/csr_tlbelo1_reg[22]/Q net (fo=4, routed) 0.137 -0.229 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/DIB0 SLICE_X18Y28 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.673 -0.274 clock pessimism -0.219 -0.493 SLICE_X18Y28 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/RAMB ------------------------------------------------------------------- required time 0.347 arrival time -0.229 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_tg_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_sync_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.522ns (logic 0.164ns (31.430%) route 0.358ns (68.570%)) Logic Levels: 0 Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.676 SLICE_X56Y105 FDCE 0.000 -0.676 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_tg_reg/C SLICE_X56Y105 FDCE (Prop_fdce_C_Q) 0.164 -0.512 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_tg_reg/Q net (fo=2, routed) 0.358 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_tg_reg_n_0 SLICE_X63Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_sync_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism 0.040 -0.343 SLICE_X63Y99 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_sync_reg[0] ------------------------------------------------------------------- required time 0.273 arrival time -0.154 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_tg_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_sync_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.522ns (logic 0.164ns (31.430%) route 0.358ns (68.570%)) Logic Levels: 0 Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.676 SLICE_X56Y105 FDCE 0.000 -0.676 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_tg_reg/C SLICE_X56Y105 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_tg_reg/Q net (fo=2, routed) 0.358 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_tg_reg_n_0 SLICE_X63Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_sync_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism 0.040 -0.343 SLICE_X63Y99 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_sync_reg[0] ------------------------------------------------------------------- required time 0.273 arrival time -0.154 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.465ns Source Clock Delay (SCD): -0.691ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.158 -0.691 SLICE_X67Y161 FDCE 0.000 -0.691 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[1]/C SLICE_X67Y161 FDCE (Prop_fdce_C_Q) 0.141 -0.550 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[1]/Q net (fo=1, routed) 0.056 -0.494 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2[1] SLICE_X67Y161 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.482 -0.465 clock pessimism -0.226 -0.691 SLICE_X67Y161 FDCE (Hold_fdce_C_D) 0.078 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[1] ------------------------------------------------------------------- required time 0.613 arrival time -0.494 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.465ns Source Clock Delay (SCD): -0.691ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.158 -0.691 SLICE_X67Y161 FDCE 0.000 -0.691 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[1]/C SLICE_X67Y161 FDCE (Prop_fdce_C_Q) 0.141 -0.550 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[1]/Q net (fo=1, routed) 0.056 -0.494 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2[1] SLICE_X67Y161 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.482 -0.465 clock pessimism -0.226 -0.691 SLICE_X67Y161 FDCE (Hold_fdce_C_D) 0.078 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[1] ------------------------------------------------------------------- required time 0.613 arrival time -0.494 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X67Y95 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[3] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.078 -0.538 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.538 arrival time -0.419 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X67Y95 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[3] SLICE_X67Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.078 -0.538 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.538 arrival time -0.419 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.633ns (logic 0.492ns (77.772%) route 0.141ns (22.228%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.241 -0.607 SLICE_X52Y98 RAMD32 0.000 -0.607 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.115 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.141 0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] SLICE_X53Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X53Y99 FDRE (Hold_fdre_C_D) -0.011 -0.095 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24] ------------------------------------------------------------------- required time 0.095 arrival time 0.025 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.633ns (logic 0.492ns (77.772%) route 0.141ns (22.228%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.241 -0.607 SLICE_X52Y98 RAMD32 0.000 -0.607 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.115 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.141 0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] SLICE_X53Y99 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.568 -0.379 clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X53Y99 FDRE (Hold_fdre_C_D) -0.011 -0.095 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24] ------------------------------------------------------------------- required time 0.095 arrival time 0.025 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[16]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.465ns Source Clock Delay (SCD): -0.691ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.158 -0.691 SLICE_X67Y161 FDCE 0.000 -0.691 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/C SLICE_X67Y161 FDCE (Prop_fdce_C_Q) 0.141 -0.550 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/Q net (fo=1, routed) 0.056 -0.494 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2[16] SLICE_X67Y161 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.482 -0.465 clock pessimism -0.226 -0.691 SLICE_X67Y161 FDCE (Hold_fdce_C_D) 0.076 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[16] ------------------------------------------------------------------- required time 0.615 arrival time -0.494 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[16]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.465ns Source Clock Delay (SCD): -0.691ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.158 -0.691 SLICE_X67Y161 FDCE 0.000 -0.691 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/C SLICE_X67Y161 FDCE (Prop_fdce_C_Q) 0.141 -0.550 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/Q net (fo=1, routed) 0.056 -0.494 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2[16] SLICE_X67Y161 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.482 -0.465 clock pessimism -0.226 -0.691 SLICE_X67Y161 FDCE (Hold_fdce_C_D) 0.076 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[16] ------------------------------------------------------------------- required time 0.615 arrival time -0.494 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X69Y91 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.076 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.541 arrival time -0.420 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X69Y91 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X69Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.076 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.541 arrival time -0.420 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X73Y93 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C SLICE_X73Y93 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X73Y93 FDCE (Hold_fdce_C_D) 0.076 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.541 arrival time -0.420 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X73Y93 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C SLICE_X73Y93 FDCE (Prop_fdce_C_Q) 0.141 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X73Y93 FDCE (Hold_fdce_C_D) 0.076 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.541 arrival time -0.420 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X67Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C SLICE_X67Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2] SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.229 -0.616 SLICE_X67Y96 FDCE (Hold_fdce_C_D) 0.076 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.540 arrival time -0.419 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X67Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C SLICE_X67Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2] SLICE_X67Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.229 -0.616 SLICE_X67Y96 FDCE (Hold_fdce_C_D) 0.076 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.540 arrival time -0.419 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X67Y95 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[2] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.076 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.540 arrival time -0.419 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X67Y95 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[2] SLICE_X67Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.076 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.540 arrival time -0.419 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X71Y95 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C SLICE_X71Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X71Y95 FDCE (Hold_fdce_C_D) 0.076 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.541 arrival time -0.420 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X71Y95 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C SLICE_X71Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X71Y95 FDCE (Hold_fdce_C_D) 0.076 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.541 arrival time -0.420 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.278 -0.570 SLICE_X15Y62 FDCE 0.000 -0.570 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C SLICE_X15Y62 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.373 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.606 -0.341 clock pessimism -0.229 -0.570 SLICE_X15Y62 FDCE (Hold_fdce_C_D) 0.076 -0.494 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.494 arrival time -0.373 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.278 -0.570 SLICE_X15Y62 FDCE 0.000 -0.570 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C SLICE_X15Y62 FDCE (Prop_fdce_C_Q) 0.141 -0.429 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.373 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.606 -0.341 clock pessimism -0.229 -0.570 SLICE_X15Y62 FDCE (Hold_fdce_C_D) 0.076 -0.494 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.494 arrival time -0.373 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[0]/C (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.284ns (logic 0.141ns (49.624%) route 0.143ns (50.376%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X65Y96 FDRE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[0]/C SLICE_X65Y96 FDRE (Prop_fdre_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[0]/Q net (fo=1, routed) 0.143 -0.330 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIA0 SLICE_X64Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.213 -0.598 SLICE_X64Y95 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA ------------------------------------------------------------------- required time 0.451 arrival time -0.330 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[0]/C (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.284ns (logic 0.141ns (49.624%) route 0.143ns (50.376%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.234 -0.614 SLICE_X65Y96 FDRE 0.000 -0.614 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[0]/C SLICE_X65Y96 FDRE (Prop_fdre_C_Q) 0.141 -0.473 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[0]/Q net (fo=1, routed) 0.143 -0.330 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIA0 SLICE_X64Y95 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.213 -0.598 SLICE_X64Y95 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA ------------------------------------------------------------------- required time 0.451 arrival time -0.330 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMA ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 f u_regfile/rf_reg_r1_0_31_24_29/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMA ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMA_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 f u_regfile/rf_reg_r1_0_31_24_29/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMA_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMB ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 f u_regfile/rf_reg_r1_0_31_24_29/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMB ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMB_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 f u_regfile/rf_reg_r1_0_31_24_29/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMB_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMC ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 f u_regfile/rf_reg_r1_0_31_24_29/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMC ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMC_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 f u_regfile/rf_reg_r1_0_31_24_29/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMC_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMS32 r u_regfile/rf_reg_r1_0_31_24_29/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMD ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMS32 f u_regfile/rf_reg_r1_0_31_24_29/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMD ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMS32 r u_regfile/rf_reg_r1_0_31_24_29/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMD_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.348 -0.501 SLICE_X13Y17 FDRE 0.000 -0.501 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMS32 f u_regfile/rf_reg_r1_0_31_24_29/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.677 -0.270 clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMD_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X69Y91 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.542 arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X69Y91 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X69Y91 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.542 arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X73Y93 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C SLICE_X73Y93 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X73Y93 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.542 arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X73Y93 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C SLICE_X73Y93 FDCE (Prop_fdce_C_Q) 0.141 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X73Y93 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.542 arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X67Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C SLICE_X67Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0] SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.229 -0.616 SLICE_X67Y96 FDCE (Hold_fdce_C_D) 0.075 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.541 arrival time -0.419 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X67Y96 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C SLICE_X67Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0] SLICE_X67Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.229 -0.616 SLICE_X67Y96 FDCE (Hold_fdce_C_D) 0.075 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.541 arrival time -0.419 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X67Y95 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[0] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.075 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.541 arrival time -0.419 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X67Y95 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[0] SLICE_X67Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.075 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.541 arrival time -0.419 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X71Y95 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C SLICE_X71Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X71Y95 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.542 arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X71Y95 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C SLICE_X71Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.229 -0.617 SLICE_X71Y95 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.542 arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.278 -0.570 SLICE_X15Y62 FDCE 0.000 -0.570 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C SLICE_X15Y62 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.373 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.606 -0.341 clock pessimism -0.229 -0.570 SLICE_X15Y62 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.495 arrival time -0.373 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.278 -0.570 SLICE_X15Y62 FDCE 0.000 -0.570 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C SLICE_X15Y62 FDCE (Prop_fdce_C_Q) 0.141 -0.429 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.373 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.606 -0.341 clock pessimism -0.229 -0.570 SLICE_X15Y62 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.495 arrival time -0.373 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.568ns Clock Pessimism Removal (CPR): 0.231ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.280 -0.568 SLICE_X9Y59 FDCE 0.000 -0.568 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C SLICE_X9Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] SLICE_X9Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism -0.231 -0.568 SLICE_X9Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.493 arrival time -0.371 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.568ns Clock Pessimism Removal (CPR): 0.231ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.280 -0.568 SLICE_X9Y59 FDCE 0.000 -0.568 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C SLICE_X9Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] SLICE_X9Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism -0.231 -0.568 SLICE_X9Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.493 arrival time -0.371 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_cpu/axi_bridge/awaddr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.568ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.280 -0.568 SLICE_X17Y58 FDRE 0.000 -0.568 r u_cpu/axi_bridge/awaddr_reg[1]/C SLICE_X17Y58 FDRE (Prop_fdre_C_Q) 0.141 -0.427 r u_cpu/axi_bridge/awaddr_reg[1]/Q net (fo=1, routed) 0.116 -0.311 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 SLICE_X16Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.214 -0.553 SLICE_X16Y60 RAMD32 (Hold_ramd32_CLK_I) 0.120 -0.433 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.433 arrival time -0.311 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_cpu/axi_bridge/awaddr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.568ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.280 -0.568 SLICE_X17Y58 FDRE 0.000 -0.568 r u_cpu/axi_bridge/awaddr_reg[1]/C SLICE_X17Y58 FDRE (Prop_fdre_C_Q) 0.141 -0.427 f u_cpu/axi_bridge/awaddr_reg[1]/Q net (fo=1, routed) 0.116 -0.311 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 SLICE_X16Y60 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.214 -0.553 SLICE_X16Y60 RAMD32 (Hold_ramd32_CLK_I) 0.120 -0.433 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.433 arrival time -0.311 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.123ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.263ns (logic 0.164ns (62.300%) route 0.099ns (37.700%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X48Y94 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[1]/C SLICE_X48Y94 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[1]/Q net (fo=1, routed) 0.099 -0.345 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/DIB1 SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism -0.212 -0.592 SLICE_X46Y93 RAMD32 (Hold_ramd32_CLK_I) 0.124 -0.468 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1 ------------------------------------------------------------------- required time 0.468 arrival time -0.345 ------------------------------------------------------------------- slack 0.123 Slack (MET) : 0.123ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.263ns (logic 0.164ns (62.300%) route 0.099ns (37.700%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.240 -0.608 SLICE_X48Y94 FDCE 0.000 -0.608 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[1]/C SLICE_X48Y94 FDCE (Prop_fdce_C_Q) 0.164 -0.444 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[1]/Q net (fo=1, routed) 0.099 -0.345 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/DIB1 SLICE_X46Y93 RAMD32 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.567 -0.380 clock pessimism -0.212 -0.592 SLICE_X46Y93 RAMD32 (Hold_ramd32_CLK_I) 0.124 -0.468 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1 ------------------------------------------------------------------- required time 0.468 arrival time -0.345 ------------------------------------------------------------------- slack 0.123 Slack (MET) : 0.123ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.303ns (logic 0.141ns (46.480%) route 0.162ns (53.520%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.278ns Source Clock Delay (SCD): -0.510ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.339 -0.510 SLICE_X19Y24 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[12]/C SLICE_X19Y24 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[12]/Q net (fo=4, routed) 0.162 -0.206 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 SLICE_X18Y25 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.669 -0.278 clock pessimism -0.196 -0.474 SLICE_X18Y25 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.330 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC ------------------------------------------------------------------- required time 0.330 arrival time -0.206 ------------------------------------------------------------------- slack 0.123 Slack (MET) : 0.123ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.303ns (logic 0.141ns (46.480%) route 0.162ns (53.520%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.278ns Source Clock Delay (SCD): -0.510ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.339 -0.510 SLICE_X19Y24 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[12]/C SLICE_X19Y24 FDRE (Prop_fdre_C_Q) 0.141 -0.369 f u_cpu/u_csr/csr_tlbelo1_reg[12]/Q net (fo=4, routed) 0.162 -0.206 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 SLICE_X18Y25 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.669 -0.278 clock pessimism -0.196 -0.474 SLICE_X18Y25 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.330 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC ------------------------------------------------------------------- required time 0.330 arrival time -0.206 ------------------------------------------------------------------- slack 0.123 Slack (MET) : 0.125ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__16/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.483ns (logic 0.186ns (38.497%) route 0.297ns (61.503%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.476ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.147 -0.702 SLICE_X79Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__16/C SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__16/Q net (fo=118, routed) 0.297 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[304] SLICE_X85Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[833]_i_1/I2 SLICE_X85Y156 LUT4 (Prop_lut4_I2_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[833]_i_1/O net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833]_0 SLICE_X85Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.471 -0.476 clock pessimism 0.040 -0.436 SLICE_X85Y156 FDCE (Hold_fdce_C_D) 0.092 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833] ------------------------------------------------------------------- required time 0.344 arrival time -0.219 ------------------------------------------------------------------- slack 0.125 Slack (MET) : 0.125ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__16/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.483ns (logic 0.186ns (38.497%) route 0.297ns (61.503%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.476ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.147 -0.702 SLICE_X79Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__16/C SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__16/Q net (fo=118, routed) 0.297 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[304] SLICE_X85Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[833]_i_1/I2 SLICE_X85Y156 LUT4 (Prop_lut4_I2_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[833]_i_1/O net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833]_0 SLICE_X85Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.471 -0.476 clock pessimism 0.040 -0.436 SLICE_X85Y156 FDCE (Hold_fdce_C_D) 0.092 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833] ------------------------------------------------------------------- required time 0.344 arrival time -0.219 ------------------------------------------------------------------- slack 0.125 Slack (MET) : 0.445ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.906ns (logic 0.185ns (20.413%) route 0.721ns (79.587%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X67Y102 FDCE 0.000 -0.682 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.339 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 SLICE_X68Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X68Y94 FDCE (Remov_fdce_C_CLR) -0.129 -0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg ------------------------------------------------------------------- required time 0.221 arrival time 0.224 ------------------------------------------------------------------- slack 0.445 Slack (MET) : 0.445ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.906ns (logic 0.185ns (20.413%) route 0.721ns (79.587%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X67Y102 FDCE 0.000 -0.682 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.339 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 SLICE_X68Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X68Y94 FDCE (Remov_fdce_C_CLR) -0.129 -0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg ------------------------------------------------------------------- required time 0.221 arrival time 0.224 ------------------------------------------------------------------- slack 0.445 Slack (MET) : 0.518ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.725ns (logic 0.185ns (25.518%) route 0.540ns (74.482%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X67Y102 FDCE 0.000 -0.682 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.158 0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X68Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism 0.040 -0.346 SLICE_X68Y99 FDCE (Remov_fdce_C_CLR) -0.129 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0] ------------------------------------------------------------------- required time 0.475 arrival time 0.043 ------------------------------------------------------------------- slack 0.518 Slack (MET) : 0.518ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.725ns (logic 0.185ns (25.518%) route 0.540ns (74.482%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X67Y102 FDCE 0.000 -0.682 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.158 0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X68Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism 0.040 -0.346 SLICE_X68Y99 FDCE (Remov_fdce_C_CLR) -0.129 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1] ------------------------------------------------------------------- required time 0.475 arrival time 0.043 ------------------------------------------------------------------- slack 0.518 Slack (MET) : 0.518ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.725ns (logic 0.185ns (25.518%) route 0.540ns (74.482%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X67Y102 FDCE 0.000 -0.682 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.158 0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X68Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism 0.040 -0.346 SLICE_X68Y99 FDCE (Remov_fdce_C_CLR) -0.129 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2] ------------------------------------------------------------------- required time 0.475 arrival time 0.043 ------------------------------------------------------------------- slack 0.518 Slack (MET) : 0.543ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.725ns (logic 0.185ns (25.518%) route 0.540ns (74.482%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X67Y102 FDCE 0.000 -0.682 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.158 0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X69Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism 0.040 -0.346 SLICE_X69Y99 FDCE (Remov_fdce_C_CLR) -0.154 -0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[0] ------------------------------------------------------------------- required time 0.500 arrival time 0.043 ------------------------------------------------------------------- slack 0.543 Slack (MET) : 0.543ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.725ns (logic 0.185ns (25.518%) route 0.540ns (74.482%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X67Y102 FDCE 0.000 -0.682 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.158 0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X69Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.561 -0.386 clock pessimism 0.040 -0.346 SLICE_X69Y99 FDCE (Remov_fdce_C_CLR) -0.154 -0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[2] ------------------------------------------------------------------- required time 0.500 arrival time 0.043 ------------------------------------------------------------------- slack 0.543 Slack (MET) : 0.568ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_wready_reg/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.774ns (logic 0.185ns (23.892%) route 0.589ns (76.108%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X67Y102 FDCE 0.000 -0.682 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.207 0.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X72Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_wready_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.040 -0.347 SLICE_X72Y98 FDCE (Remov_fdce_C_CLR) -0.129 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_wready_reg ------------------------------------------------------------------- required time 0.476 arrival time 0.092 ------------------------------------------------------------------- slack 0.568 Slack (MET) : 0.568ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_last_l_reg/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.774ns (logic 0.185ns (23.892%) route 0.589ns (76.108%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X67Y102 FDCE 0.000 -0.682 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.207 0.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X72Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_last_l_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.040 -0.347 SLICE_X72Y98 FDCE (Remov_fdce_C_CLR) -0.129 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_last_l_reg ------------------------------------------------------------------- required time 0.476 arrival time 0.092 ------------------------------------------------------------------- slack 0.568 Slack (MET) : 0.591ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.185ns (23.221%) route 0.612ns (76.779%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X67Y102 FDCE 0.000 -0.682 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.230 0.115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X70Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.040 -0.347 SLICE_X70Y98 FDCE (Remov_fdce_C_CLR) -0.129 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[1] ------------------------------------------------------------------- required time 0.476 arrival time 0.115 ------------------------------------------------------------------- slack 0.591 Slack (MET) : 0.595ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_awready_reg/PRE (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.185ns (23.221%) route 0.612ns (76.779%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X67Y102 FDCE 0.000 -0.682 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.230 0.115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X70Y98 FDPE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_awready_reg/PRE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.040 -0.347 SLICE_X70Y98 FDPE (Remov_fdpe_C_PRE) -0.133 -0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_awready_reg ------------------------------------------------------------------- required time 0.480 arrival time 0.115 ------------------------------------------------------------------- slack 0.595 Slack (MET) : 0.632ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_bvalid_reg/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.838ns (logic 0.185ns (22.085%) route 0.653ns (77.915%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.166 -0.682 SLICE_X67Y102 FDCE 0.000 -0.682 r pll_clk.u_rst_mlkem/delay_reg[1]/C SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.271 0.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X72Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_bvalid_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism 0.040 -0.347 SLICE_X72Y99 FDCE (Remov_fdce_C_CLR) -0.129 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_bvalid_reg ------------------------------------------------------------------- required time 0.476 arrival time 0.156 ------------------------------------------------------------------- slack 0.632 Slack (MET) : 0.746ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X8Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism -0.192 -0.529 SLICE_X8Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.596 arrival time 0.150 ------------------------------------------------------------------- slack 0.746 Slack (MET) : 0.746ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X8Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism -0.192 -0.529 SLICE_X8Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.596 arrival time 0.150 ------------------------------------------------------------------- slack 0.746 Slack (MET) : 0.746ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X8Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism -0.192 -0.529 SLICE_X8Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.596 arrival time 0.150 ------------------------------------------------------------------- slack 0.746 Slack (MET) : 0.746ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X8Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism -0.192 -0.529 SLICE_X8Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.596 arrival time 0.150 ------------------------------------------------------------------- slack 0.746 Slack (MET) : 0.746ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X8Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism -0.192 -0.529 SLICE_X8Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.596 arrival time 0.150 ------------------------------------------------------------------- slack 0.746 Slack (MET) : 0.746ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X8Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism -0.192 -0.529 SLICE_X8Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.596 arrival time 0.150 ------------------------------------------------------------------- slack 0.746 Slack (MET) : 0.771ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X9Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism -0.192 -0.529 SLICE_X9Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.621 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.621 arrival time 0.150 ------------------------------------------------------------------- slack 0.771 Slack (MET) : 0.771ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r pll_clk.u_rst_cpu/delay_reg[1]/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 r pll_clk.u_rst_cpu/reset_i_1/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X9Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.610 -0.337 clock pessimism -0.192 -0.529 SLICE_X9Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.621 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.621 arrival time 0.150 ------------------------------------------------------------------- slack 0.771 Slack (MET) : 0.793ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.717ns (logic 0.246ns (34.327%) route 0.471ns (65.673%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.184 0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X73Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X73Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.693 arrival time 0.099 ------------------------------------------------------------------- slack 0.793 Slack (MET) : 0.793ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.717ns (logic 0.246ns (34.327%) route 0.471ns (65.673%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.184 0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X73Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X73Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.693 arrival time 0.099 ------------------------------------------------------------------- slack 0.793 Slack (MET) : 0.793ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.717ns (logic 0.246ns (34.327%) route 0.471ns (65.673%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.184 0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X73Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X73Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.693 arrival time 0.099 ------------------------------------------------------------------- slack 0.793 Slack (MET) : 0.798ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.722ns (logic 0.246ns (34.065%) route 0.476ns (65.935%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.190 0.106 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X67Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X67Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.692 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.692 arrival time 0.106 ------------------------------------------------------------------- slack 0.798 Slack (MET) : 0.798ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.722ns (logic 0.246ns (34.065%) route 0.476ns (65.935%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.190 0.106 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X67Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X67Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.692 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.692 arrival time 0.106 ------------------------------------------------------------------- slack 0.798 Slack (MET) : 0.798ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.722ns (logic 0.246ns (34.065%) route 0.476ns (65.935%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.190 0.106 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X67Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X67Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.692 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.692 arrival time 0.106 ------------------------------------------------------------------- slack 0.798 Slack (MET) : 0.798ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.722ns (logic 0.246ns (34.065%) route 0.476ns (65.935%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.190 0.106 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X67Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X67Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.692 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.692 arrival time 0.106 ------------------------------------------------------------------- slack 0.798 Slack (MET) : 0.805ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.724ns (logic 0.246ns (33.995%) route 0.478ns (66.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.352 0.179 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.606 -0.341 clock pessimism -0.192 -0.533 SLICE_X15Y62 FDCE (Remov_fdce_C_CLR) -0.092 -0.625 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.625 arrival time 0.179 ------------------------------------------------------------------- slack 0.805 Slack (MET) : 0.805ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.724ns (logic 0.246ns (33.995%) route 0.478ns (66.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.352 0.179 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.606 -0.341 clock pessimism -0.192 -0.533 SLICE_X15Y62 FDCE (Remov_fdce_C_CLR) -0.092 -0.625 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.625 arrival time 0.179 ------------------------------------------------------------------- slack 0.805 Slack (MET) : 0.805ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.724ns (logic 0.246ns (33.995%) route 0.478ns (66.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.352 0.179 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.606 -0.341 clock pessimism -0.192 -0.533 SLICE_X15Y62 FDCE (Remov_fdce_C_CLR) -0.092 -0.625 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.625 arrival time 0.179 ------------------------------------------------------------------- slack 0.805 Slack (MET) : 0.805ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.724ns (logic 0.246ns (33.995%) route 0.478ns (66.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.352 0.179 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.606 -0.341 clock pessimism -0.192 -0.533 SLICE_X15Y62 FDCE (Remov_fdce_C_CLR) -0.092 -0.625 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.625 arrival time 0.179 ------------------------------------------------------------------- slack 0.805 Slack (MET) : 0.805ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.724ns (logic 0.246ns (33.995%) route 0.478ns (66.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.352 0.179 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.606 -0.341 clock pessimism -0.192 -0.533 SLICE_X15Y62 FDCE (Remov_fdce_C_CLR) -0.092 -0.625 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.625 arrival time 0.179 ------------------------------------------------------------------- slack 0.805 Slack (MET) : 0.805ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.724ns (logic 0.246ns (33.995%) route 0.478ns (66.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.352 0.179 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.606 -0.341 clock pessimism -0.192 -0.533 SLICE_X15Y62 FDCE (Remov_fdce_C_CLR) -0.092 -0.625 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.625 arrival time 0.179 ------------------------------------------------------------------- slack 0.805 Slack (MET) : 0.813ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.760ns (logic 0.246ns (32.373%) route 0.514ns (67.627%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.227 0.144 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X65Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.192 -0.577 SLICE_X65Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.669 arrival time 0.144 ------------------------------------------------------------------- slack 0.813 Slack (MET) : 0.813ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.760ns (logic 0.246ns (32.373%) route 0.514ns (67.627%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.227 0.144 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X65Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.192 -0.577 SLICE_X65Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.669 arrival time 0.144 ------------------------------------------------------------------- slack 0.813 Slack (MET) : 0.813ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.760ns (logic 0.246ns (32.373%) route 0.514ns (67.627%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.227 0.144 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X65Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.192 -0.577 SLICE_X65Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.669 arrival time 0.144 ------------------------------------------------------------------- slack 0.813 Slack (MET) : 0.813ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.760ns (logic 0.246ns (32.373%) route 0.514ns (67.627%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.227 0.144 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X65Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.192 -0.577 SLICE_X65Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.669 arrival time 0.144 ------------------------------------------------------------------- slack 0.813 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.847ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X13Y59 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X13Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.622 arrival time 0.225 ------------------------------------------------------------------- slack 0.847 Slack (MET) : 0.847ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X13Y59 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X13Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.622 arrival time 0.225 ------------------------------------------------------------------- slack 0.847 Slack (MET) : 0.847ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X13Y59 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X13Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.622 arrival time 0.225 ------------------------------------------------------------------- slack 0.847 Slack (MET) : 0.847ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X13Y59 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X13Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.622 arrival time 0.225 ------------------------------------------------------------------- slack 0.847 Slack (MET) : 0.857ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.829ns (logic 0.246ns (29.675%) route 0.583ns (70.325%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.296 0.260 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X12Y58 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X12Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.597 arrival time 0.260 ------------------------------------------------------------------- slack 0.857 Slack (MET) : 0.857ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.829ns (logic 0.246ns (29.675%) route 0.583ns (70.325%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.296 0.260 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X12Y58 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X12Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.597 arrival time 0.260 ------------------------------------------------------------------- slack 0.857 Slack (MET) : 0.857ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.829ns (logic 0.246ns (29.675%) route 0.583ns (70.325%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.296 0.260 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X12Y58 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X12Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.597 arrival time 0.260 ------------------------------------------------------------------- slack 0.857 Slack (MET) : 0.857ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.829ns (logic 0.246ns (29.675%) route 0.583ns (70.325%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.279 -0.569 SLICE_X8Y60 FDCE 0.000 -0.569 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.296 0.260 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X12Y58 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.609 -0.338 clock pessimism -0.192 -0.530 SLICE_X12Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 0.597 arrival time 0.260 ------------------------------------------------------------------- slack 0.857 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.246ns (30.872%) route 0.551ns (69.128%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.264 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X73Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.693 arrival time 0.179 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.246ns (30.872%) route 0.551ns (69.128%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.264 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X73Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.693 arrival time 0.179 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.246ns (30.872%) route 0.551ns (69.128%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.264 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X73Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.693 arrival time 0.179 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.246ns (30.872%) route 0.551ns (69.128%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.264 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X73Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.693 arrival time 0.179 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.246ns (30.872%) route 0.551ns (69.128%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.264 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X73Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.693 arrival time 0.179 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.246ns (30.872%) route 0.551ns (69.128%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.264 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X73Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.693 arrival time 0.179 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.970%) route 0.548ns (69.030%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.262 0.177 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/buffers_0_reg[3] SLICE_X71Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.216 -0.604 SLICE_X71Y96 FDCE (Remov_fdce_C_CLR) -0.092 -0.696 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.696 arrival time 0.177 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.970%) route 0.548ns (69.030%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.262 0.177 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/buffers_0_reg[3] SLICE_X71Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.216 -0.604 SLICE_X71Y96 FDCE (Remov_fdce_C_CLR) -0.092 -0.696 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.696 arrival time 0.177 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.970%) route 0.548ns (69.030%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.262 0.177 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/buffers_0_reg[3] SLICE_X71Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.216 -0.604 SLICE_X71Y96 FDCE (Remov_fdce_C_CLR) -0.092 -0.696 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.696 arrival time 0.177 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[3]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.970%) route 0.548ns (69.030%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.262 0.177 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/buffers_0_reg[3] SLICE_X71Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.216 -0.604 SLICE_X71Y96 FDCE (Remov_fdce_C_CLR) -0.092 -0.696 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 0.696 arrival time 0.177 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.875ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.858%) route 0.578ns (70.142%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.291 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X66Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X66Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.667 arrival time 0.208 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.875ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.858%) route 0.578ns (70.142%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.291 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X66Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X66Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.667 arrival time 0.208 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.875ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.858%) route 0.578ns (70.142%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.291 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X66Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X66Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.667 arrival time 0.208 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.875ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.858%) route 0.578ns (70.142%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.291 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X66Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X66Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.667 arrival time 0.208 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.875ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.858%) route 0.578ns (70.142%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.291 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X66Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X66Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.667 arrival time 0.208 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.875ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.858%) route 0.578ns (70.142%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.291 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X66Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.560 -0.387 clock pessimism -0.213 -0.600 SLICE_X66Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.667 arrival time 0.208 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.877ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.846%) route 0.578ns (70.154%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.292 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.192 -0.577 SLICE_X65Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.669 arrival time 0.208 ------------------------------------------------------------------- slack 0.877 Slack (MET) : 0.877ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.846%) route 0.578ns (70.154%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.292 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.192 -0.577 SLICE_X65Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.669 arrival time 0.208 ------------------------------------------------------------------- slack 0.877 Slack (MET) : 0.877ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.846%) route 0.578ns (70.154%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.292 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.192 -0.577 SLICE_X65Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.669 arrival time 0.208 ------------------------------------------------------------------- slack 0.877 Slack (MET) : 0.877ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.846%) route 0.578ns (70.154%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.232 -0.616 SLICE_X68Y94 FDCE 0.000 -0.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.292 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.562 -0.385 clock pessimism -0.192 -0.577 SLICE_X65Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 0.669 arrival time 0.208 ------------------------------------------------------------------- slack 0.877 Slack (MET) : 0.898ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X14Y61 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.192 -0.531 SLICE_X14Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.598 arrival time 0.299 ------------------------------------------------------------------- slack 0.898 Slack (MET) : 0.898ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X14Y61 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.192 -0.531 SLICE_X14Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.598 arrival time 0.299 ------------------------------------------------------------------- slack 0.898 Slack (MET) : 0.898ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X14Y61 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.192 -0.531 SLICE_X14Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.598 arrival time 0.299 ------------------------------------------------------------------- slack 0.898 Slack (MET) : 0.898ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X14Y61 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.192 -0.531 SLICE_X14Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.598 arrival time 0.299 ------------------------------------------------------------------- slack 0.898 Slack (MET) : 0.905ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.828ns (logic 0.246ns (29.723%) route 0.582ns (70.277%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.295 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X71Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.558 -0.389 clock pessimism -0.213 -0.602 SLICE_X71Y92 FDCE (Remov_fdce_C_CLR) -0.092 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.694 arrival time 0.210 ------------------------------------------------------------------- slack 0.905 Slack (MET) : 0.905ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.828ns (logic 0.246ns (29.723%) route 0.582ns (70.277%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.295 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X71Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.558 -0.389 clock pessimism -0.213 -0.602 SLICE_X71Y92 FDCE (Remov_fdce_C_CLR) -0.092 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.694 arrival time 0.210 ------------------------------------------------------------------- slack 0.905 Slack (MET) : 0.905ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.828ns (logic 0.246ns (29.723%) route 0.582ns (70.277%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.295 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X71Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.558 -0.389 clock pessimism -0.213 -0.602 SLICE_X71Y92 FDCE (Remov_fdce_C_CLR) -0.092 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.694 arrival time 0.210 ------------------------------------------------------------------- slack 0.905 Slack (MET) : 0.905ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.828ns (logic 0.246ns (29.723%) route 0.582ns (70.277%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.295 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X71Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.558 -0.389 clock pessimism -0.213 -0.602 SLICE_X71Y92 FDCE (Remov_fdce_C_CLR) -0.092 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.694 arrival time 0.210 ------------------------------------------------------------------- slack 0.905 Slack (MET) : 0.913ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.837ns (logic 0.246ns (29.384%) route 0.591ns (70.616%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.305 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X71Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.693 arrival time 0.220 ------------------------------------------------------------------- slack 0.913 Slack (MET) : 0.913ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.837ns (logic 0.246ns (29.384%) route 0.591ns (70.616%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.305 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X71Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.693 arrival time 0.220 ------------------------------------------------------------------- slack 0.913 Slack (MET) : 0.913ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.837ns (logic 0.246ns (29.384%) route 0.591ns (70.616%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.305 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X71Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.693 arrival time 0.220 ------------------------------------------------------------------- slack 0.913 Slack (MET) : 0.913ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.837ns (logic 0.246ns (29.384%) route 0.591ns (70.616%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.305 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X71Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.693 arrival time 0.220 ------------------------------------------------------------------- slack 0.913 Slack (MET) : 0.913ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.837ns (logic 0.246ns (29.384%) route 0.591ns (70.616%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.305 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X71Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.693 arrival time 0.220 ------------------------------------------------------------------- slack 0.913 Slack (MET) : 0.913ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.837ns (logic 0.246ns (29.384%) route 0.591ns (70.616%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.231 -0.617 SLICE_X70Y96 FDCE 0.000 -0.617 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.305 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.559 -0.388 clock pessimism -0.213 -0.601 SLICE_X71Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.693 arrival time 0.220 ------------------------------------------------------------------- slack 0.913 Slack (MET) : 0.915ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[106]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.785ns (logic 0.213ns (27.129%) route 0.572ns (72.871%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.676 SLICE_X56Y104 FDCE 0.000 -0.676 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/I1 SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.455 0.109 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X61Y115 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[106]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.189 -0.647 SLICE_X61Y115 FDCE (Remov_fdce_C_CLR) -0.159 -0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[106] ------------------------------------------------------------------- required time 0.806 arrival time 0.109 ------------------------------------------------------------------- slack 0.915 Slack (MET) : 0.915ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[138]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.785ns (logic 0.213ns (27.129%) route 0.572ns (72.871%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.676 SLICE_X56Y104 FDCE 0.000 -0.676 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/I1 SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.455 0.109 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X61Y115 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[138]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.189 -0.647 SLICE_X61Y115 FDCE (Remov_fdce_C_CLR) -0.159 -0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[138] ------------------------------------------------------------------- required time 0.806 arrival time 0.109 ------------------------------------------------------------------- slack 0.915 Slack (MET) : 0.915ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[170]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.785ns (logic 0.213ns (27.129%) route 0.572ns (72.871%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.676 SLICE_X56Y104 FDCE 0.000 -0.676 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/I1 SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.455 0.109 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X61Y115 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[170]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.189 -0.647 SLICE_X61Y115 FDCE (Remov_fdce_C_CLR) -0.159 -0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[170] ------------------------------------------------------------------- required time 0.806 arrival time 0.109 ------------------------------------------------------------------- slack 0.915 Slack (MET) : 0.915ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[195]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.785ns (logic 0.213ns (27.129%) route 0.572ns (72.871%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.676 SLICE_X56Y104 FDCE 0.000 -0.676 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/I1 SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.455 0.109 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X61Y115 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[195]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.189 -0.647 SLICE_X61Y115 FDCE (Remov_fdce_C_CLR) -0.159 -0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[195] ------------------------------------------------------------------- required time 0.806 arrival time 0.109 ------------------------------------------------------------------- slack 0.915 Slack (MET) : 0.919ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[168]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.788ns (logic 0.213ns (27.025%) route 0.575ns (72.975%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.028ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.459ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.676 SLICE_X56Y104 FDCE 0.000 -0.676 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/I1 SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.458 0.112 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X59Y116 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[168]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.488 -0.459 clock pessimism -0.189 -0.648 SLICE_X59Y116 FDCE (Remov_fdce_C_CLR) -0.159 -0.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[168] ------------------------------------------------------------------- required time 0.807 arrival time 0.112 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.919ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[8]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.788ns (logic 0.213ns (27.025%) route 0.575ns (72.975%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.028ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.459ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.676 SLICE_X56Y104 FDCE 0.000 -0.676 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/I1 SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.458 0.112 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X59Y116 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.488 -0.459 clock pessimism -0.189 -0.648 SLICE_X59Y116 FDCE (Remov_fdce_C_CLR) -0.159 -0.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[8] ------------------------------------------------------------------- required time 0.807 arrival time 0.112 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.921ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[107]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.213ns (26.784%) route 0.582ns (73.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.676 SLICE_X56Y104 FDCE 0.000 -0.676 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/I1 SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.465 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X56Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[107]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.210 -0.668 SLICE_X56Y117 FDCE (Remov_fdce_C_CLR) -0.134 -0.802 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[107] ------------------------------------------------------------------- required time 0.802 arrival time 0.119 ------------------------------------------------------------------- slack 0.921 Slack (MET) : 0.921ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[108]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.213ns (26.784%) route 0.582ns (73.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.676 SLICE_X56Y104 FDCE 0.000 -0.676 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/I1 SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.465 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X56Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[108]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.210 -0.668 SLICE_X56Y117 FDCE (Remov_fdce_C_CLR) -0.134 -0.802 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[108] ------------------------------------------------------------------- required time 0.802 arrival time 0.119 ------------------------------------------------------------------- slack 0.921 Slack (MET) : 0.921ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[73]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.213ns (26.784%) route 0.582ns (73.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.676 SLICE_X56Y104 FDCE 0.000 -0.676 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/I1 SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.465 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X56Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[73]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.210 -0.668 SLICE_X56Y117 FDCE (Remov_fdce_C_CLR) -0.134 -0.802 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[73] ------------------------------------------------------------------- required time 0.802 arrival time 0.119 ------------------------------------------------------------------- slack 0.921 Slack (MET) : 0.921ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[75]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.213ns (26.784%) route 0.582ns (73.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.172 -0.676 SLICE_X56Y104 FDCE 0.000 -0.676 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/I1 SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.465 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X56Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[75]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.489 -0.458 clock pessimism -0.210 -0.668 SLICE_X56Y117 FDCE (Remov_fdce_C_CLR) -0.134 -0.802 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[75] ------------------------------------------------------------------- required time 0.802 arrival time 0.119 ------------------------------------------------------------------- slack 0.921 Slack (MET) : 0.923ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X15Y61 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.192 -0.531 SLICE_X15Y61 FDCE (Remov_fdce_C_CLR) -0.092 -0.623 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.623 arrival time 0.299 ------------------------------------------------------------------- slack 0.923 Slack (MET) : 0.923ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X15Y61 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.192 -0.531 SLICE_X15Y61 FDCE (Remov_fdce_C_CLR) -0.092 -0.623 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.623 arrival time 0.299 ------------------------------------------------------------------- slack 0.923 Slack (MET) : 0.923ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.304 -0.544 SLICE_X6Y63 FDCE 0.000 -0.544 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X15Y61 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.608 -0.339 clock pessimism -0.192 -0.531 SLICE_X15Y61 FDCE (Remov_fdce_C_CLR) -0.092 -0.623 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.623 arrival time 0.299 ------------------------------------------------------------------- slack 0.923